CONTENTS
1.4 Hardware–Software Partitioning
1.7.5 Hardware–Software Partitioning
2.2.5 Congruences of Polynomial
3.2.1 Sign-Magnitude Representation
3.2.3 B's Complement Representation
4 Arithmetic Operations: Addition and Subtraction
4.1 Addition of Natural Numbers
4.1.5 Long-Multioperand Addition
4.2 Subtraction of Natural Numbers
4.3.2 B's Complement Sign Change
4.3.3 B's Complement Subtraction
4.3.4 B's Complement Overflow Detection
4.3.5 Excess-E Addition and Subtraction
4.3.6 Sign–Magnitude Addition and Subtraction
5 Arithmetic Operations: Multiplication
5.1 Natural Numbers Multiplication
5.1.2 Shift and Add Algorithms
5.1.2.3 Extended Shift and Add Algorithm: XY + C + D
5.1.2.4 Cellular Shift and Add
5.2.1 B's Complement Multiplication
5.2.1.1 Mod Bn+m B's Complement Multiplication
5.2.1.3 Postcorrection B's Complement Multiplication
5.2.2 Postcorrection 2's Complement Multiplication
5.2.3 Booth Multiplication for Binary Numbers
5.2.3.2 Per Gelosia Signed-Digit Algorithm
5.2.4 Booth Multiplication for Base-B Numbers (Booth-r Algorithm in Base B)
5.3.1.1 Cellular Carry–Save Squaring Algorithm
6 Arithmetic Operations: Division
6.2.2 Restoring Division Algorithm
6.2.3 Base-2 Nonrestoring Division Algorithm
6.2.5 SRT Radix-2 Division with Stored-Carry Encoding
6.2.8 Base-B Nonrestoring Division Algorithm
6.3 Convergence (Functional Iteration) Algorithms
6.3.2 Newton–Raphson Iteration Technique
6.3.3 MacLaurin Expansion—Goldschmidt's Algorithm
7.2 Residue Number System Conversion
7.2.2 Base-B to RNS Conversion
7.2.3 RNS to Base-B Conversion
7.3 Logarithmic, Exponential, and Trigonometric Functions
7.3.2 Polynomial Approximation
7.3.3 Logarithm and Exponential Functions Approximation by Convergence Methods
7.3.3.1 Logarithm Function Approximation by Multiplicative Normalization
7.3.3.2 Exponential Function Approximation by Additive Normalization
7.3.4 Trigonometric Functions—CORDIC Algorithms
7.4.1 Digit Recurrence Algorithm—Base-B Integers
7.4.2 Restoring Binary Shift-and-Subtract Square Rooting Algorithm
7.4.3 Nonrestoring Binary Add-and-Subtract Square Rooting Algorithm
7.4.4 Convergence Method—Newton–Raphson
8.1.3.2 Modified Shift-and-Add Algorithm
8.1.3.3 Montgomery Multiplication
8.3.1 Addition and Subtraction
Appendix 8.1 Computation of fki
9.1 Design Methods for Electronic Systems
9.1.1 Basic Blocks of Integrated Systems
9.1.2 Recurring Topics in Electronic Design
9.1.2.1 Design Challenge: Optimizing Design Metrics
9.1.2.2 Cost in Integrated Circuits
9.2 Instruction Set Processors
9.2.3 Embedded Processors Everywhere
9.2.4 Digital Signal Processors
9.2.5 Application-Specific Instruction Set Processors
9.2.6 Programming Instruction Set Processors
9.3.2.2 Standard-Cell-Based ASIC
9.4.1 Programmable Logic Devices (PLDs)
9.4.2 Field Programmable Gate Array (FPGA)
9.4.2.1 Why FPGA? A Short Historical Survey
9.4.3.1 Configurable Logic Blocks (CLBs)
9.4.3.2 Input/Output Blocks (IOBs)
9.4.3.5 Arithmetic Resources in Xilinx FPGAs
9.4.4 FPGA Generic Design Flow
9.5 Hardware Description Languages (HDLs)
9.5.1 Today's and Tomorrow's HDLs
10 Circuit Synthesis: General Principles
10.2 Precedence Relation and Scheduling
11.1.1 Basic Adder (Ripple-Carry Adder)
11.1.4 Optimization of Carry-Skip Adders
11.1.7 Optimization of Carry-Select Adders
11.1.8 Carry-Lookahead Adders (CLAs)
11.1.10 FPGA Implementation of Adders
11.1.10.3 Experimental Results
11.1.12.1 Sequential Multioperand Adders
11.1.12.2 Combinational Multioperand Adders
11.1.13 Subtractors and Adder-Subtractors
11.1.15 FPGA Implementation of the Termination Detection
11.2.1 B's Complement Adders and Subtractors
11.2.2 Excess-E Adders and Subtractors
11.2.3 Sign-Magnitude Adders and Subtractors
12.1.3 Cellular Multiplier Arrays
12.1.3.1 Ripple-Carry Multiplier
12.1.3.2 Carry-Save Multiplier
12.1.4 Multipliers Based on Dissymmetric Br × Bs Cells
12.1.5 Multipliers Based on Multioperand Adders
12.1.6 Per Gelosia Multiplication Arrays
12.1.6.2 Adding Tree for Base-B Partial Products
12.1.7 FPGA Implementation of Multipliers
12.2.1 B's Complement Multipliers
12.2.2.3 Signed-Digit Multiplier
12.2.3 FPGA Implementation of the Booth-1 Multiplier
13.2.1 Base-2 Nonrestoring Divider
13.2.2 Base-B Nonrestoring Divider
13.2.3.2 SRT-2 Divider with Carry-Save Computation of the Remainder
13.2.3.3 FPGA Implementation of the Carry-Save SRT-2 Divider
13.2.5.1 Newton–Raphson Divider
13.2.5.3 Comparative Data Between Newton–Raphson (NR) and Goldschmidt (G) Implementations
14.1.1 General Base Conversion
14.1.2 BCD to Binary Converter
14.1.2.1 Nonrestoring 2p Subtracting Implementation
14.1.2.2 Shift-and-Add BCD to Binary Converter
14.1.3 Binary to BCD Converter
14.1.4 Base-B to RNS Converter
14.1.5 CRT RNS to Base-B Converter
14.1.6 RNS to Mixed-Radix System Converter
14.2 Polynomial Computation Circuits
14.5 Sine and Cosine Operators
14.6.1 Restoring Shift-and-Subtract Square Rooter (Naturals)
14.6.2 Nonrestoring Shift-and-Subtract Square Rooter (Naturals)
14.6.3 Newton–Raphson Square Rooter (Naturals)
15 Circuits for Finite Field Operations
15.1.2.3 Montgomery Multiplication
15.1.2.4 Modulo (Bk−c) Reduction
16.1 Floating-Point System Definition
16.2.1 Addition of Positive Numbers
16.2.2 Difference of Positive Numbers