14.4 EXPONENTIAL OPERATOR

This section presents an implementation for binary exponential computation using additive normalization, as described in Section 7.3.3.2. The implementation of Algorithm 7.9, presented in Figure 14.18, is somewhat similar to the preceding one. It also handles binary coded data and results; the same look-up tables are required to read out the numerical values of (1 + 2⁻ⁱ), (1 − 2⁻ⁱ), ln (1 + 2⁻ⁱ), and ln (1 − 2⁻ⁱ). Nevertheless, the argument X is now in [− 1, 1[, so to implement the auxiliary sequence computations, a signed-number subtractor is needed. As the main sequence (computing e^x) starts with 1 and always multiplies by positive numbers (1 ± 2⁻ⁱ), the multiplier device can be simpler, dealing with natural numbers only. Figure 14.18 assumes a 2's complement coding for the argument X, so the first bit of x(i) may be used to control the multiplexers selecting the LUT outputs. The X register requires a length corresponding to the desired precision, plus some additional bits (not represented) to cope with rounding errors. As quoted in Chapter 7, the sign of x(i) can be used to select the candidate values to subtract (auxiliary sequence) and to multiply (main sequence) but a further comparison is needed to proceed. This comparison ensures that x(i) will either decrease or stay unchanged after each step. A specific comparison circuit (comp. circuit) can be designed to compare the absolute values of 2.x(i) and ln c(i); c(i) = 1 + 2⁻ⁱ if x₀(i) ≥ 0, c(i) = 1 − 2⁻ⁱ otherwise. If ln c(i) is smaller or equal to 2.x(i), then ln c(i) is subtracted from x(i) while y(i) is multiplied by c(i); otherwise the operations are neutralized: subtracting 0 from x(i) and multiplying y(i) by 1. For that purpose, the output of comp. circuit is used to control the multiplexers located at the respective inputs of the subtractor and multiplier. According to the assumptions of Example 7.10 (Section 7.3.3.2), x(0) = X and y(0) = 1, the steps are numbered from 0 to p − 1, while x(i + 1) and y(i + 1) are computed at step i. After step i = p − 1, a final multiplication of y(p) by (1 + x(p)) doubles the precision. This operation, appropriately timed, is materialized in figure 14.18 by a signed adder connected to the output of register X. The output of this adder is connected to the multiplier through a multiplexer (muxp) controlled by C(p): C(p) = 1 at step p.

Figure 14.18 Exponential computation circuit using additive normalization.

As in the preceding implementation circuit, a counter (not represented) may be used to generate step number i. During the second phase of clock pulse i, registers X and acc are loaded with x(i + 1) and y(i + 1), respectively. At step p, register acc only has to be loaded, while the control input of multiplexer muxp is set to C(p) = 1. The final result is stored in register acc after step p:

Observe that the stop condition test (x(i) = 0 ?), which is optional, is not represented in Figure 14.18.

The cost and computation time are given by

where the delay T_multiplier(2.p) of the multiplier is assumed greater that the one of the subtractor.