A basic divider deduced from algorithm 16.6 is shown in Figure 16.9. The inputs of the (p + 1)-digit divider are s1/B and s2 (Comment 6.1), so that the dividend is smaller than the divisor. The precision is chosen equal to p + 3 digits. Thus (see Section 6.1) the outputs quotient and remainder satisfy the relation
The sticky digit is equal to 1 if r > 0 and to 0 if r = 0. The final approximation of the exact result is
Example 16.9 (Complete VHDL code available.) Generate the VHDL model of a generic floating-point divider. It is made up of three blocks:
1. Division. This block includes the (p + 2)-digit divider, the subtractor, the xor gate, and the sticky digit generation circuit. Any type of divider can be used (Chapter 13). In this model a modified (dividend = s1/B) restoring divider has been used:
entity division is port ( s1, s2: in digit_vector(0 downto -p); signl, sign2: in std_logic; e1, e2: in integer; s: out digit_vector(0 downto -(p+3)); sign: out std_logic; e: out integer ); end division; architecture circuit of division is component modif_div_rest_baseB…end component; … end circuit;
2. Normalization. This circuit multiplies the quotient by B, and decreases the exponent accordingly, if the quotient is smaller than 1:
entity normalization is port ( e: in natural; s: in digit_vector(0 downto -(p+3)); new_s: out digit_vector(0 downto -(p+3)); new_e: out natural ); end normalization; architecture rtl of normalization is signal quotient_by_B: digit_vector(0 downto -(p+3)); begin multiply_by_B: for i in -(p+2) to 0 generate quotient_by_B(i)<=s(i-1); end generate; quotient_by_B(-(p+3))<=0; new_s<=quotient_by_B when s(0)=0 else s; new_e<=e-1 when s(0)=0 else e; end rtl;
3. Rounding. The rounding circuit is the same as before, or even simpler (it is not necessary to normalize after rounding):
entity rounding is port ( s: in digit_vector(0 downto -(p+3)); e: in natural; new_s: out digit_vector(0 downto -p); new_e: out natural ); end rounding;
It remains to assemble the three parts:
entity fp_divider is port ( sign1, sign2: in std_logic; e1, e2: in integer; s1, s2: in digit_vector(0 downto -p); sign: out std_logic; e: out natural; s: out digit_vector(0 downto -p) ); end fp_divider; architecture circuit of fp_divider is component division…end component; component normalization…end component; component rounding…end component; signal e_d, e_n: natural; signal s_d, s_n: digit_vector(0 downto -(p+3)); begin divider_component: division port map (s1, s2, sign1, sign2, e1, e2, s_d, sign, e_d); normalization_component: normalization port map (e_d, s_d, s_n, e_n); rounding_component: rounding port map (s_n, e_n, s, e); end circuit;