9.3 ASIC DESIGNS

Application-specific integrated circuits (ASICs) refer to those integrated circuits specifically built for preset tasks. Why use an ASIC solution instead of another off-the-shelf technology—programmable logic device (PLD, FPGA), or a microprocessor/microcontroller system? There are, indeed, many advantages in ASICs with respect to other solutions: increased speed, lower power consumption, lower cost (for mass production), better design security (difficult reverse engineering), better control of I/O characteristics, and more compact board design (less complex PCB, less inventory costs). However, there are important disadvantages: long turn-around time from silicon vendors (several weeks), expensive for low-volume production, very high NRE cost (high investment in CAD tools, workstations, and engineering manpower), and, finally, once committed to silicon the design cannot be changed.

Application-specific components can be classified into full-custom ASICs, semi custom ASICs, and field programmable ICs (Figure 9.10). This latter, sometimes referred to as programmable ASICs, will be analyzed in Section 9.4: programmable logic.

9.3.1 Full-Custom ASIC

In a full-custom ASIC all mask layers are customized (Figure 9.11). Full-custom designs offer the highest performance and the smallest die size, with the disadvantages of increased design time, higher complexity and costs, together with the highest risk of failure. This design option only makes sense when neither libraries nor IP cores are available, or when very high performances are required. Time after time, fewer projects are really “full-custom,” because of the very high cost and the prohibitively slow time-to-market. Most of the full-custom works are related to library cell generation or minor parts of a full design. Examples of full-custom IC specific parts are high-voltage (automobile, avionic), analog processing and analog/digital communication devices, sensors and transducers. Traditionally, microprocessors and memories were exclusively full-custom, but the industry is increasingly turning to semicustom ASIC techniques in these areas too.

Figure 9.10 Application-specific components.

Figure 9.11 In a full-custom design every layer must be defined.

9.3.2 Semicustom ASIC

In order to reduce the unaffordable cost of full custom in most projects, a wide variety of design approaches have been developed to shorten design time, cut down costs, and automate the processes. These approaches are commonly called semicustom. Semicustom designs are performed at logic (gate) level. As such, they lose some of the flexibility available from a full-custom fashion—that is the price paid for a much easier design technique. Semicustom solutions can be further categorized into gate array and standard cell.

9.3.2.1 Gate-Array ASIC

Gate arrays (GAs) are basically composed of continuous arrays of p- and n-type transistors. The silicon vendor provides master or base wafers, to be then personalized according to the interconnection information supplied by the customer. Therefore, the designer supplies the personalized information that defines the connections between transistors in the gate array. Although a gate array standardizes the chip at the geometry level, user interaction is still typically carried out at logic level. The mapping, from transistors to gates, is performed through an ad hoc CAD tool. The gate array (also called masked gate array, or prediffused array) uses library components and macros that reduce the development time. Two main types of gate arrays can be mentioned: channeled and channelless (Figure 9.12). In a channeled gate array, the interconnections are drawn within predefined spaces (channels) between rows of logic cells. In a channelless gate array (channelfree gate array or sea-of-gates), there are no connection channels; the connections are drawn with the upper metal layers, that is, on the top of the logic cells. In both cases, only some mask layers (the upper ones) must be customized.

Figure 9.12 Gate array architectures: channeled and channelless gate arrays.

9.3.2.2 Standard-Cell-Based ASIC

Standard cells are logic components (e.g., gates, multiplexers, adders, flip-flops) previously designed and stored in a library. A design is created using these library cells as inputs to a CAD system: logic schematic diagram or hardware description language (HDL) code description. Next, a further CAD tool automatically converts the design into a chip layout. Standard-cell designs are typically organized on the chip, as rows of constant height cells (Figure 9.13). Together with logic-level component cells, standard-cell systems typically offer-higher-level functions such as multipliers and memory arrays. This allows the use of predesigned (or automatically generated) high-level components to complete the design.

Figure 9.13 Typical standard cell layout.

9.3.3 Design Flow in ASIC

Figure 9.14 shows a typical semicustom ASIC design flow (excepted for the test vector generation). The steps in a traditional ASIC design flow (with a brief description) are:

• Design Entry: enters the design using either a hardware description language such as VHDL or Verilog (see Section 9.5) or a schematic entry.
• Logic Synthesis: from the HDL or schematic entry, extracts a netlist, that is, a description of the logic cells and their connections. The synthesis tool can infer a hardware implementation with the behavior as the HDL description.
• System Partitioning: divides a large system into ASIC-sized pieces.
• Prelayout (Behavioral) Simulation: checks the circuit working.
• Floorplanning: arranges the different blocks of the circuit on the chip.
• Placement: sets the cell locations in a block.
• Routing: creates the connections between cells and blocks.

  

  Figure 9.14 ASIC design flow.

• Extraction (Back Annotation): determines the resistance and capacitance of the interconnections and calculates delays for simulation purposes.
• Postlayout (Physical) Simulation: checks the circuit working after including the delays created by interconnection loads.
• Design Rule Check (DRC): verifies that the circuit layout complies with the specifications of the design rules. DRC tools can range from a simple physical spacing check-up to complex tests.