5.11. Queue-Based System Topologies
Queue-based system topologies maximize the performance of systems built with multiple processors. Use of queues greatly increases concurrency by creating many unshared connections between and among processors. These multiple unshared connections support multiple transactions per clock on multiple and split queues. Figures 5.14–5.16 illustrate several FIFO-based architectural configurations for multiple-processor systems. Figure 5.15 shows a simple system with one FIFO linking two processors. Figure 5.16 shows a FIFO driving other FIFOs to increase I/O concurrency while accommodating dissimilar processing rates of the receiving processors. Figure 5.17 shows a FIFO with address bits selectively driving other FIFOs. The address bits steer the data to the appropriate receiving FIFO.
Figure 5.15. A FIFO memory between producing and consuming processors equalizes bursty transfers from and to the processors.
Figure 5.17. One FIFO built from separate address and data FIFOs can automatically and selectively separate out merged data streams containing data intended for different individual FIFOs.
As a result of their extremely high connectivity levels, Xtensa and Diamond processors permit the development of many new and interesting system topologies that substantially boost an SOC’s processing performance. For example, Figure 5.18 shows the block diagram of a wireless audio/video receiver built from four processors. All four processors perform flow-through tasks and there is FIFO buffering between all of the processors to smooth data flow.
Figure 5.18. Some applications, such as this wireless audio/video receiver, are especially well suited to FIFO-based system architectures.
