2.5. Computational Alternatives

There are several alternatives for executing high-performance tasks without resorting to stratospheric clock rates. These alternatives include tuning a configurable processor, splitting the task across more than one processor, and using or implementing a hardware block to perform the task. Each of these alternatives is quite viable and each should be carefully evaluated to make the most appropriate choice given overall system requirements.

Tuning a configurable processor allows the design team to retain the programmability and flexibility of a firmware-based computing element while adding parallel, programmable execution units to the processor to boost performance without raising clock rate. The industry is starting to use the term ASIP (application-specific instruction-set processor) to refer to such an augmented processor. In essence, developing an ASIP superficially resembles RTL hardware development in its addition of hardware execution units using a hardware-description language. But it differs markedly from RTL design by retaining the processor’s firmware programmability, which permits state machines to be implemented in firmware. The next chapter in this book discusses this design approach in much more detail.

Splitting the high-performance task across multiple processors is another viable approach. Most complex, high-performance tasks have easily identifiable subtasks that can be distributed to multiple processors and executed in parallel. For example, H.264 video decoding consists of subtasks that include bitstream parsing and decoding and pixel reconstruction using macroblocks. One PC processor running at more than 1 GHz can implement the entire H.264 decoding algorithm. However, most consumer applications that would use an H.264 decoder lack the cooling fans or power sources needed to support such a processor in a system.

The single, complex video-decoding task can be split across two tailored ASIPs: a bitstream processor and a pixel processor. This approach results in a 2-processor, firmware-programmable hardware block that performs the desired function, with the desired performance, but without the excessive clock rate or power dissipation.

The third alternative is to either reuse an existing hardware block or develop a new one to implement the desired function. If such a hardware block already exists, and if it’s unlikely that the function will change in the future, then this alternative may well be the best one.