14.3. Fit the Processor to the Algorithm
Configurable, extensible processors allow developers to tailor the processor to the target algorithms. Designers can add special-purpose, variable-width registers; specialized execution units; and wide data buses to reach an optimum processor configuration for specific algorithms. They perform this work using a surprisingly small variation of the conventional development flow shown above in Figure 14.1. In addition to recoding critical routines in assembly language, a configurable processor gives the SOC development team the option of adding instructions, registers, and register files to the processor that speed critical inner loops.
This processor tailoring can occur at the same point in the software-development process as the assembly-coding step, as shown in Figure 14.2. One box (with a drop shadow for emphasis) has been added. This box represents the step where the SOC designers add processor extensions to an Xtensa processor core using the Tensilica Instruction Extension (TIE) language.
Figure 14.2. The embedded software-development process with configurable processors.
As with hand-tuned assembly language, code-optimization points for an application-tailored processor become apparent through code profiling. Optimization targets typically reside within the innermost software loops that execute many thousands or millions of times per second. Reducing the instruction count of the object code inside of these critical inner loops greatly improves system performance without raising clock rate.
The examples in the following sections show the performance improvements possible when using the TIE language to tailor Tensilica’s Xtensa processors.