10.7. Input and Output Queue Interfaces

In addition to the 32-bit input and output ports discussed in the previous section, the Diamond 570T CPU core has a 32-bit input-queue interface and a 32-bit output queue interface. These queue interfaces, respectively, connect directly to the head or tail of a FIFO memory. Each queue interface has a pair of hardware handshaking wires that automatically sequence the flow of data between the attached FIFO memory and the processor. The input-queue handshake signals are called PopReq (Pop Request) and Empty. The output-queue handshake signals are called PushReq (Push Request) and Full.

Table 10.7 lists the instructions added to the Diamond 570T CPU to manage the input and output queue interfaces.

The Diamond 570T CPU’s input- and output-queue interfaces have been designed to mate directly to synchronous FIFO devices. The queue interfaces are synchronous in that all data transfers between the Diamond 570T CPU core and the external FIFOs occur on the rising edge of the clock signal. There should be no combinational paths from PopReq to Empty in the input-queue interface logic or from PushReq to Full in the output-queue interface logic.

If an input queue becomes empty as a result of a pop request from the Diamond 570T CPU, the queue should assert its Empty signal in the next clock cycle, following the clock edge marking the data transfer. Similarly, if an output queue becomes full as a result of a push request, it should assert its Full signal in the next clock cycle after the clock edge, when it accepts the data from the processor.

The Diamond 570T CPU can assert its PopReq signal even when an input queue is empty and it can assert its PushReq signal even when an output queue is full. External queue designs must protect the queue FIFOs against input-queue underflows and output-queue overflows by ignoring the processor’s requests when an input queue is empty or when an output queue is full.

The Diamond 570T CPU core should be the only device connected to the read port of an input FIFO or the write port of an output FIFO because the Diamond core’s queue interfaces are not designed to connect to external queues that are shared between multiple clients. During normal queue operation, the status of an input queue must change from “not empty” to “empty” only in response to a pop request from the Diamond 570T CPU core. Similarly, the status of an output queue must change from “not full” to “full” only in response to a push request from the Diamond 570T CPU core. The only situation where it may be appropriate to violate this particular restriction (for both input and output queues) is during a system flush. Such a flush might occur, for example, before data processing begins on a new stream of data.

System designers must ensure that the queue interfaces are used in a manner consistent with the recommendations outlined in this section. Not doing so may result in unexpected or incorrect queue behavior.

External queues can also be connected to the Diamond 570T CPU core through its 64-bit XLMI port. To choose between the XLMI port and the queue interfaces to connect to external queues, an SOC architect should consider the following points:

• FIFO queues connected to the Diamond 570T CPU’s XLMI port are accessed via memory-mapped load and store instructions. Access to the FIFO queues attached to the processor through the output- and input-queue interfaces is through the push and pop instructions, because the queue interfaces do not exist within the processor’s address space. The designer should consider whether memory-mapped or queue push and pop operations are more appropriate for a specific application. The Diamond 570T CPU can transfer data to or from only one XLMI-attached queue during any given cycle (because there’s only one XLMI port), but it can transfer data to and from both the input and output queues during each clock cycle using slots 0 and 2 of the processor’s second 64-bit instruction-word format.

• If a FIFO queue is attached to the XLMI port, it must share that port with any other XLMI-attached devices, which may result in bandwidth issues. The Diamond 570T CPU’s queue interfaces are not shared, and therefore an external FIFO attached to a queue interface receives the full bandwidth of that interface.

• The Diamond 570T’s XLMI port is 64 bits wide and can therefore conduct 64-bit I/O transactions. The Diamond 570T CPU’s input-and output-queue interfaces are 32 bits wide, which might limit bandwidth in some applications.

• If the Diamond 570T CPU tries to read from an input queue when it’s empty, an XLMI-attached FIFO queue will stall the I/O operation. The stalled I/O read transaction will stall the processor’s pipeline as well and this stalled state is not interruptible. The queue interfaces can also stall the processor’s pipeline but interrupts can still occur and will be serviced when a queue transaction is stalled.

• If the processor executes a store to the XLMI port immediately followed by a load from an XLMI-attached FIFO queue, the store is buffered and the load occurs first. If this load causes an I/O stall because the addressed FIFO queue is empty, a resource deadlock results that will freeze the processor’s pipeline. The XLMI load cannot complete because the FIFO queue is empty and the store to the FIFO queue cannot take place because the pipeline is stalled. No such resource conflicts exist with the queue interfaces.

• All XLMI-attached devices including FIFO queues must handle speculative reads over the XLMI port. To do this, XLMI-attached devices must observe and use the processor control signals that indicate whether a read has committed or flushed. The queue interfaces do not conduct speculative operations.