8.3. The XLMI Port

Diamond processor cores, like all RISC processors, perform speculative read operations that initiate read transactions on the local-memory buses. Data obtained from these read operations may or may not be used, depending on the circumstances in the processor’s pipeline. For example, a branch instruction or interrupt can cause the processor to discard data that it has speculatively read.

Diamond processor load transactions that appear on the processor’s interface ports (with the exception of the PIF) are speculative, so a read operation on the XLMI interface signals does not necessarily mean that the processor will consume the data it reads. A variety of internal events (such as branches) and exceptions can initiate pipeline flushes that cause the processor to discard all uncompleted instructions in its pipeline, including load instructions. The processor may later replay these loads but the data obtained from the first execution of the load instruction will have been flushed. Consequently, all devices attached to the XLMI port must be designed to accommodate the speculative nature of processor read operations.

Simple RAMs do not have read side effects. FIFO memories and most I/O devices do have read side effects. For example, reading the status register of an I/O device often has an irreversible effect on the I/O device and reading a word from the head of a FIFO permanently removes that word from the FIFO. Attaching devices with read side effects to the local memory buses of Diamond processor cores will result in unpredictable and incorrect system behavior. Speculative transactions only occur on the Diamond cores’ local-memory and XLMI buses. They do not occur on the Diamond processor cores’ main PIF bus.

The Diamond 212GP processor’s XLMI port is a general-purpose data port that allows for the direct attachment of:

• RAMs

• Hardware peripherals (through memory-mapped I/O registers)

• Inter-processor communication devices (such as FIFOs)

Note: The XLMI port is a data interface only. The Diamond 212GP controller does not fetch instructions from the XLMI port.

The Diamond Standard Series XLMI port enables the proper design of interfaces to devices that have read side effects, such as FIFO memories. If a device with read side effects is connected to the XLMI port, additional external logic is required to ensure that data read from the device is not lost until the XLMI port indicates that the processor has retired the load. The speculative nature of RISC processor loads makes such interface behavior mandatory for proper system operation. The XLMI port interface eases the design of this logic by signaling when the processor completes the load operation and when the pipeline has been flushed. This XLMI port feature distinguishes it from the other Diamond processor core local-memory interfaces.

The XLMI port signals the initiation of loads (normal read cycles), the completion of loads, and the flushing of speculative loads that will not be completed. Load completion is indicated by the assertion of the “Data Port Load Retired” signal. Assertion of this signal tells the attached device that it no longer needs to maintain a copy of the data read by the associated load operation because the processor has consumed the information.

A second XLMI port signal, “Data Port Retire Flush,” indicates that the processor has discarded all unretired XLMI loads. The processor asserts this signal when pipeline conditions cause instructions in the pipeline to be flushed. Devices that have read effects have difficulty in dealing with this condition, so careful design is required. These two signals, “Data Port Load Retired” and “Data Port Retire Flush,” help SOC designers take into account the speculative nature of reads directed at the Diamond 212GP controller’s XLMI port.