15.1.3. SOC Disaster Scenario 3: Loss of Manufacturability

The current SOC-design style assumes a perfect chip. Flawed chips are simply thrown away, a decades-old practice. Memory and FPGA vendors have long designed redundant circuits in the form of extra rows and columns into their products to boost manufacturing yields. Nanometer silicon manufacturing can no longer provide the luxury of perfect chips to SOC designers.

One of the wonders of the semiconductor industry is that it has pushed manufacturing yields high enough to shield application-specific integrated circuit (ASIC) and SOC designers from the need to develop manufacturable systems for their chip designs. As system designers move to higher design-abstraction levels and become further removed from the “bare metal” circuitry of their systems, they need to devote energy toward developing system design styles that produce manufacturable designs. The classic approach to developing fault-tolerant systems is through the addition of redundant components, at the circuit level and at higher levels.

Yield is not the only manufacturability issue. Device-test time and test costs are another. Testability has always been the system designer’s unloved stepchild. In general, designers wish to design new systems, not develop ways to test them. As a result, designers of semiconductor-test equipment have had to scramble to develop increasingly innovative ways of testing larger and more complex SOCs without letting test times become completely unreasonable.

Future step functions in potential SOC logic complexity brought on by each new semiconductor process node will be accompanied by a similar, disastrous increase in SOC test times unless the system designer’s basic approach to design for testability (DFT) changes. This warning cry is now decades old, so it’s unlikely that system designers will adopt DFT methods en masse unless the DFT methods dovetail nicely with system designers’ main interest: designing shiny new and ever more powerful systems.