4.2. Xtensa Processor Block Diagram

Figure 4.2 shows a block diagram of the Xtensa processor with all of its optional and configurable components. If the Xtensa processor core was a fixed-ISA machine, every instance of the processor would need to contain all of the elements appearing in Figure 4.2, which would result in a large processor core. Such a large core would be quite powerful but it would not be a precise fit for any particular set of application tasks. Instead, the Xtensa processor core is configurable, which means that the SOC design team can develop processor cores based on the Xtensa ISA that are sized to fit the performance profiles of the various processor “sockets” in the overall system design.

The Xtensa block diagram shows many blocks common to all RISC processors including an instruction-fetch/instruction-decode unit, a load/store unit, a register file, and an ALU. Optional and configurable elements include interfaces to local instruction and data memories; interfaces to instruction and data caches; the processor’s main interface bus (called the processor interface, PIF); predefined functional execution units such as a multiplier, multiplier/accumulator, a floating-point unit (FPU), and a vector DSP unit; a second load/store unit; exceptions, interrupts, and timers; memory-management and memory-protection blocks; and trace, and debugging hardware. Table 4.1 describes some of the configurable hardware elements in the Xtensa processor core design.

In addition to the configurable elements in the Xtensa core design, designers can add registers, register files, instructions, and data ports using the TIE language to describe the desired processor extensions. Later sections in this chapter discuss TIE-based processor extensions in more detail.