13.3. On-Chip Communications for SOCs
Previous chapters in this book have discussed a number of ways to connect multiple processors together to achieve high bandwidths. Some of these include the use of bridged buses (shown in Figure 13.7) and pipelined data-flow architectures (or systolic-processing systems) using FIFO-based inter-processor communications (Figure 13.8). Many such possible architectures exist.
All of the SOC architectures shown so far are ad hoc designs. The inter-processor connections in these designs all follow the intended function of the chip. The ad hoc approach to processor connectivity can produce the most efficient interconnection amongst processors, if the data-movement requirements of the system are well understood. However, these needs are often not so well understood or they may change during the SOC’s operation. In such cases, the SOC design may need a more flexible approach to moving data among processors. One way of building such flexible connections is through on-chip networks or “networks on chip” (NoCs).