13.1. Toward a 21st-Century SOC Design Strategy
The organization that perhaps pays more attention to chip-level system-design-strategies than any other in the world is the ITRS (International Technology Roadmap for Semiconductors). The ITRS assesses all semiconductor technology requirements (for design, manufacturing, and reliability) to ensure continued global advancements in integrated circuit performance. This assessment, which produces a new industry road map every two years, is a worldwide cooperative effort of the industry’s manufacturers and suppliers, government organizations, consortia, and universities. It is the way that the semiconductor industry has chosen to map the route for the continued enforcement of Moore’s law.
The ITRS continually assesses the available design technologies, technology trends, and possible future developments that shape the way design teams develop integrated circuits, including SOCs. It produced an updated road map at the end of 2005 with many new additions. Several of these additions to the road map directly apply to the way SOCs are designed. In fact, the ITRS is extremely concerned with the way ICs are designed. Here’s a quote from the Design section of the 2005 ITRS Report on IC design:
The main message in 2005 remains—Cost (of design) is the greatest threat to continuation of the semiconductor roadmap. Cost determines whether differentiating value is best achieved in software or in hardware, on a programmable commodity platform or on a new IC. Manufacturing non-recurring engineering (NRE) costs are on the order of millions of dollars (mask set + probe card); design NRE costs routinely reach tens of millions of dollars, with design shortfalls being responsible for silicon re-spins that multiply manufacturing NRE. Rapid technology change shortens product life cycles and makes time-to-market a critical issue for semiconductor customers.
Manufacturing cycle times are measured in weeks, with low uncertainty. Design and verification cycle times are measured in months or years, with high uncertainty. Without foundry amortization and return-on-investment (ROI) for supplier industries, the semiconductor investment cycle stalls. ITRS editions prior to 2003 have documented a design productivity gap—the number of available transistors grows faster than the ability to meaningfully design them. Yet, investment in process technology has by far dominated investment in design technology.
The good news is that enabling progress in DT [design technology] continues. The estimated design cost of the power-efficient system-on-chip (SOC-PE) defined in the System Drivers chapter is near $20 M in 2005, versus around $900 M had DT innovations between 1993 and 2005 not occurred. . . . The bad news is that software can account for 80% of embedded-systems development cost; test cost has grown exponentially relative to manufacturing cost; verification engineers outnumber design engineers on microprocessor project teams; etc. Today, many design technology gaps are crises.
The ITRS assessment divides the many aspects of the design-technology crisis into two broad groups:
silicon complexity
system complexity
The issues surrounding silicon complexity relate to the physical design of a chip. Some of the physical-design challenges identified by the 2005 ITRS report include:
Non-ideal scaling of device parasitics and supply/threshold voltages (leakage, power management, circuit/device innovation, current delivery).
Coupled high-frequency devices and interconnects (noise/interference, signal integrity analysis and management, substrate coupling, delay variation due to cross-coupling).
Manufacturing variability (statistical process modeling and characterization, yield, leakage power).
Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, NRE cost).
Process variability (library characterization, analog and digital circuit performance, error-tolerant design, layout reuse, reliable and predictable implementation platforms).
Scaling of global interconnect performance relative to device performance (communication, synchronization).
Decreased reliability (gate insulator tunneling and breakdown integrity, joule heating and electromigration, single-event upset, general fault-tolerance).
The issues connected with silicon complexity threaten some long-standing IC-design paradigms:
Systemwide clock synchronization becomes infeasible due to power-dissipation limits and the rising cost of system robustness (statistical timing slack) in the face of increasing manufacturing variability.
CMOS transistors exhibit ever-larger behavioral variability.
Fabrication of perfect chips with 100% functional transistors and interconnects is becoming prohibitively expensive.
These issues connected with escalating silicon complexity result in other issues related to system complexity. The ITRS report ties on-chip system complexity directly to the exponentially increasing transistor counts produced by the semiconductor industry’s adherence to Moore’s law, which is spurred by consumer demand for increased product capabilities, lower cost, the perpetual craving—spurred by marketing—for “the new, new thing,” and increasingly global competition among system and silicon vendors.
Note that consumer demand did not always serve as the semiconductor industry’s main driver. In the 1960s and 1970s, relatively low-volume military system requirements drove much of the industry’s development. In the 1980s and 1990s, the demands of computer systems became the semiconductor industry’s leading driver. Computer systems, particularly PCs, sold in higher volumes than did the military systems and used massive quantities of certain key ICs, especially DRAMs. Only in the late 1990s did consumer electronics ascend to the leading position as the semiconductor industry’s main volume driver. The voracious demands of high-volume, consumer-product categories for low cost, good performance, and rapid improvement (to promote frequent replacement or upgrade purchases) now largely define the semiconductor industry.
These changes have severely challenged the existing, tried-and-true methods used to architect and develop electronic systems (and therefore SOCs). System complexity has exploded due to the development of increasingly advanced forms of digital media and broad consumer demand yet the system-design techniques and design styles used to develop the latest systems are often the same ones used during earlier, simpler eras.
The ITRS road map identifies many 21st-century system-design challenges including:
Block reuse and support for hierarchical design
Verification and test
Embedded software design and hardware codesign
Design process management (design team size and geographic distribution).
Any updated SOC design style must address all of these issues.