2.9. Summary: Handling SOC Complexity

Simply put, SOC design costs and design risk are rising because global competitive pressures are causing system complexity to grow exponentially. Moore’s law places relentless pressure on system design from another direction by making more transistors available to system designers every year. Moore’s law has been in place since 1960 and it will continue to be enforced for many more years, according to the ITRS. Where “system” designers of the early 1960s were designing 5- and 7-transistor radios and board-level designers in the 1980s put a few LSI (large-scale integration) chips and a few dozen medium-scale integration (MSI) components on a board to make a system, today’s SOC designers funnel tens or hundreds of millions of transistors into each chip. Increased design cost and risk inevitably accompany increased system performance and complexity.

Rising design costs and risks are not the only problem. A recent IC/ASIC functional verification study performed by Collett International Research suggests that two-thirds of all chip designs that reach volume production require two or more silicon respins. More than 80% of these designs are respun because of design errors, incomplete or incorrect specifications, or specification changes made after design begins. Functional and logic flaws are the biggest problems. Respinning a design increases design costs through the direct cost of the respin and through missed market windows that result in sales lost to competitors or simply the vagaries of time.

The MPSOC design style advocated in this chapter is a 21st-century process that reflects the realities of today’s nanometer silicon. It produces firmware-programmable SOCs that can serve as platforms. These hardware platforms can satisfy the needs of multiple products across multiple product generations through reprogrammability. The MPSOC design style does not require design teams to learn new techniques or to understand radically new component types. Further, this design style has been successfully used by dozens of companies to produce hundreds of SOC designs. Thus the advocated design style is based in practical experience. It is not academic or hypothetical.

The systematic SOC design style discussed in this chapter produces working, flexible silicon with low risk and minimal cost. That result is substantially different from the dismal state of the SOC projects discussed in the IC/ASIC functional verification report from Collett International Research. What remains is for your SOC-development team to consciously select a design style for its next project. Which will it be?