5.17. SOC Design in the 21st Century

SOC complexity continues to grow in lockstep with Moore’s law. As the number of SOC blocks continues to increase, efficient interconnection of all system blocks and system-level modeling of the resulting complex systems become ever more important. Conventional on-chip interconnection schemes (namely buses and bus hierarchies) derived from board-level system designs of the 1970s and 1980s are increasingly unattractive for global on-chip interconnection because they incur severe routing liabilities and have significant speed limitations due to growing on-chip capacitance. In addition, available design tools from EDA vendors lack support for developing complex systems using multiple processors, and that situation is unlikely to change for a variety of reasons discussed earlier.

Xtensa and Diamond processor cores have multiple on-chip buses, ports, and queues that can support both conventional and newer, more efficient system architectures. The MPSOC-design tool complements these processors by making it possible to perform high-level, SystemC simulations of subsystems and entire SOCs constructed from multiple processor cores and other large logic blocks. The Xtensa and Diamond processor cores and MPSOC allow SOC architectural design to step up to the next level of complexity while leveraging all that’s familiar and well understood in the realm of system-level and SOC design.