Chapter 6. Introduction to Diamond Standard Series Processor Cores
Heaven polishes its jewels with.
—Thomas Carlyle
With their configurability and extensibility, Tensilica’s 32-bit Xtensa microprocessor cores can perform a very wide array of SOC tasks. However, there are many on-chip tasks that do not require the processing and I/O bandwidths achievable with configurable Xtensa cores. Consequently, Tensilica has used the Xtensa ISA and the Xtensa Processor Generator to create architecturally compatible, pre-configured processor cores for specific task sets frequently encountered in SOC design.
These cores, comprising the Diamond Standard Series of pre-configured cores, offer a wide range of performance options without the need to further configure them. Diamond processor cores all employ the Xtensa ISA, so they are software compatible with the configurable Xtensa cores and use the same software-development tools. They carry on the Xtensa system-design philosophy of moving the bulk of a system’s capabilities into firmware and defining those capabilities through application code written in C or C++ as much as possible for maximum flexibility and easier system maintenance. In addition to being extremely useful system components for SOC designs, the Diamond processor cores also demonstrate several of the many interesting dimensions of Xtensa configurable-core technology.