Furber, S., “Future Trends in SOC Interconnect,” SOC 2005, Tampere, Finland, November 15–17, 2005.

Ganssle, J., “Subtract Software Costs by Adding CPUs,” Embedded Systems Design, May, 2005, pp. 16–25, http://www.embedded.com/showArticle.jhtml?articleID161600589.

Greiner, A., “Distributed Micronetwork for GALS,” SOC 2005, Tampere, Finland, November 15–17, 2005.

International Technology Roadmap for Semiconductors: 2005, http://public.itrs.net/.

Lee, S.-J., “Realization of an On-chip Network for Practical Application to System-on-Chip—A Chip Designer’s View,” SOC 2005, Tampere, Finland, November 15–17, 2005.

Leibson, S., “NOC, NOC, NOCing on heaven’s door: Beyond MPSOCs: A report from the seventh-annual International Symposium on System-on-Chip design,” EDN, December 8, 2005, http://www.edn.com/article/CA6289284.html.

Nurmi, J., “Network-on Chip: A New Paradigm for System-on-Chip Design,” SOC 2005, Tampere, Finland, November 15–17, 2005.

Smit, G., “An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip,” SOC 2005, Tampere, Finland, November 15–17, 2005.