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End User License Agreement
by Steffen Kroehnert, Beth Keser
Advances in Embedded and Fan-Out Wafer Level Packaging Technologies
Cover
Preface
List of Contributors
Acknowledgments
1 History of Embedded and Fan‐Out Packaging Technology
1.1 Introduction
1.2 First Embedding Technologies Based on MCM‐D Concepts
1.3 First Embedding Technologies Based on Organic Laminates and Flex
1.4 Helsinki University of Technology and Imbera Electronics Embedded Chips
1.5 Fraunhofer IZM/TU Berlin Chip‐in‐Polymer (CiP)
1.6 HiCoFlex, Chip‐in‐Flex, and UTCP
1.7 Conclusion
References
2 FO‐WLP Market and Technology Trends
2.1 Introduction
2.2 FO‐WLP: A Disruptive Technology
2.3 Embedded Die Packaging
2.4 FO‐WLP Advantages
2.5 FO‐WLP Versions
2.6 Challenges for FO‐WLP
2.7 Drivers for FO‐WLP
2.8 Strong Demand for FO‐WLP
References
3 Embedded Wafer‐Level Ball Grid Array (eWLB) Packaging Technology Platform
3.1 Technology Description
3.2 Basic Package Construction
3.3 Manufacturing Process Flow and BOM
3.4 System Integration Capability
3.5 Manufacturing Format and Scalability
3.6 Package Performance
3.7 Robustness and Reliability Data
3.8 Electrical Test Considerations
3.9 Applications and Markets
References
4 Ultrathin 3D FO‐WLP eWLB‐PoP (Embedded Wafer‐Level Ball Grid Array‐Package‐on‐Package) Technology
4.1 Introduction
4.2 eWLB‐MLP (Mold Laser Package‐on‐Package) Technology
4.3 3D eWLB‐PoP Technology
4.4 3D eWLB SiP/Module
4.5 Conclusions
References
5 NEPES’ Fan‐Out Packaging Technology from Single die, SiP to Panel‐Level Packaging
5.1 Introduction
5.2 Structure and Process Flow
5.3 Thin Fan‐Out Packaging
5.4 Double‐Sided Fan‐Out Packaging
5.5 Via Frame (VF) Fan‐Out Package
5.6 System‐in‐Package
5.7 Panel‐Level Package
5.8 Performance and Reliability
5.9 Application
5.10 Roadmap and Remarks
References
6 M‐Series™ Fan‐Out with Adaptive Patterning™
6.1 Technology Description
6.2 Basic Package Construction
6.3 Manufacturing Process Flow and BOM
6.4 Design Features and System Integration Capability
6.5 Adaptive Patterning
6.6 Manufacturing Format and Scalability
6.7 Robustness and Reliability Data
6.8 Electrical Test Considerations
6.9 Applications and Markets
Acknowledgment
References
7 SWIFT® Semiconductor Packaging Technology
7.1 Technology Description
7.2 Basic Package Construction
7.3 Manufacturing Process
7.4 Design Features
7.5 Manufacturing Format and Scalability
7.6 Package Performance
7.7 Thermal Performance
7.8 Robustness and Reliability Data
7.9 Applications and Markets
References
8 Embedded Silicon Fan‐Out (eSiFO®) Technology for Wafer‐Level System Integration
8.1 Technology Description
8.2 Basic Package Construction
8.3 Manufacturing Process Flow
8.4 Design Features
8.5 System Integration Capability
8.6 Manufacturing Format and Scalability
8.7 Package Performance
8.8 Robustness and Reliability Data
8.9 Applications and Markets
Acknowledgment
References
9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology
9.1 Technology Description
9.2 Basic Interposer Construction
9.3 Manufacturing Process Flow and BOM
9.4 Design Features
9.5 System Integration Capability
9.6 Manufacturing Format and Scalability
9.7 Package Performance
9.8 Robustness and Reliability Data
9.9 Electrical Test Considerations
9.10 Applications and Markets
9.11 Summary
References
10 Embedding of Power Electronic Components: The Smart p2 Pack Technology
10.1 Introduction
10.2 Technology Description p Pack
10.3 Basic Package Construction
10.4 The p Pack Technology Process Flow
10.5 Smart p Pack
10.6 Package Performance
10.7 Applications and Markets
10.8 Summary
Acknowledgments
References
11 Embedded Die in Substrate (Panel‐Level) Packaging Technology
11.1 Technology Description
11.2 Basic Package Construction
11.3 Manufacturing Process Flow and BOM
11.4 Design Features
11.5 System Integration Capability
11.6 Package Performance
11.7 Diversity of EDS Technology: Module
11.8 Diversity of EDS Technology: Power Devices
11.9 Applications and Markets
References
12 Blade: A Chip‐First Embedded Technology for Power Packaging
12.1 Technology Description
12.2 Development and Implementation
12.3 Basic Package Construction
12.4 Manufacturing Process Flow and BOM
12.5 Design Features
12.6 System Integration Capability
12.7 Manufacturing Format and Scalability
12.8 Package Performance
12.9 Robustness and Reliability Data
12.10 Electrical Test Considerations
12.11 Applications and Markets
Acknowledgments
References
13 The Role of Liquid Molding Compounds in the Success of Fan‐Out Wafer‐Level Packaging Technology
13.1 Introduction
13.2 The Necessity of Liquid Molding Compound for FO‐WLP
13.3 The Required Parameters of Liquid Molding Compound for FO‐WLP
13.4 Design of LMC Resin Formulation
13.5 Development of LMC in Connection with Latest Requirements
13.6 Current LMC Representative Proprieties
13.7 Conclusions
Acknowledgment
References
14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan‐Out Wafer‐Level Packaging (FO‐WLP)
14.1 Introduction
14.2 Brief History of PI/PBO‐Based Materials in Semiconductor Applications
14.3 Dielectric Challenges in FO‐WLP Applications
14.4 HDM Material Sets for FO‐WLP
14.5 PBO‐Gen3 (Positive‐Acting, Aqueous‐Developable Material)
14.6 PBO‐Gen3 Process Flow
14.7 PBO‐Gen3 Lithography
14.8 PBO‐Gen3 Material Properties
14.9 PBO‐Gen3 Dielectric Reliability Testing
14.10 PBO‐Gen3 Package Reliability Performance (TCT Testing at Component and Board Level)
14.11 Performance Comparison Between PBO‐Gen3 and PBO‐Gen2
14.12 PI‐Gen2 (Negative‐Acting, Solvent‐Developable Material)
14.13 PI‐Gen2 Process Flow
14.14 PI‐Gen2 Lithography
14.15 PI‐Gen2 Material Properties
14.16 PI‐Gen2 Dielectric Reliability Data
14.17 PI‐Gen2 Package Reliability Performance (Component and Board Level)
14.18 Comparison Between PBO‐Gen3 and PI‐Gen2
14.19 Summary
References
15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer‐Level Packaging
15.1 Description of Technology
15.2 Material Challenges for FO‐WLP
15.3 Material Overview
15.4 Process Flow
15.5 Material Properties
15.6 Design Rules
15.7 Reliability
15.8 Next Steps
References
16 The Role of Pick and Place in Fan‐Out Wafer‐Level Packaging
16.1 Introduction
16.2 Equipment Requirements for Fan‐Out Bonders
16.3 Avoiding Fan‐Out Bonding Pitfalls
16.4 Equipment Qualification for Fan‐Out Pick and Place
16.5 Running a Large Area Glass‐on‐Glass Process
16.6 Running a Glass‐on‐Carrier Process
16.7 Running a Reference Production Lot with Test Die
16.8 Conclusions
References
17 Process and Equipment for eWLB: Chip Embedding by Molding
17.1 Introduction
17.2 Historical Background Molding
17.3 The Molded Wafer Idea: Key for the Fan‐Out eWLB Technology
17.4 The Compression Molding Process
17.5 Principle Challenges for Chip Embedding with Compression Molding
17.6 Process Development Solutions for Principle Challenges
17.7 Compression Molding Equipment for Chip Embedding
17.8 Chip Embedding Features Achieved by Compression Molding
17.9 Conclusions and Next Steps
Acknowledgments
References
18 Tools for Fan‐Out Wafer‐Level Package Processing
18.1 Turnkey Solution for Fan‐Out Wafer‐Level Packaging
18.2 Die Placement Process and Tools for FO‐WLP
18.3 Encapsulation Tool for Large Format Encapsulation
18.4 The Test Handling and Packing Solution for Wafer‐Level Packaging and FO‐WLP
References
19 Equipment and Process for eWLB: Required PVD/Sputter Solutions
19.1 Background
19.2 Process Flow
19.3 Equipment Challenges for FO‐WLP
19.4 Equipment Developed to Overcome Challenges
19.5 Additional Equipment Features
19.6 Design Rules Related to the Equipment
19.7 Reliability
19.8 Next Steps
References
20 Excimer Laser Ablation for the Patterning of Ultra‐fine Routings
20.1 Advanced Packaging Applications and Technology Trends
20.2 The High Density Structuring Challenge
20.3 Excimer Laser Ablation Technology
20.4 Summary and Conclusion
References
21 Temporary Carrier Technologies for eWLB and RDL‐First Fan‐Out Wafer‐Level Packages
21.1 Slide‐Off Debonding for FO‐WLP
21.2 Laser Debonding: Universal Carrier Release Process for Fan‐Out Wafer Packages
21.3 Parameters Influencing DPSS Laser Debonding
Acknowledgments
References
22 Encapsulated Wafer‐Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection
22.1 Improving the Conventional WLCSP Structure
22.2 The Encapsulated WLCSP Process
22.3 Advantages of the Encapsulated WLCSP, eWLCSP
22.4 eWLCSP Reliability
22.5 Reliability of Larger eWLCSP over 6 mm × 6 mm Package Size
22.6 eWLCSP Wafer‐Level Final Test
22.7 Conclusions
References
23 Embedded Multi‐die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect
23.1 Introduction
23.2 EMIB Architecture
23.3 High Level EMIB Process Flow
23.4 EMIB Signaling
23.5 Conclusions
Acknowledgments
References
24 Interconnection Technology Innovations in2.5D Integrated Electronic Systems
24.1 Introduction
24.2 Polymer‐Enhanced TSVs
24.3 HIST
24.4 Conclusion
References
Index
End User License Agreement
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