12
Blade: A Chip‐First Embedded Technology for Power Packaging
Boris Plikat and Thorsten Scharf
Infineon Technologies AG, Regensburg, Germany
12.1 Technology Description
The name “Blade” for Infineon’s laminate chip embedding technology was chosen as the outward appearance of the very thin package bears a resemblance to the blade of a knife or a similar tool. The discrete metal–oxide–semiconductor field‐effect transistor (MOSFET) package Blade3x3 and the package of the integrated buck‐converter product DrBlade2, where Dr stands for Driver, even share the shiny metallic surface at their topsides with a typical metallic cutting blade. A buck converter is a DC‐to‐DC power converter that steps down voltage from its supply (input) to its load (output), where DC stands for direct current.
The main application field of Blade products is buck converters, e.g. for use in servers. The integrated buck converter DrBlade1 (see Figure 12.1) was branded with its high peak efficiency, the small package size (only 5 × 5 mm2) and low profile (0.5 mm), and the compact and simplified board layout that it enables. In addition, DrBlade2 comes with temperature sensing and thermal warning as well as integrated high precision load current sensing. Together with the multiphase pulse width modulation (PWM) controller from Infineon, these allow optimizing the operation of several parallel DrBlade2 in a multiphase configuration as well as protection features.
Figure 12.1 DrBlade1 with small package size and low profile of 5 × 5 × 0.5 mm3.
The first Blade product, announced by Infineon in 2013, was DrBlade1 [1]. The brand name DrBlade is a fusion of the name for the Blade technology and the well‐known DRMOS standard, a combination of a MOSFET half bridge and driver. The development of the Blade package technology was triggered by the MOSFET chip shrink when it started in the middle of the previous decade. Originally, it targeted the packaging of vertically conducting MOSFETs with a few mm2 area or even less than 1 mm2 area and about 60 μm thickness oriented facedown to the application board to achieve low parasitics. The new package technology overcomes the high contribution of wire‐bond interconnects to the product’s on‐resistance and inductivity and the limitation of clips to bigger chip sizes. Additionally, the exposed die pad on the topside allows efficient topside cooling. With changed market demands in the low voltage area, the focus changed from discrete MOSFETs to integrated DC‐to‐DC converters. For the integration of a driver chip and the two MOSFETs, the technology’s strength in terms of complex and compact redistribution with low inductance came into play. DrBlade1 with its 5 mm × 5 mm footprint hosts more silicon area than its molded wire‐bond and clip‐bond predecessor with its 6 mm × 6 mm package area.
12.2 Development and Implementation
As of 2017, Infineon has brought three Blade packages to the market. In addition to the two different integrated DC‐to‐DC converter packages of DrBlade1 and DrBlade2, a discrete MOSFET package with a 3.0 mm × 3.4 mm package size was launched. Targeting different markets, the three packages were produced in different volumes. The highest contribution to the overall volume of Blade packages stems from the youngest product DrBlade2.
The Blade package technology merges conventional packaging technology and printed circuit board (PCB) technology. Furthermore, it contains dedicated chip embedding process steps. The use of a copper lead frame and the diffusion solder or glue die attach are also part of conventional power package technologies, and the package separation by mechanical dicing is similar to the process used for molded array packages assembled in strip format. Although the lead frame already has certain functionality in terms of redistribution, the Blade package technology can be classified as chip‐first embedding technology, because the actual embedding and dominant part of the redistribution are realized with PCB processes after die attach.
12.3 Basic Package Construction
The basic package construction is described in this section. Figure 12.2 shows a schematic cross section of the DrBlade1 package mainly indicating the different materials, but not to scale. The actual dimensions can be inferred from the SEM cross section given in Figure 12.3.
Figure 12.2 Schematic cross section of DrBlade1; the color codes indicate the materials used.
Figure 12.3 SEM image of a mechanical cross section through a DrBlade1 package.
Besides the laminate layers, the copper lead frame makes up the dominant volume of the package. With 250 μm thickness at DrBlade1, it accounts for about half of the package thickness. Its shape reveals that it is an etched lead frame. Laterally, the die pads and leads are electrically insulated to each other by laminate epoxy resin and its filler particles. Resin and fillers were pressed out of the surrounding prepreg, layers of uncured glass fiber reinforced epoxy, above and below the lead frame during the first lamination step to fill these cavities. Hence, there are no glass fibers in these areas except for those slightly bent into the lead frame’s etched openings. Areas without glass fibers are also the cutout regions of the prepreg around the dies and the etched areas of the redistribution layers (RDLs) (see Figure 12.3). All lamination layers used in this package contain glass fibers.
The lead frame, the last metal of the die pads, the vias, the RDLs, and footprint of the package are all made of copper (Cu) with Cu‐to‐Cu interconnects. Hence, there is no driving force for any diffusion or phase formation at the corresponding interfaces, contributing to the high reliability of the Blade package technology. Only the diffusion solder die attach, final finish, and bumping – if applicable – establish interfaces of the package to other metals than copper.
The Blade packages contain two via sizes. The small about 70 μm thick via type connects the chip pads, two adjacent RDLs, and the lead frame to the footprint layer. The ~120 μm thick via type connects the first RDL over the die to the closest lead frame side. These large vias are needed because of the vertical current flow through the MOSFETs. In DrBlade1 only, they also serve as interconnect elements from the package topside to the leads.
The die attach layers with low bond line thickness of a few μm for the diffusion solder are almost invisible in the cross section in Figure 12.3. The low bond line thickness supports the low package Ron and Rth and enables thin chip die attach. The not shown glue die attach layer of the driver chip is slightly thicker, which has to be counterbalanced by a thinner chip. The well‐defined bond line thickness and correspondingly low die tilt as well as die thickness are essential for the chip embedding process, as the surrounding geometry of layers and micro‐vias limits the degrees of freedom.
All segments of the lead frame of DrBlade1 and DrBlade2 have an exposed part to the package surface at the dicing street. Originally, they form one metal body to keep all parts in their position before the laminate material connects them after the first lamination process. Only at package dicing is the lead frame cut through, and hence has exposed surfaces. Although these are at different electrical potentials, for the addressed products operating at low voltage, this is not an issue. Nevertheless, the process flow can be adapted to create insulated sidewalls of the packages as well. This would be needed for high voltage products to ensure sufficient creepage distances.
The cross sections of DrBlade1 (Figure 12.2) and also the micro‐computer tomography (μ‐CT) picture in Figure 12.4 illustrate that every electrical potential to be connected from the topside of the package to the footprint requires an individual lead (or pad) of the lead frame. This adds complexity to the package construction and consumes package area.
Figure 12.4 μ‐CT image of DrBlade1, topside view.
The DrBlade2 package (see Figure 12.5) trades the symmetry of a redistribution on both sides to improve this drawback, as the lead frame is not located between the die and the footprint toward the application board, but above the die. The larger vias are only needed to carry the vertical current flow of the MOSFETs.
Figure 12.5 Schematic cross section of the DrBlade2 package.
Obviously, the lead frame makes the Blade package a one‐sided package with limitations for the integration of components on the package top or package‐on‐package (PoP) solutions. Although terminals can easily be created on both package sides, the electrical path through the lead frame layer needs big vias, dedicated pads on the lead frame, and therefore package area. This usually limits the topside to low pin count connections, like passives.
Chip embedding laminate packages without lead frames are technically feasible and already in the market [2]. Not only to carry electrical current but also for thermal reasons, vias can be connected to the backsides of the die. Care must be taken with applications depending on a low package Ron and a high thermal impedance or heat spreading capability within the package, if the lead frame is omitted.
However, without the lead frame, the laminate chip embedding package becomes a true double‐sided package. With a copper via interconnect on both sides of the die, it can contain die with different orientation (“face‐up/face‐down”). A laminate chip embedding package without lead frame is basically symmetric with regard to interconnects and redistribution on package top and bottom side. This is the base for a much higher flexibility in terms of its 3D capability and enables more stacked configurations (PoP, passives on top) compared with the Blade package technology. Basically the two laminate chip embedding technologies, with and without lead frame, both address different specific points for their respective application. While the technology without lead frame has advantages in terms of 3D capability, the Blade technology with lead frame has superior high current and high thermal performance.
With typical minimum line/space widths of roughly 60 μm/60 μm at typically about 35 μm thickness of the RDLs, the Blade package technology is made to realize DC‐to‐DC converters with load currents of 60 A and more. Compared with eWLB‐like embedding technologies, fields of application and design rules are complementary. Pitches, cross sections of traces, and cooling options are much smaller in these technologies.
12.4 Manufacturing Process Flow and BOM
12.4.1 Manufacturing Equipment
The production line for the Infineon Blade technology consists of a mixture of a few semiconductor packaging machines and several PCB production machines (see Figure 12.6). The die bond process follows classical approaches for solder and glue die bonding, modified for the diffusion soldering. Also, the dicing and testing is done with standard machines, although large production formats require some special consideration. Standard PCB machines, on the other hand, are horizontal wet benches for cleaning, roughening, and develop, etch, strip (DES). Also, resist lamination, laser drilling, and FR‐4, a standard laminate material with flame retardant grade 4, and precut prepreg lamination are done in typical PCB line equipment, with moderate adaptions to allow the high requirements for quality and traceability. The precutting of the prepreg is done with a laser cutter or mechanical driller. For the Cu plating, a vertical plating line with more than 10 different steps is applied, which can be divided into desmear, activation, and via filling. The requirements for the process are higher than for typical PCB processes, especially as two different via geometries are filled at the same time. This requires a much higher effort in control of the bath performance, making an automatic analysis and dosing system advantageous.
Figure 12.6 Process flow overview.
In general, the lithographic exposure can be done with standard masks or foils, but a mask‐less exposure has significant advantages for the assembly flow.
12.4.2 Basic BOM
The material inside the Infineon Blade package is a mix of classical packaging material and PCB material. The main component material is copper. A lead frame of typical thickness for small power packages of ~250 μm and all RDLs, pads, and micro‐vias consist of Cu. Cu on the top or bottom surface is covered with NiP/Au as solderable finish. In between the Cu, high‐glass transition temperature (Tg) FR‐4 material is used. Also special for power packages is the Au‐containing diffusion solder die lead frame interconnect, which makes the whole device lead‐free and green according to the Restriction of Hazardous Substances (RoHS) (EU directive).
12.4.3 Wafer/Die/Assembly Preparation
The Infineon Blade technology was developed as a thin chip package. While test vehicles were built with more than 200 μm thick chips, the main focus definitely is on the thickness range below 100 μm total chip thickness. This implies that one major preparation step is the thinning of the chip. A new challenge for the thinning process is the tight tolerance. While for usual packages their wires are bonded on the die surface, allowing a wide chip height tolerance, a chip in the Blade technology has to fit in a tight space [3]. This limits the process window for the chip thickness and requires unusual awareness for the grinding processes.
Another central point is the chip metallization. For technologies that embed in laminate, Cu pads are more or less unavoidable. The high heat capacity and high reflectivity at IR wavelengths combined with a sufficiently high melting temperature make it a performant laser stop layer for via drilling. On the other hand, it provides chemical robustness and avoids unnecessary material interfaces with the micro‐vias, which are Cu anyhow. Many tests were done with differing metallization. They always faced problems with insufficient robustness to the intense use of different aggressive chemicals or poor adhesion of the laminate or even the micro‐vias.
Open Cu areas are attacked by the adhesion‐promoting step, a Cu roughening. This etch has to be considered in the planning of the pad thickness. To avoid damage during laser drilling, the minimal Cu thickness at the micro‐via positions has to be planned thoroughly, including process variations, reductions by etching, and testing needle imprints. In summary, there is never too much Cu [3].
For the rear side of the chip, diffusion solder was chosen to achieve a very thin, stable bond line thickness with extreme electrical and thermal performance. The respective metallization has to be applied.
Special care has to be taken for the die separation, as very thin chips with thick metals tend to chip, crack, and break. Therefore, dicing blades and feed speed have to be selected carefully. For some versions, laser dicing was also applied.
12.4.4 Die Attach and Adhesion Promotion
Attaching die to a lead frame with solder is typical in the semiconductor assembly industry. Very thin die and diffusion solder are advanced, yet not unknown. Where the die have to be insulated from the lead frame potential, a standard glue die bonding with thin insulating glue was used.
After the die bonding, the adhesion‐promoting step follows (see Figure 12.6). For this, a Cu roughening is done as it is known from the PCB industry. Unfortunately, the lead frame material, which is rolled Cu, has a different, slower roughening behavior than the chip metallization. Therefore, the roughening step has to compromise between sufficient adhesion on the lead frame and not too deep etching on the chip.
A major challenge of chip embedding in laminate is the design rules of the chip pad sizes. While for wire bonding bond pad openings significantly below 100 μm are well known, this is currently not possible with the Blade technology, where 180 μm is a typical value. An enormous contributor to the needed area is the tolerance chain of the micro‐via positioning as well as the mere size of the via of 70 μm. The first can be strongly reduced by measuring the die positions before lamination and later correction of the micro‐via positions. By this, the tolerance chain is reduced to the single measurement error and the distortion of the panel during lamination. The position data is stored for later use.
12.4.5 PCB Processes
The next step is the lamination of the chip and lead frame into the FR‐4 material. For this, the prepreg layers, which are at chip height, are cut out at the die positions by laser cutting or mechanical drilling. A stencil is put between the lead frames and the first stack is built up including several prepreg layers and Cu foils. This is then pressed as in standard laminate substrate and PCB manufacturing.
The chips are contacted by forming vertical electrical interconnects. For this, different PCB via formation technologies can be selected like dual beam laser drilling, direct laser drilling (including a black oxide process), or lithographic definition of the micro‐via positions in the Cu layer and CO2 drilling through the laminate afterward. It was mentioned before that the adaptation of the via positions to the die positions is highly advantageous for the narrowing of design rules. Therefore, lithography should be done with mask‐less tools and laser drilling with individualized drilling positions for each chip. Having a fixed mask would not align to individual die positions and would hence impact yield, cause much worse design rules, or in the worst case of not properly adapted design rules cause fails in the field. No matter which process is used, the software landscape as well as the machine capability to do a lot to lot correction for the individual die positions is complex.
In all cases, the final step of drilling through the laminate toward the chip is done with a CO2 laser. The advantage of this wavelength is the almost full reflection at the Cu surfaces, which allows for a safe process without chip damage [3].
Another complex process step is the galvanic Cu deposition in the laser‐formed vias mentioned above, which can be divided into desmear, activation, and filling. The desmear process, a cleaning of the laser drilled holes to remove debris, can be done chemically or with plasma, the activation either by a palladium (Pd) activation or a direct plating approach. Also for the filling, different suppliers offer solutions that differ more by the chemical approach than by the result. The most significant difference between a standard PCB and the Blade process is the filling of two different via geometries at the same time (parallel process). This is only solvable by careful process selection. A perfect filling of vias would result in a completely flat surface above. Higher filling results in small elevations above the vias, lower filling in so‐called dimples. At this point it has to be carefully and individually considered, which via shape is necessary and at which point neither quality nor function is harmed. The whole range of shapes was thoroughly tested for robustness. Therefore, certain compromises in the dimple shape could be released.
After via plating, the RDL already reaches its final thickness. Now it can be lithographically structured to form pads and conductive traces. For this, standard PCB exposure equipment and mask‐less exposure are possible. The high value per area supports investment in machines, which can deliver a high yield. The development of the lithographic structures is done in a standard DES horizontal line.
Depending on the complexity of the product, these steps can be done on only one side or both sides of the panel and can also be repeated to form additional RDLs.
For the finish of the Blade technology, several approaches are followed, depending on the needs of the specific product. The simplest one just applies a final finish, typically e‐less NiP/Au. It could be shown that also other finishes work well. In some configurations, where the pads can be electrically connected during plating and later be separated, e.g. at package dicing, even galvanic plating like Ni/Sn can be applied.
The more complicated approach adds an additional half RDL by applying a solder resist. This would result in a negative standoff of the pads, which is challenging for the soldering behavior on board. Therefore, an additional solder depot is applied by solder printing and reflow at DrBlade2 (see Figure 12.7) and Blade3x3. DrBlade1 is without solder resist and bumps but has Ni/Au plated copper terminals.
Figure 12.7 Top and bottom views of DrBlade2 (left) and DrBlade1 (right).
After this the individual packages are separated by mechanical dicing. Several process flows were successfully introduced for different products. Dicing on standard dicing tape on wafer frames allows parallel probe card testing afterward (test of components still on wafer frame), while tapeless dicing requires single device handling into the tester. Also, the laser marking can be done in frame or on the single device. Finally, the products are packed into tape and reel.
12.4.6 Inspection and Process Controls
To ensure a high product quality and extremely low failure rate, a very high rate of process control is used. This includes an automated optical inspection (AOI) after every lithography step. The final inspection is done from all six sides and measures the specified package outline. For the other processes, controls on a statistical basis are applied. The line was set up to allow for a full backward traceability from the final product back to the position on the panel and back to the chip on the front‐end wafer. For high process stability, special care on the galvanic baths is necessary, realized by an automated analysis and dose system.
12.5 Design Features
12.5.1 Mature Design Rules and Roadmap
Qualified products are produced in a range from about 3 mm × 3 mm to 4.5 mm × 6 mm. On the test vehicle level, devices as small as 2 mm × 2 mm and as large as 11 mm × 11 mm were tested. For special purposes, even 30 mm × 35 mm was demonstrated [4, 5]. The thickness of a Blade package is typically in the range of 500 μm and above, depending on the number of layers, the chip thickness, and, very importantly, the application of solder depots. The naming therefore sometimes results in USON or UIQFN (ultrathin: >500 and ≤650 μm) or WIQFN (very very thin: >650 and ≤800 μm) [6]. The package families of the Blade products are for DrBlade1 “Laminate Green, Ultra Integrated Quad Flat Nonleaded Package (LG‐UIQFN),” for Blade33 “Laminate Green Ultra‐thin Small Non Outline Non‐Leaded Package (LG‐USON),” and for DrBlade2 “Laminate Green, very very thin Integrated Quad Flat Nonleaded Package (LG‐WIQFN).”
Pin counts reach from 3 to ~40. So far no ball grid arrays are used as they are not typical for power packages. Pad sizes are more limited by the typical second‐level design rules.
In general there is no technological limitation for line/space design rules to be different from those of high density integration (HDI) PCB production; however, the main application for the Infineon Blade technology is for power packaging. Therefore, the focus so far was on low ohmic connections more than high density. This results in RDL thicknesses of >30 μm and line/space of 60 μm/60 μm for high volume production. Mature design rules include two RDLs on each side plus a half layer realized by solder resist. Also, asymmetric assemblies are qualified.
The minimum allowed pad size, which is contacted by micro‐vias, is 180 μm. The minimum pad pitch results from the line/space and the overlay accuracy between the layers.
12.6 System Integration Capability
12.6.1 2D and Side‐by‐Side Packaging
The first announced product of the Blade technology, DrBlade1, was a multi‐chip package, including power chips and a logic chip side‐by‐side. Complex routing can be achieved over several layers, including layers on top and bottom, which is absolutely necessary for vertical power dies, as both sides of the die have to be contacted.
12.6.2 3D and Package on Package
A basic design element of the Infineon Blade technology is vertical interconnects, realized by micro‐vias in the FR‐4 laminate toward the die and lead frame. Due to the low thickness of the packages, a PoP approach is obvious to fill the gained space. At the same time it is easy to realize if only the existing lines in the RDL have to be exposed at the required positions and need a solderable surface. 3D chip stacking is not part of the Blade package technology design features and would imply a much higher complexity in laminate chip embedding technology than a PoP approach. The piggyback package on package as well as passives on top of packages was demonstrated. A typical application also uses a large inductor bridging over the package, not electrically connecting the topside of the same. This saves almost the complete board space of the package itself, and at the same time the inductor aids as a heat sink for the power die.
12.7 Manufacturing Format and Scalability
Blade products were produced in different formats with different lead frame strip sizes and numbers of strips per panel arranged into a rectangular panel. Also, different panel sizes were used. A typical HDI board has a size of 24″ × 21″ (~600 mm × 500 mm). An early production concept worked with quarter panels hosting about 10 lead frame strips. The use of small strips was originally triggered by the availability of diffusion solder die bonders with sufficient placement accuracy. Within later production concepts, the lead frame area was increased by a factor of 2–3, and the panel size moved toward the size of a typical HDI PCB production panel.
The applied lead frame strip sizes and panel formats have a huge impact on the panel occupation with active devices. A cost‐optimized production concept has to consider this carefully and monitor the yield as well as the higher engineering effort with larger formats. Larger formats will increase the challenges of the alignment concepts required to maintain attractive design rules, for example, in terms of chip pad sizes. Chip position measurement routines applied before lamination do not take into account panel distortions during lamination and further processing.
Nevertheless, even a lead frame strip size close to the panel size itself will never lead to an occupation close to 100% as long as the outer rim of the lamination panel has to be discarded as an inherent limitation of PCB technology.
The Blade package technology has a very high potential concerning the scalability of the packages themselves. Packages can be as small as the Blade3x3 (3 mm × 3.4 mm) or even smaller. In terms of the production technology, a complete lead frame strip can also make up an individual package. Test vehicles with several centimeters of edge length were easily built on a Blade package production line [4].
12.8 Package Performance
12.8.1 Electrical Performance
The Infineon Blade technology was developed as a power technology. Therefore, electrical performance is an obligatory basic feature. The micro‐via connection to the chip has a resistance of less than 1 mΩ per via, at the same time allowing high parallelization and a good coverage of the pad area, reducing sheet resistances. The typical RDL thickness of 35 μm and wide lines allow low resistances as well. Good designs typically avoid horizontal routing of the high current lines and take advantage of the vertical capabilities. The die are best placed directly facing their according potential on the board. Only minimal horizontal routing distances over the RDL and usage of the high cross section of the lead frame allow superior electrical performance.
As an example, the simulated voltage over the Blade3x3 shows no significant voltage drop within the package metal. Almost the whole resistance lies in the silicon, which is a 1 mOhm chip after all (cf. Figure 12.8).
Figure 12.8 Cross section through simulated voltage (normalized values) within an open gate of the MOSFET (die).
So far, half bridges with integrated drivers with current ratings up to 80 A on 20 mm2 were built.
12.8.2 Thermal Performance
The thermal performance is absolutely crucial for power packages. The preferred setup, with the most heat‐producing chip facing toward the PCB, allows an extremely low Rth (thermal resistance) from junction to board. Additionally, the included lead frame and the wide RDLs deliver a relatively high thermal mass, short wired over Cu vias or diffusion solder, which is advantageous for the Zth (thermal impedance, time‐dependent thermal resistance). The thin package, either with exposed lead frame or with a thin insulation layer, allows double‐sided cooling. The Blade products have a significantly lower thermal resistance junction to package topside than corresponding molded products (see Table 12.1). Hence, forced air convection can significantly improve topside cooling for Blade packages (see Figure 12.9).
Table 12.1 Data sheet values of thermal resistances to package top and to package bottom for Blade products and similar molded products [7–11]. (Lower values allow more efficient cooling.)
| Product | Package type | Remark | R th junction case top (K W−1) | R th junction case bottom (soldering point) (K W−1) |
| Blade3x3 | Blade, exposed lead frame, die face‐down | Large die products | 1.0 | 1.6 |
| Blade3x3 | Small die products | 1.0 | 3.2 | |
| DrBlade1 | Blade, lead frame embedded, die face‐up | Large MOSFET (low side) | 2 | 1 |
| Small MOSFET (high side) | 7 | 2 | ||
| DrBlade2 | Blade, lead frame embedded, die face‐down | Typical | 3.7 | 3.5 |
| DrMOS | Molded package, die face‐up with soldered clip(s) | Typical | 20 | 5 |
| Discrete MOSFET in TDSON8 | Typical | 20 | 1.3 |
Figure 12.9 Thermal resistance to ambient; Ploss = 4.5 W, TA = 70 °C, eight‐layer server board with 2 oz. copper per layer (lfm: linear feet per minute).
Source: data taken from data sheet DrBlade2 [9].
Simulations have shown that forced air convection can significantly improve the cooling of the device over the topside. An additional heat sink on the top is much more efficient than for thick standard molded packages.
12.8.3 Thermomechanical/CTE, Moisture, and Warpage Issues
The Blade package uses laminate materials and copper. Therefore, the CTE closely matches that of the PCB to which the package is attached, thereby reducing some standard problems such as thermo‐mechanical package‐to‐PCB mismatch. Although it is very thin and somewhat bendable, dedicated bending stress tests on test boards showed resistance to mechanical stress to almost the same level as heavier molded packages. This is probably because the thin chips bend under stress instead of breaking.
However, FR‐4 materials are known to absorb much more moisture than mold compound. This requires special care for corrosion‐resistant chips and materials. If some material combinations like chlorine‐containing laminates and non‐noble metals are avoided, the moisture resistance is the same or less as for the PCB and therefore fully sufficient.
An ultrathin package can show some warpage due to CTE mismatch between the materials used, but the included relatively thick Cu lead frame stiffens the system significantly. At least for the small packages, warpage is therefore within the typical package specifications of less than 80 μm [8]. Warpage is more an issue in the panel during manufacturing in the line than in the final singulated component, which requires a high level of knowledge in materials and process engineering to overcome.
12.9 Robustness and Reliability Data
12.9.1 First Level/Component Level (CLR)
Blade products are basically qualified according to Infineon’s industry standard, similar to AEC Q100. Only autoclave stress tests are not used, since the Blade package falls under the category of laminate‐/PCB‐based packages and a uHAST (130 °C, 85% RH) is applied instead [12, 13].
The Blade3x3 was additionally exposed to combined and extended stress tests to check for potential weaknesses concerning component reliability. These tests covered active and passive tests.
The IPC (IPC – Association Connecting Electronics Industries) has published the industry standard IPC‐TM‐650 2.6.25. It defines stress test conditions for the investigation of conductive anodic filament (CAF) at PCB materials. Among others, a 50‐hour storage at a temperature of 85 °C and at 85% relative humidity with an applied voltage of 100 V is described. This stress test was applied to Blade3x3 products for 500 h instead of the above defined 50 h. Nevertheless, within this test exceeding the stress test duration as defined in the standard by a factor of 10, no CAF could be observed. Also at 175 °C, 20 V for more than 1000 h, extended H3TRB (high temperature reverse bias with TA = 85 °C/85% relative humidity with device reverse biased at 80% of rated breakdown voltage), corresponding gate stress, and HAST (biased highly accelerated stress test) tests, neither CAF nor other package failures could not be provoked. This high reliability is related to the high quality lamination material in the BOM of the Blade packages.
12.9.2 Second‐Level/Board‐Level Reliability (BLR)
Blade products deliver excellent board‐level reliability (BLR) test results. For temperature cycling on board (TCoB), tests devices were soldered to a four‐layer PCB 1.6 mm thick with Sn final finish and green SnAgCu solder paste. TCoB was performed between −40 and 125 °C with a duration of one hour per cycle according to IPC‐9701 [14]. All Blade products withstood far more than 1000 TCoB without electrical fails in the online monitoring.
In a study with DrBlade2, none of the devices showed fails in the electrical online monitoring up to the test end at 6000 cycles. Cross sections were made after 1000 cycles showing no degradation of the solder joint (see Figure 12.10).
Figure 12.10 Mechanical cross section through a DrBlade2 package at outer row along the long package edge after 1000 TCoB on a four‐layer 1.6 mm thick PCB.
As Table 12.2 shows, all Blade products withstood far more than 1000 TCoB cycles without fails in online readouts.
Table 12.2 Blade solder joint robustness in TCoB test.
| Product | Package | Cu layers of board | First fails in online readout |
| DrBlade1 | LG‐UIQFN‐32‐2 | 4 | 2000 cycles |
| DrBlade2 | LG‐WIQFN‐38‐1 | 4 | 3000 to >6000 cycles depending on board assembly |
| Blade3x3 | LG‐USON‐5‐1 | 4, 8, 10 | No fails at 5000 cycles |
Compression tests were performed on the DrBlade2 package LG‐WIQFN‐38 (4.5 mm × 6.6 mm) containing two MOSFET chips and a driver chip and the Blade3x3 package LG‐USON‐6‐1 (3 mm × 3.4 mm), which is a single MOSFET package. For the tests, the devices were soldered to a high Tg FR‐4 PCB with 1.6 mm thickness and four copper layers with chemical Sn final finish with a SAC305 solder (96.5% tin, 3% silver, and 0.5% copper). Online readout equipment was connected to the test PCB. Then a force ramp was applied perpendicular to the PCB and package plane until an electrical fail was detected or a maximum force was reached. For both packages no fails could be induced with the maximum applied forces of 2000 N (Blade33) and 2500 N (DrBlade2). This behavior is similar to molded power packages. Applied to the plastic encapsulated package with a copper lead frame, a single MOSFET die, and a soldered clip as source interconnect PG‐TDSON‐8 (Plastic Green Thin Dual Small Outline Non‐leaded Package; size: 5 mm × 6 mm), no damage could be provoked up the maximum applied force of 2500 N in the same test setup. Also bending tests gave similar results as for molded packages.
Electromigration stress tests were performed on a dedicated Blade test vehicle in a modified Blade3x3 package to test single via connections and a newly developed nonstandard test setup, where a single micro‐via of ~60 μm diameter was subjected to a current flow of 30 A at 165 °C at each device under test (DuT). The DuTs were soldered to a board with 105 μm thick outer copper traces with Ni/Au finish with a SnAgCu solder. No defects could be provoked at the vias toward the chip, copper traces in the package, or other package internal Cu‐to‐Cu interconnects. With end‐of‐life tests by far exceeding the components mission profile after more than 3000 h test duration at 165 °C, the second‐level interconnect was finally destroyed, and the board‐level solder dissolved part of the copper of the package pads and copper vias (see Figure 12.11).
Figure 12.11 Cross section through electromigration test vehicle after more than 3000 hours at 165 °C with 30 A current flow showing diffusion of solder into the Cu trace of the test board as well as into the Cu pad and vias of the package.
No drop tests were performed for the Blade package technology, as the targeted application range so far does not include mobile applications and these tests are obviously irrelevant for servers.
Overall, the Blade package technology has the potential to be qualified for conditions well exceeding standard industrial qualification conditions.
12.10 Electrical Test Considerations
All Blade and DrBlade products are 100% electrically tested. This can only be done after package dicing, because the lead frame shorts the devices. There are many different options for dicing as well as for testing. Dicing on dicing frames on foils allows frame testing, which is efficient for devices with a high logic content. Cheaper foil‐less dicing requires single device handling and testing later, which makes high current tests simpler, as they do not require test needle cards.
Fortunately for testing, the Blade package is a fully robust package, which can be handled and contacted without special risk of damage. Therefore, the test can be done on the device pads. E‐less Ni/Au surfaces are very easy to contact. On the other hand, the solder depots of the Blade3x3 and DrBlade2 with their uneven surface challenge the test and needle design.
12.11 Applications and Markets
Following the general trend of miniaturization and the reduction of system cost, the DC‐to‐DC power supplies for central processing units (CPUs) started in the early 2010 to move from discrete MOSFET devices toward integrated half bridges including the driver ICs. Especially in the market of large server farms, current consumption is the main cost driver. Therefore, high efficiency for DC‐to‐DC conversion, especially in the high current parts like CPU and graphics processing unit (GPU), is a strong market requirement. Due to the high switching frequencies above 100 kHz, low parasitics are significantly improving the efficiency.
Additional advantage of the Blade technology can be taken for applications, which require small outlines, either as board space or in package height. The product in Blade3x3 package has a size of only 10 mm2 with an Ron of 1.2 mΩ, which is unbeaten at this technology generation.
Acknowledgments
This work was partly supported by the research and development project ProPower (Grant Number 13N11879), funded by the German Federal Ministry of Education and Research (BMBF), and in part by the project eRamp (Grant Agreement Number 621270), co‐funded by grants from Austria, Germany, Slovakia, and the ENIAC Joint Undertaking.
We want to thank colleagues at Infineon Technologies AG for their support by fruitful discussions, review of the manuscript, and provision of pictures: T. Both, R. Fischer, A. Gruber, G. Haubner, J. Höglauer, A. Keßler, G. Lohmann, X. Schlögel, F. Treutinger, S. Weiß, and R. Wombacher.
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