5.1 Introduction

nepes Corporation’s fan‐out wafer‐level packaging (FO‐WLP) technology was first introduced in the year 2010 on a 300 mm platform, which is based on the redistributed chip package (RCP) licensed from NXP (formerly Freescale Semiconductor) using a chip‐first, face‐down concept, which is similar to most conventional FO‐WLP platforms in the industry [1–5].

Further development has been made, enhancing the process robustness and high volume mass (HVM) production capability for automotive products, mobile applications, and system solutions with multiple devices embedded and integrated. nepes’ FO‐WLP system‐in‐package (SiP) solution offers 40–90% volumetric shrink from existing modules with flexible product design to end user [6]. Numerous active or passive components could be embedded and connected in 2D or 3D via connections to the backside of an FO‐WLP package for package‐on‐package (PoP) structures typically designed for communication modules and system control applications.

5.2 Structure and Process Flow

As shown in Figures 5.1 and 5.2, nepes’ FO‐WLP is based on chip‐first technology. Embedded ground planes (EGPs) (Cu material) are placed onto adhesive tapes laminated on substrates in advance. This EGP, however, is optional depending on the necessity and the package design. Incoming wafers, regardless of size, 6, 8, 12, or even 18 in. (in the future), are subjected to backgrinding and dicing to segregate individual die. The die are subsequently picked and placed onto the substrate. Optional passives, integrated passive devices (IPD), and discrete components could be placed as well. Epoxy compounds are then used to encapsulate the EGP and die in the form of 300 mm wafers by either printing or compression molding. This process is known as panelization. The molded panel is attached to a carrier, which is reusable for subsequent process. Redistribution layers (RDLs) comprising polymeric dielectrics and metallization are then built onto the wafers using tools similar to back‐end silicon wafer processing. The number of layers of metallization is dictated by device complexity and governing FO‐WLP design rules. Upon RDL completion, ball grid array (BGA) balls are placed, or bumps are formed to be used for the next level of interconnection. Finally, the wafers are sawn into individual packages, laser‐marked for product traceability, and shipped to the customer [7].

The value proposition of nepes’ FO‐WLP includes PoP larger than 14 mm × 17 mm enabled in HVM, four metal layer capability with ~100 μm die to die spacing realizing a volumetric shrink of 40–90% for SiP, heterogeneous integration of several active die and more than a hundred passives with robust design and process control, a thin package profile of ~250 μm including solder ball for PoP, low contact resistance between silicon die and RDL, enhanced thermal and electrical performance with EGP, and a via frame structure available for the top package in 3D integration.

In addition, one key distinctive feature in nepes’ FO‐WLP is embedded metal frame, known as EGP. This frame was designed initially to localize die drift during the encapsulant cure step, which controls the die drift within the pocket of the EGP locally. As the EGP is copper material, it allows for better heat dissipation when connected to a chip or exposed to the environment through the package backside after backgrinding. Furthermore, EGP could also enhance package electrical performance through various designs and shapes. As shown in Figure 5.3, EGP can be partitioned to perform ground, VCC (voltage connected between ground and the collector), and electromagnetic interference (EMI) shielding that could potentially reduce the number of RDLs and provide IC designers more real estate for their chip design when necessary. Of course, EGP as a metal frame also reinforces the mechanical robustness of the package, assisting the handling of the thin panel together with the process carrier attached on the backside of the panel while processing.

5.3 Thin Fan‐Out Packaging

Mobile and wearable applications continue to drive reduction of Z height of the assembly due to more dense and complex integration within limited space. Another added advantage and perhaps a more critical one of thin profile packaging is the enhanced thermal performance. nepes Corporation’s continual development of thinner packages is one key focus of the packaging roadmap. Figure 5.4 shows a two‐chip with two‐RDL FO‐WLP device produced in nepes. Package dimension is 10 mm × 10 mm × 0.28 mm with more than 500 balls with PoP structure incorporated using a via frame.

5.4 Double‐Sided Fan‐Out Packaging

For further flexibility to adapt various formats of top package, backside (top) RDL, which is called double‐sided RDL, has been introduced (Figure 5.5). The bottom package has a 0.4 mm thin profile including solder ball, where 10 μm/10 μm line and space RDL has been applied. This technology will allow the main chip in the bottom package to stay faceup so that the top device and bottom package could communicate more efficiently electrically or optically. Table 5.1 shows a package reliability test of the fan‐out package with double‐sided RDL and an embedded vertical structure. The test vehicle (bottom) was 6 mm × 6 mm × 0.35 mm and passed Joint Electron Device Engineering Council (JEDEC) standard package reliability tests such as MSL2.

5.5 Via Frame (VF) Fan‐Out Package

Via frame fan‐out package (VF‐FOP) is shown in Figure 5.6 as a solution developed for 2D and 3D SiP and module packages using a printed circuit board (PCB)‐based via frames structure. This technology enables chip face‐up packages for sensor application and package stacking for 3D integration as well.

In principle, the via frame is an interconnection media designed with through holes filled with conductive material where one side has pads to connect to chips while the other side has metal bumps, which will be connected to other packages through PoP. Via frames can be designed in various forms matching the ball layout and size and number of balls of the upper package.

As shown in Figure 5.7, the process to provide through vias within the FO‐WLP base includes using a laminate‐based via unit with top and bottom electrodes as a critical element in SiP and 3D interconnections. Materials and processes for VF‐FOP were adopted from the PCB industry but with added proprietary features for a fan‐out PoP structure. As shown in the panelization process (the left of Figure 5.7), conductive balls or bumps were adopted on the other side of the via frame, which needs precise temperature control throughout the entire fan‐out package process. These via frame units are embedded during the chip attachment process. FO‐WLP panels having an epoxy‐based substrate with conductive through vias (via frame) will need to be coplanar with both top and bottom surfaces of the package as well as solderable surfaces (on package top). As panels contain semiconductor devices that might have different thicknesses, panels would require delicate control during backgrinding to expose the electrode on one side of the via frame [7]. After panelization, embedding chip and via frame, the post process is almost identical to a typical FO‐WLP or wafer‐level package (WLP) process like dielectric and metal redistribution.

3D stacking process for some package configuration using VF‐FOP was also developed as shown in Figure 5.8. Having metal balls on one side of the VF‐FOP, a more advanced and complex SiP could be manufactured with bottom package for PoP (Figure 5.8c). Such SiP has multiple active dies and up to a hundred passive components with a via frame surrounding all devices that are interconnected to one another. The via frame also acts as a 3D connection to the package top (with backside). Via frame pads are subsequently exposed through epoxy mold compound using a panel backgrind process step. Figure 5.8 shows several types of VF‐FOP for different product application. As shown in Figure 5.8a, VF‐FOP is able to face chip‐up (opposite to solder ball side) with certain selected chip surface area to be exposed or protected by very thin dielectric layer.

5.6 System‐in‐Package

SiP combines functional units into one single package to enable the shortest electrical distance between parts for more superior performance. This significantly reduces the amount of metal traces going into and out from the package, facilitating a more simplistic PCB design for the final product that could potentially translate into substantial savings in manufacturing costs. Fan‐out wafer‐level SiP (FOWL‐SiP) is one of the great technologies enabling these advantages due to the nature and capability of multi‐die packaging at wafer‐level processes where bumps, wires, and substrates become unnecessary. In such a platform, system designers only need to tune and optimize the layout of SiP through device and component locations and RDL designs. This reduces design cycle time significantly in the development stage so that time to market‐in will be much shorter than others. However, in order to adequately support this, FOWL‐SiP needs to have the capability to build multilayer RDL to minimize or completely eliminate the use of additional substrates. It is also essential to understand the behaviors of various components during fan‐out processing through electrical and reliability data.

PoP takes this integration a step further, placing one package on top of another, allowing greater integration complexities and interconnect densities. PoP also enables procurement flexibility, lower cost of ownership, better total system and solution costs, and faster time to market. Scalability is another PoP key advantage because PoP body sizes comply with JEDEC standards, so customers can maintain control of memory procurement, enabling multiple suppliers, supplier qualifications, and certifications with minimal inventory vulnerability. Customers can choose from a wide range and combinations of memory such as flash, PSRAM, SDRAM, or DDR. With the understanding of this requirement, it is possible to expand the applications of FOWL‐SiP, PoP solutions such that they can truly serve as subsystems.

The FOWL‐SiP process flow is almost identical to single‐die package except for multiple embedded devices and repeated RDL processes. However, in order to truly realize SiP in FO‐WLP platforms, it is crucial to understand different components’ (passive, active) drift behaviors and also the criticality of robust RDL designs to pass stringent environmental reliability tests [1, 7]. The angle of the RDL crossing from component to component, device to EMC interface at die edge to control surface topography, surface condition controls of devices to prevent the resin bleed during the molding process, adhesion control between multi‐RDL to multi‐dielectric through PVD, and photo process parameter controls are just few of the critical factors for high volume manufacturing. On top of that, package backside quality also needs to be well controlled for subsequent assembly processing of PoP [8].

Typical processes involve chip bonding, via frame bonding, and passive components bonding (not necessarily in the same order) onto temporary glass substrates followed by molding (either print mold or compression mold). This is followed by iterations of dielectric and RDL processes before finishing with ball drop and panel backside grind to expose terminals for PoP assembly. Figure 5.9 includes examples of images from panel through final assembly. One could notice very dense and complicated RDL structures (dielectric removed on purpose) in the center picture of Figure 5.9. The package (Table 5.2) passed commercial and industrial grade package reliability with less than 50 μm package‐level warpage over the entire reflow profile range. It has three‐die comprising processor, memory, and power chips with 109 passive components [9, 10]. As illustrated in Figure 5.10, all of the active devices and components are integrated and embedded in one single package, representing a true modular level package. Robust process controls and capabilities mentioned earlier are the key prerequisites in order to enable such highly integrated SiP eliminating the use of substrate modules.

Multi‐RDL capability is also utilized to build inductor coils on the package surface as shown in Figure 5.11. Three inductors (2 of 180 nH, 1 of 48 nH) were built on 9 mm × 9 mm FO‐WLP utilizing two layers of Cu spiral trace, and the inductance is achieved well with ±5% tolerance range for the target value. The quality factor (Q factor) is higher than 25 at 200 MHz, implying the inductor is well designed.

5.7 Panel‐Level Package

FO‐WLP built in large‐scale panels, called panel‐level package (PLP), is designed for direct cost reduction from 300 mm scaled FO‐WLP. PLP maximizes the benefits of fan‐out packaging, which resolves the input and output (I/O) limitation of WLP and offers SiP capability with shorter system development cycle time, flexibility of system design due to RDL routing with no substrate, and simple logistic flow in the entire supply chain at large scale. Key processes and technologies of PLP are leveraged from FO‐WLP. The key challenges in fan‐out packaging need to be known first before scaling up. On the other hand, the panel format of PLP requires a different approach of handling, materials, and equipment. Considering all this and the capital expense, starting PLP development is very challenging. The prime motivation for starting PLP development at nepes Corporation is the broad technology experience in WLP, FO‐WLP, and more importantly also in large panel manufacturing of liquid crystal display (LCD) product. With years of experience in both FO‐WLP and LCD processing including touch screen panel for mobile product using fourth‐generation LCD equipment, 600 mm × 600 mm PLP technology has been developed and demonstrated in a mass production platform (Figure 5.12).

5.8 Performance and Reliability

5.8.1 Thermal Performance

The effect of EGP demonstrated by the simulated thermal performance of a package structure is shown in Figure 5.13 using the FloTHERM analysis tool. Conditions include JEDEC still air enclosure of X : 304.8 mm, Y : 304.8 mm, Z : 304.8 mm with test board of 114.3 mm × 76.2 mm × 1.6 mm, which has four layers with Cu coverage of Trace 1 (20%)/Trace 2 (90%)/Trace 3 (90%)/Trace 4 (20%). The test is based on JEDEC standards JESD51‐2/JESD51‐8/JESD51‐14.

Simulation results showed 25% better thermal performance in package with EGP compared with no EGP structure as summarized in Figure 5.14. The hot spot zone is reduced as heat is more efficiently transferred externally since the EGP carries heat more from the chip through RDL than the no EGP structure. This implies nepes’ fan‐out package (RCP) has better heat dissipation ability than a typical FO‐WLP.

5.8.2 Electrical Performance of Automotive Radar Package

The requirements for packaged automotive radar solutions include excellent RF isolation, controlled impedance, low insertion loss, low attenuation, good thermal dissipation up to 2 W in an ambient temperature of 125 °C, and fulfilling stringent AEQ‐100 G1 reliability criteria. Using the advantages of EGP and robustness of nepes’ FO‐WLP, this platform was selected for 77 GHz Radar Package used for automotive solution. The package has an EGP size of 6 mm × 6 mm and is shown in Figure 5.15.

The package has been tested over a range of frequencies and temperatures for voltage‐controlled oscillators (VCO), transceiver, and receiver as shown in Figures 5.16 and 5.17. It shows extremely low loss of <1 dB, and insertion loss degradation is small across a wide temperature range.

5.9 Application

New and emerging applications in the consumer and mobile space, the growing impact of the automotive, Internet of things (IoT) and wearable electronics (WE), and the complexities in sustaining Moore’s Law have been driving many new trends and innovations in advanced packaging technology. Demand for functional integration in the small and thin package will continue to grow with the requirements for lower cost and power consumption. To develop a disruptive packaging technology capable of achieving these goals is challenging, and FO‐WLP is playing important roles in many application areas as shown below. Figure 5.18 shows various application products of FO‐WLP from mobile consumer to automotive.

5.9.2 Sensor Products

Figure 5.19 shows a double‐sided RDL with VF‐FOP for a fingerprint sensor (FPS) package with a thin profile of less than 0.2 mm thickness. FO‐WLP greatly enhances the detectability or sensing ability of sensor devices since the distance from the chip surface to the external surface is shorter than with a wire‐bonding package, which determines the sensing ability. It has been qualified for package‐level reliability conditions of MSL2, 700 temperature cycles (−55 to 125 °C), and 96 hours of pressure cooker test (121 °C/100% RH).

Other sensors like pressure sensors and biosensors are also being targeted and implanted as a niche market.

5.9.3 Optical Module

The era of big data is driving optical interconnections to enhance the transmission speed. Concerns include the signal loss at wire bonding, complicated assembly of fiber alignment, and form factor.

These concerns can be relaxed with key benefits of FO‐WLP. Below shows a simple concept of an optical module for high‐definition multimedia interface (HDMI) application that may need a smaller version of module for mini or micro HDMI (see Figure 5.20). The package size is small with optical IC and driver IC as well. This technology and concept provide not only a small form factor but also some special features on the package top, which allows easy fiber alignment as well. It leads compact‐sized package and also easy assembly providing the module manufacturer with better productivity at lower cost. The package size is 3.50 mm × 3.00 mm and 0.315 mm thick. The chip sizes are 0.27 mm × 1.0 mm, 1.3 mm × 0.9 mm. The structure is face‐up with two RDL layers and via frame embedded for vertical interconnection.

5.9.4 IoT and Industrial Applications

An Arduino (Orange Board™) was successfully optimized and redesigned in VF‐FOP. Die and components have been assembled on the modules embedded in FO‐WLP. This is based on one VF‐FOP size of 7.35 mm × 7.35 mm excluding the connector. Figure 5.21 shows the package structure and size comparison of this new redesigned package against the original Arduino. This small dot‐sized Arduino (called DotDuino) is 100% compatible with original Arduino module but with a 90% size reduction. After prototyping this new product, the inventors can commercialize their idea very quickly and efficiently for this new smaller module to the market on various applications as showcased in Figure 5.22. Nepes’ FO‐WLP roadmap is show in Figure 5.23.

5.10 Roadmap and Remarks

Development focus is driven by markets where form factors and cost are important while new features such as thermal, speed, and integration capability are equally important. As introduced, large‐scale PLP has been implemented in high volume manufacturing mode and is in the initial production stage. Special features and materials are applied and implemented to enhance the thermal and EMI shield performance as well. Further reduction in package thickness to less than 100 μm will be implemented.

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