22.1 Improving the Conventional WLCSP Structure

The WLCSP was introduced in 1998 as a semiconductor package wherein all packaging operations were done in wafer form [1]. The resultant package has dielectric layers, thin film metals, and solder balls directly on the surface of the die with no additional packaging. The basic structure of the WLCSP has an active surface with polymer coatings and solder balls with bare silicon exposed on the remaining sides and back of the die. The WLCSP is the smallest possible package size since the final package is no larger than the required circuit area. Based on the small form factor and low cost, the number of WLCSP used in semiconductor packaging has experienced significant growth since its introduction. The growth has been driven aggressively by mobile consumer products because of the small form factor and high performance required in the package design. Although WLCSP is now a widely accepted package option, the initial acceptance of WLCSP was limited by concerns with the surface‐mount technology (SMT) assembly process and the fragile nature of the exposed silicon inherent in the package design. Assembly skills and methods have improved since the introduction of the package; however damage to the exposed silicon remains a concern. This is particularly true for advanced node products with fragile extreme low dielectric constant (low‐ELK) dielectric layers used in the silicon processing. One method commonly used to improve die strength and reduce silicon chipping during assembly is lamination of an epoxy film on the back of the die. The film is laminated and cured on the back of the wafer prior to singulation to strengthen the die, in spite of the fact it adds cost to the package. By the nature of the backside lamination process, the uncoated sides of the die continue to be exposed after dicing the wafer, and the silicon continues to be at risk for chipping, cracking, and other handling damage during the assembly process.

Despite the indisputable benefits of WLCSP, there are a number of concerns that have continued to plague the adopters of this technology since its inception:

1. WLCSP is essentially a bare die with exposed Si surfaces. The package suffers mechanical damage in the form of chipping and cracking in the course of processing, shipping, and during SMT operations. This necessitates additional processing (e.g. backside coating or lamination) for partial die protection and inspection steps to ensure outgoing product quality, leaving the product still exposed to potential field failures due to the risk of marginally damaged parts being shipped that may not be “caught” by inspection. Also, WLCSP is typically tested at wafer level prior to saw, which is a quality risk.
2. The manufacturing infrastructure for WLCSP is entirely dependent on the incoming wafer diameter. As designs migrate to larger wafer diameters (as in the 200–300 mm transition or the future transition from 300 to 450 mm), new investments become necessary to support the capacity requirements, while investments in the existing infrastructure may be rendered obsolete.
3. From a design perspective, WLCSP is effectively a “fan‐in only” package. The input and output signals (I/O) must be accommodated on the area of the die at the desired terminal pitch; hence, there is a threshold of I/O density above which the WLCSP package becomes unusable and a change to a completely different packaging solution becomes necessary. Such situations often arise with node transitions that result in die shrinks. For example, a change from WLCSP to wire‐bond ball grid array (FBGA), flip‐chip BGA (fcFBGA), or quad‐flat no‐lead (QFN) packaging is not uncommon, which entails a radical change in package footprint, form factor, performance, and cost structure.

Enter the eWLCSP that is a simple variation of the broader fan‐out wafer‐level packaging (FO‐WLP) platform (trade named eWLB for embedded wafer‐level ball grid array). eWLCSP retains the compelling benefits of WLCSP packaging while addressing many of the key concerns mentioned above. The structure of the package, the fabrication process, the unique advantages, and the preliminary product/reliability assessment are discussed here.

eWLCSP has been developed to provide five‐sided protection for the exposed silicon in a WLCSP. The process starts with an existing high volume manufacturing flow developed for eWLB fan‐out products. The implementation of this process flow into 300 mm diameter reconstituted wafers has been described in detail in previous presentations [2]. In this manufacturing method the wafer is diced at the start of the process and then reconstituted into a standardized wafer (or panel) shape for the subsequent process steps. The basic process flow for creating the reconstituted wafer is shown in Figure 22.1:

1. The reconstitution process starts by laminating an adhesive foil onto a carrier.
2. The singulated die is accurately placed face‐down onto the carrier with a pick and place tool.
3. A compression molding process is used to encapsulate the die with mold compound while the active face of the die is protected.
4. After curing the mold compound, the carrier and foil are removed with a debonding process, resulting in a reconstituted wafer where the mold compound surrounds all exposed silicon die surfaces.

The eWLB process is unique since the reconstituted wafer does not require a carrier during the subsequent wafer‐level packaging processes.

After the reconstitution process, the reconstituted wafer is processed with conventional wafer‐level packaging techniques for the application and patterning of dielectric layers, thin film metals for redistribution and under‐bump metal, and solder bumps. In the final dicing operation, a thin layer of mold compound, typically less than 70 μm, is left on the side of the die as a protective layer. The back of the die is also protected with mold compound, although with a greater thickness than the sidewall layer. A schematic drawing of a typical structure is shown in Figure 22.2 for greater clarity. Alternatively, the backside mold compound can be removed, and the body is made thinner with an optional backgrind operation without damaging the protective sidewall layer. The remaining sidewall coating will continue to protect the fragile silicon sides of the die during the assembly operation.

22.2 The Encapsulated WLCSP Process

The FO‐WLP process has been discussed in many venues, and it is recognized as an industry standard process. In the FO‐WLP process the area of the package is increased to allow for placement of redistribution layers (RDL) and solder balls outside of the silicon die area [3]. This packaging method allows the die to shrink to a minimum size independent of the required area for an array of solder balls at industry standard BGA ball pitches [4]. It also allows for novel multi‐die structures, 2.5D structures, and 3D structures. The FO‐WLP process has been qualified to a 28 nm process node with the same dielectrics and Cu plating as are used in the eWLCSP process described here [5]. The eWLCSP process data presented in this paper was generated with a 300 mm round reconstituted panel [2]. In the case of conventional FO‐WLP, the die is typically widely spaced to allow for the expanded RDL and bump area and the conventional saw street. In the case of eWLCSP, the die is closely spaced allowing for only the sidewall thickness in addition to a street area of 80 μm. The die size used in this evaluation was 4.5 mm × 4.5 mm similar to the construction shown in Figure 22.2. The final structure had two layers of polymer dielectric and one layer of plated Cu RDL with the solder ball mounted directly on the RDL without the use of a separate under‐bump metallurgy (UBM) layer. The process flow used is shown in Figure 22.3 and the details of the structure are shown in Table 22.1 [6, 7].

Intuitively the process flow shown in Figure 22.3 would have higher cost since there are additional steps required for reconstitution at the start of the flow. There are two key factors that offset the cost of the additional steps required for the reconstitution to make this a commercially viable process. (i) Panel size scaling reduces the unit cost if the source silicon wafer is smaller than the reconstituted panel size. In the case of the 300 mm reconstituted panel used here, the cost is very competitive for silicon wafers with a diameter of 200 mm and below. The cost of processing a 300 mm reconstituted panel for WLCSP is approximately 1.7× the cost of processing a conventional 200 mm silicon wafer in WLCSP; however the units processed per panel increase by a factor of 2.3×, effectively offsetting the cost of reconstitution. (ii) Since known good die can be selected at the start of the process, advanced devices that have a lower electrical yield can be tested in wafer form prior to the process. If the incoming wafer has a probe yield of 85%, then 15% more units per reconstituted panel can be processed to offset the cost of the reconstitution process. Since the reconstituted panel size is no longer linked to the incoming silicon wafer size, the panel size can be increased over time and change from a round to a much larger rectangular format. This scaling to a larger panel size will provide a compelling cost reduction when compared with conventional WLCSP packaging methods where the round silicon format is maintained throughout the wafer‐level packaging process.

One difference in processing panels in the reconstitution flow is found in the attributes of the polymers that are used. In conventional WLCSP either polyimide (PI) or polybenzobisoxazole (PBO) is used as the dielectrics for planarization, stress buffering, and RDL insulation. In the case of the reconstituted panel, the mold compound has a lower temperature threshold than silicon, and sustained temperatures over 200 °C can cause degradation of the material. PI typically has a cure temperature of 380 °C, and PBO has a typical cure temperature of 300 °C and therefore cannot be used in the process. A new low temperature polymer has been developed for this application that has a cure temperature compatible with the 200 °C threshold temperature of the mold compound.

A scanning electron microscope (SEM) image of a cross section of an eWLCSP™ part created in the process is shown in Figure 22.4. In this case, a thicker sidewall protection layer was used to demonstrate the process on an existing production device running in the conventional 200 mm WLCSP production line. The device demonstrated equivalent electrical yield, component‐level reliability (CLR), and board‐level reliability (BLR) performance.

A second SEM cross section is shown in Figure 22.5 showing the finished package with a thin protective sidewall coating and the use of the optional backgrind to thin the body thickness.

A WLCSP product that is currently in production using a conventional WLCSP process can be converted to a eWLCSP product without any design change required, regardless of the current silicon wafer diameter. If a reduced thickness is required for the specific application, an optional backgrind step can be added to the process flow to reduce the body thickness while retaining the protective sidewall coating. Since the die is singulated at the start of the process, the manufacturing equipment and bill of materials are the same for any incoming wafer size. The initial backgrind and dicing tools are the only wafer size dedicated equipment required for the process. Very little process development and very little additional capital will be required to package 450 mm silicon wafers as eWLCSP.

22.3 Advantages of the Encapsulated WLCSP, eWLCSP

Intuitively, eWLCSP would seem to have a higher cost over conventional WLCSP since there are additional steps required for reconstitution at the start of the FlexLine manufacturing flow. There are key factors, however, that offset the cost of the additional steps required for the reconstitution to make this a commercially viable process:

1. Cost‐effectiveness: As described above, eWLCSP is fabricated using reconstitution. Good die from the parent wafer are picked and transferred to a (larger) reconstituted carrier. Since the majority of WLCSP products use 200 mm wafers, reconstitution enables the scaling of the manufacturing process from the 200 mm wafer to the size of the carrier in eWLB technology. This carrier size ranges from 200 to 300 mm to a larger format like high density (HD) with ~20% greater area or ultrahigh density (UHD) with >300% greater area. The scaling of the manufacturing process with reconstitution far outweighs the cost of reconstitution itself, thereby enabling large net cost reductions. Additionally, the ability to selectively pick good die from the parent wafer presents an additional net cost benefit as most wafers have a less than 100% wafer sort yield. Last but not least, the ability to pool the volume of traditional fan‐out eWLB packages seamlessly together with eWLCSP packages on the same FlexLine provides important economies of scale. With the three factors stated above, significant net cost reductions over traditional WLCSP front‐end processing are achievable, depending on the original wafer diameter, the carrier format used for reconstitution (300 mm, HD or UHD), and the yield of incoming wafers.
2. High quality solutions: The polymer sidewall structure of eWLCSP all but eliminates mechanical damage such as chipping and cracking that is commonly encountered in traditional WLCSP processing. This serves to eliminate many expensive steps such as backside coating or lamination and complex inspection steps that are currently necessary for standard WLCSP to manage mechanical damage and ensure product quality. More fundamentally, the eWLCSP allows customers to build in quality by design versus using inspection to weed out defects. This has implications for reducing the risk of field failure due to the shipment of marginally defective parts that may escape inspection. As is shown in a later section, the eWLCSP structure has also helped to increase the overall die strength by ~100% in addition to the mitigation of cracking and chipping defects, making for an overall more robust package.
3. Investment and infrastructure – wafer‐agnostic processing: In traditional WLCSP processing, the investment and infrastructure for manufacturing are based on the diameter of the incoming wafer. This creates a financial burden to retool the manufacturing lines to provide the needed capacity (to meet market demand) as wafer transitions occur (e.g. from 200 to 300 mm or from 300 to 450 mm in the future) while also having to obsolete the existing manufacturing assets. The FlexLine approach for eWLB and eWLCSP effectively decouples the packaging process from the incoming wafer, altogether obviating the above‐described financial burden resulting from wafer diameter transitions.
4. Design friendly – allows seamless transition from fan‐in to fan‐out within the same basic package platform: As noted previously, the standard fan‐in WLCSP only works below a certain threshold of I/O density, based on the minimum allowable terminal I/O pitch. The threshold is ~4 I/O/mm² for a 0.5 mm terminal I/O pitch and ~6 I/O/mm² for 0.4 mm terminal I/O pitch. Small changes in I/O density commonly occur with changes in Si design, and die shrinks resulting from Si node transitions may lead to a given design exceeding the WLCSP threshold, causing the design to “fall off” the WLCSP application space envelope, necessitating a change in packaging POR to traditional substrate‐ or lead frame‐based packages like FBGA, fcBGA, QFN, etc. These packages are fundamentally different than WLCSP in terms of footprint, form factor, performance, and cost, resulting in a major “reset” in the packaging POR. In contrast, the eWLCSP may be viewed as part of the more universal eWLB platform wherein the aforementioned I/O density transitions can be seamlessly accommodated within the same packaging platform. For designs whose I/O density falls marginally outside the threshold, an additional row of terminal solder balls can be added without fundamentally altering the package structure, form factor, or performance.

22.4 eWLCSP Reliability

The unique attribute of the eWLCSP package is the protective sidewall coating. The protective layer is durable and will prevent silicon chipping on the side of the package. This protective layer has the ability to protect the silicon during socket insertion for test. This has been demonstrated through multiple insertion tests on completed products with no observed damage to the protective coating.

Robust reliability of 4.5 mm × 4.5 mm eWLCSP was reported with CLR and BLR tests. The eWLCSP process has passed standard reliability tests used in wafer‐level packaging including CLR, temperature cycle on board (TCoB), and drop test.

CLR was completed with the test conditions shown in Table 22.2. The evaluation results were confirmed by visual inspection and electrical test. No delamination of the protective coating was detected during the CLR evaluation.

TCoB was completed and passed 500 cycles, the typical requirement for consumer and commercial devices, with the results shown in Table 22.3 and the Weibull plot in Figure 22.6. Results were obtained from electrical measurement of daisy‐chain bump structures. The results are comparable with conventional WLCSP products produced with PI dielectrics.

Drop test was completed and passed the JEDEC requirement of 30 drops with the results shown in Table 22.4 and the Weibull plot in Figure 22.7. Results were obtained from electrical measurement of daisy‐chain bump structures. The results are comparable with conventional WLCSP products produced with PI dielectrics.

22.5 Reliability of Larger eWLCSP over 6 mm × 6 mm Package Size

For reliability tests of larger eWLCSP over 6 mm × 6 mm, two test vehicles were prepared, 6 mm × 6 mm and 8 mm× 8 mm, as shown in Table 22.5. The eWLCSP process passed standard reliability tests used in wafer‐level packaging including CLR and BLR (TCoB and drop test). CLR was completed with the test conditions shown in Table 22.6.

The evaluation results were confirmed by visual inspection and electrical test. No delamination of the protective coating was detected during the CLR evaluation. TCoB was completed and passed 500 cycles with the results shown in Table 22.7. Results obtained from electrical measurement of daisy‐chain bump structures demonstrate that eWLCSP is comparable with conventional WLCSP products produced with PI dielectrics. Drop test was completed and passed the JEDEC requirement of 30 drops with the results shown in Table 22.4.

A four‐point bending test was carried out to investigate package‐level strength. eWLCSP shows an over 25% increase in die strength compared with WLCSP due to the sidewall protection and optimized backgrinding process.

The Si surface roughness was measured with atomic force microscopy (AFM). eWLCSP has a Si roughness value very close to that of WLCSP. A roughness image scan clearly showed no difference in Si surface roughness between WLCSP and eWLCSP.

The protective sidewall coating is a unique attribute of the eWLCSP. This protective layer is durable and will prevent silicon chipping on the side of the package and has the ability to protect the silicon during socket insertion for test. This has been demonstrated through multiple insertion tests on completed products with no observed damage to the protective coating in Table 22.8.

With these test results along with CLR and BLR results, large eWLCSP with additional sidewall protection has demonstrated more robust reliability than standard WLCSP and prevents side chip cracking.

22.6 eWLCSP Wafer‐Level Final Test

An eWLCSP reconstituted wafer is different from a silicon wafer as the backside of the wafer is mold compound, which tends to have a much higher warpage level compared with a silicon wafer of similar thickness. To address this issue, modifications were made to the prober to enable handling of the eWLCSP reconstituted wafer. These modifications were carried out and successfully demonstrated in a high volume manufacturing environment

The test chuck of the prober must be modified for handling of the warped wafers. A progressive and stronger vacuum at the test chuck is necessary to ensure the wafer is properly held flat on the test chunk before testing. The shape of the robot handling arms was modified, and the vacuum to these arms was enhanced to ensure proper holding during the transfer of wafers within each module of the prober. One of the key differences between an eWLCSP reconstituted wafer and a silicon wafer is the wafer identification (ID) marking on the wafer. For an eWLCSP reconstituted wafer, the ID marking is on a copper surface, which makes it look entirely different under the prober’s optical character recognition (OCR) reader. Hence, modification on the OCR reader is required to enable reading of the reconstituted wafer ID. Furthermore, in alignment with the eWLCSP assembly process, where the modified front‐opening unified pod (FOUP) is used in processing the wafers, the prober software must be modified to accommodate the differences. Figure 22.8 shows a pre‐aligner station where the wafer notch is detected and the wafer ID is read of the eWLCSP panel.

Wafer‐level testing of eWLCSP has been proven with noticeable advantages such as a higher test cell utilization and better first pass yield, resulting in an overall cost reduction of testing these packages. Wafer‐level testing offers a short index time, especially for highly parallel testing. This is mainly due to the indexing from one touchdown to the next, where it only involves a small movement within the wafer compared with the pick and place handler that has a high index time. Indeed, this short index time characteristic is most suitable for eWLCSP devices testing, especially for small package sizes, short test times, and high parallelism test requirements. Besides achieving higher throughput, wafer‐level testing improves utilization by lowering manufacturing stoppages, such as jamming associated with the handling of small packages.

Wafer‐level testing of eWLCSP improves the first pass yield by utilizing the visual alignment system, which is standard on a prober. Using camera and vision technology, the socket pin alignment to the package bumps can be highly accurate and repeatable; thus the first pass test yields for wafer‐level testing are significantly higher. Figure 22.9 shows the indexing process of an eWLCSP carrier. Besides providing better and more accurate contacts using vision technology, the prober utilizes its auto socket cleaning feature to improve test yield, whereas this auto cleaning feature is an in‐line process that minimizes test cell downtime and eliminates operator labor needed for manual cleaning. Furthermore, wafer‐level testing also reduces the tooling and hardware costs. In contrast to pick and place handlers that require a new change kit for every different package size, using a prober to handle wafer‐level testing eliminates the need to change kits and thus reduces the overall manufacturing cost.

22.7 Conclusions

A new eWLCSP process has been developed and verified with reliability testing. The process provides mechanical sidewall protection to WLCSP parts with an increase in package size of less than 140 μm in X and Y dimensions. The sidewall protection resolves the problem of silicon damage during the assembly process and provides a path to significant cost savings for customers as the panel size is increased. The eWLCSP process described is wafer size agnostic, so the same manufacturing line can process eWLCSP products regardless of the incoming wafer size. 450 mm wafers can easily be accommodated in the eWLCSP process once the service is required by the customers (Figure 22.10).

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