19.2.1 Degas

Contamination during sputtering can impact film properties and subsequent electrical performance, so it is important to remove contaminants such as moisture prior to PVD module visits. In the degas chamber, incoming wafers are raised in temperature, ideally under high vacuum conditions, to cause absorbed moisture and other contaminants to outgas from the substrate. For normal UBM and RDL processes on Si substrates, degas times from 30 to 300 seconds are typical depending on the amount and type of passivation material involved, with temperatures operating in the 150–250 °C range, again depending on the tolerances of the materials involved or other integration constraints. With FO‐WLP structures the temperature limitations are lower, typically 120–130 °C. Degas times to minimize contact resistance (R_c) are typically on the order of 20–40 minutes depending on device R_c requirements and the organic materials used.

19.2.2 Pre‐clean

Native oxide growth on exposed metal contacts is removed using a sputter etch process to ensure good electrical contact is made when the first PVD metal layer is deposited. Thermal oxide equivalent removal amounts in the 150–300 Å range are typical and no different from mainstream Si UBM and RDL. The challenges come when dealing with particles and R_c management issues generated from working with organics.

19.2.3 PVD Adhesion Layer Deposition

Since Cu does not adhere well to organic passivation, an adhesion layer is required beforehand. Ti or TiW is commonly used with the material selected either for patterning integration reasons or even historical reasons (e.g. what was available at the time of development). For automotive products TiW is generally preferred because of its superior diffusion barrier properties and subsequent impact on long‐term device reliability. From a production perspective, Ti is preferred over TiW. TiW is a brittle material, and chambers can suffer from particle problems and relatively short mean wafers between cleans (MWBC) if thermal cycling and chamber furniture surface finish is not managed carefully. As only a flash layer is required for adhesion, films are relatively thin, typically in the 500 Å–1 kÅ range.

19.2.4 Cu Seed Layer Deposition

This is the final step in the process flow, the requirement being to deposit a relatively thin layer of Cu on the wafer to act as a nucleation layer for Cu ECD. Cu seeds are typically in the 1.5–3 kÅ range. Layers are thicker for structures with thicker passivation or narrower critical dimensions (CDs) where step coverage is reduced. With Cu ECD, minimum thicknesses of 20–50 nm on surfaces are required.

With the Cu seed layer deposited, wafers are passed back from the vacuum back end of the PVD system into their FOUPs at atmosphere via the equipment front‐end module (EFEM) for transfer on to the next process stage, namely, resist coating and then patterning and selective plating of the exposed Cu seed material to form the RDL.

19.3.1 Contamination

The epoxy mold and organic passivation materials used in FO‐WLP structures suffer badly from moisture absorption at atmosphere. Moisture and other organic‐based contaminants outgas when elevated to higher temperatures or placed under vacuum. If not addressed, the presence of contamination at the adhesion metal deposition stage can create electrical contact resistance and adhesion issues. Figure 19.5 shows typical residual gas analysis (RGA) of the outgassing characteristics of a 300 mm molded wafer when placed in a vacuum degas module, with wafer temperatures driven to 120 °C. Mass 18 [H₂O] and Mass 28 [CO/N₂] dominate. From background O₂ levels (and its proportion to N₂ in air), it is clear that the Mass 28 levels are predominantly CO [5].

Whereas conventional circuits built on silicon can withstand temperatures in excess of 400 °C and can be degassed rapidly without impacting system throughput, the mold and dielectrics used in FO‐WLP have heat tolerances closer to 120 °C for production, largely due to the T_g of the epoxy mold compound, which is approximately 150 °C. Temperatures exceeding this threshold can cause material decomposition and excessive wafer warping.

Degassing wafers at such low temperatures takes a longer amount of time to fully remove contaminants and can drastically reduce the throughput of a conventional sputter system that uses single‐wafer degas chamber technology. The data in Figure 19.5 shows that for a typical 300 mm molded wafer with polyimide (PI) organic passivation, it can take up to 30 minutes (1800 seconds) for contamination levels to return to initial values.

An ex situ oven bake prior to PVD can be used to reduce degas times, but depending on device performance requirements, this may not always be sufficient: moisture reabsorption between the oven and the PVD system has the potential to impact both plasma process stability in the PVD system and overall device electrical performance. Oven bake also requires additional investment and floor space and increases overall manufacturing process flow time.

For a mainstream UBM and RDL sputter system with single or even dual wafer degas configuration and no ex situ oven bake, throughput can be limited to <5 wafers per hour (wph), which is low compared with >30 wph throughputs usually achieved with traditional Si UBM and RDL processes based on inorganic passivation material such as silicon nitride (SiN). It is worth noting that more advanced passivation schemes for Si UBM and RDL involving organics such as low temperature cure PI or polybenzoxazole (PBO) can also suffer similar productivity problems, because of similar thermal budget restrictions. Compromises in throughput for both Si and FO‐WLP cases can be made (i.e. shorter degas times) but potentially at the expense of device electrical performance. It depends on the performance specifications for the packaged device.

19.3.2 Increased I/O Density

After successful degas, the molded wafer needs to be pre‐cleaned in a plasma etch module. This facilitates the removal of trace native oxide layers from exposed metal that the RDL will connect to. With the increase in density of interconnects as more complex dies are packaged using FO‐WLP techniques, there is a need for multiple levels of RDL to overcome interconnect congestion. At the uppermost level >70% of the wafer surface can be exposed metal contacts, areas much larger than those encountered in mainstream Si UBM and RDL (typically <20%).

For PVD systems with pre‐clean modules based on inductively coupled plasma (ICP) technology with ceramic chamber walls, this increase in exposed metal contact area presents a problem for RF stability. The pre‐clean process will involve an “over etch” to accommodate any cross‐wafer variation in the etch process. During this stage metal contacts on certain parts of the wafer will gradually be revealed as native oxide is cleared. As etching continues, exposed metal will be sputtered onto the ICP ceramic sidewalls. As metal coats up the chamber walls, the RF will couple through to the metal rather than the plasma, with the process rapidly falling out of control. Figure 19.6 shows an accelerated failure case, using wafers with 60% pure repeatedly etched Cu – i.e. no native oxide present after the wafer has been etched the first time.

PVD systems using diode etch technology, otherwise known as capacitively coupled plasma (CCP), benefit from operating with a metallic chamber wall and therefore avoid this coupling issue, but diode etch technology has its own drawbacks for use in FO‐WLP that will be explained later in this chapter.

19.3.3 Organic Passivation Particle Management

Due to the presence of organic passivation such as PI or PBO on FO‐WLP wafers, carbon‐based material buildup on the ICP chamber wall will take place during pre‐clean, as organic material is sputtered off the wafer surface in parallel to the native oxide on the contacts being removed. Organic material does not adhere well to ceramic surfaces and, if not carefully managed, can result in premature particle failure (Figure 19.7). Particle management in general becomes more critical as L/S dimensions are reduced for higher density packages.

19.3.4 Contact Resistance (R_c) Management

The use of organic passivation in FO‐WLP structures also introduces challenges for R_c during the pre‐clean step that intensify as the CDs of the features reduce. As the surface of the wafer is etched, native oxide is removed from the exposed metal contact, but the organic passivation is also physically bombarded. This ion bombardment damages the surface of the passivation, releasing carbon‐based (C‐based) volatiles, which, in turn, recontaminate the metal contacts the process is attempting to clean (Figure 19.8).

Aside from advanced technology node devices, power management‐based devices (PMIC, PMU) are particularly sensitive to this parasitic resistance issue because of the relatively high currents involved with their operation. High R_c can lead to increased power consumption, increased temperature, and resistance–capacitance (RC) time delays on certain device types, so management of this parameter during the UBM and RDL stage of the process flow can be critical to performance and yield.

19.3.5 Wafer Warpage

Epoxy‐molded wafers can be warped after curing, and the size and shape of the warpage hinge on the different size, density, and placement of the die. An FO‐WLP PVD system must therefore be able to minimize temperature‐induced shape shifting and accommodate wafers with high incoming bow. The majority threshold for bow is on average less than 6 mm for high density packages, as it is not easy to make uniformly thick, fine resolution conductors on a substrate exhibiting high warpage. This is one of the major challenges facing FO‐WLP packages on a large area panel format.

Although FO‐WLP 300 mm substrates involving glass or silicon carriers with RDL‐first typically exhibit bow in the 2–3 mm range, unsupported chips‐first 300 mm wafers can experience warpage up to 6 mm (Figure 19.9). For mold substrates >300 mm, 7–8 mm warpage is experienced. Traditional PVD systems for UBM and RDL have never had to process wafers with such large bow. Processing SEMI standard thickness Si meant that wafer bows were never more than 1 mm at most.

Often wafer handling clearances, robot arm velocities, and wafer position sensors are not compatible with wafers warped to this degree, preventing many existing PVD toolsets from being utilized. Temperature management techniques such cold electrostatic chuck (ESC) pedestals on PVD systems can also have wafer bow limitations, ruling some out of FO‐WLP process flows.

19.3.6 Capital Cost

Always on the radar of any packaging house but never more so than with FO‐WLP lines, cost‐effective sputtering must form an integral part of the PVD solution. On that basis, the PVD chamber design used must not be over‐engineered. Unlike mainstream Si interconnect PVD, topography is relatively low so high cost ionized PVD capability is not required. Neither are thick metal layers such as those used for the bond pad layers of die on advanced node devices. So high power, high deposition rate capability is not required either. PVD modules for mainstream Si applications are effectively over‐specified for UBM and RDL applications, with high capital equipment cost. This makes the overall performance benefits for adopting an FO‐WLP structure difficult to justify.

19.4.1 Solution for Contamination

Multi‐wafer degas (MWD) technology has emerged as a compelling solution to the degas throughput problem, enabling multiple wafers to be degassed in parallel before being individually transferred to subsequent process steps, without breaking vacuum. With this approach, wafers are dynamically pumped under clean, high vacuum conditions, with radiation heat transfer warming wafers directly to temperatures within the operating budget. The use of high vacuum radiative heating prevents contamination cross talk.

Each wafer can spend up to an hour inside the MWD, but because they are processed in parallel, a “dry” wafer is output for metal deposition every 60–90 seconds, at a rate of between 30 and 50 wafers per hour (depending on the wafer bows and film thicknesses involved). This approach increases PVD system throughput significantly compared with single‐wafer degas processing technology, and as lower cost materials emerge with even lower thermal budgets or worse outgassing behavior, longer degas times can be accommodated with no impact on throughput.

MWD technology has also been shown to eliminate the need for an ex situ bake prior to PVD, saving capital expenditure, floor space, and overall flow time for the manufacturer.

Figure 19.10 shows how normalized mean R_c and R_c spread across a 300 mm molded test vehicle wafer reduces with increased degas time (T_MAX = 120 °C), illustrating the time required for FO substrates to be left in vacuum degas conditions to achieve the best electrical performance [6].

19.4.2 Atmospheric Degas vs. Vacuum Degas

If a substrate involving organic material is not degassed sufficiently prior to pre‐clean, it produces high levels of outgassing that can affect plasma stability during etch and film quality (R_c) during subsequent sputter deposition. Locating the MWD station in the atmospheric front end of the PVD system to minimize complexity can impact the efficacy of the process. To demonstrate this, two identical PBO‐coated wafers were monitored using an RGA in a pre‐clean module during process: one originating from an atmospheric degas station and the other originating from a vacuum degas station – both wafers given the same 30 minute degas time beforehand at 120 °C. The data obtained (Figure 19.10) shows increased levels of outgassing (H₂O partial pressure) from the wafer that received an atmospheric degas, demonstrating that a vacuum‐based degas is more effective at removing moisture.

As previously explained, this increase in contamination during pre‐clean has implications for process plasma stability and potentially device electrical performance. Therefore, the decision to locate the MWD station in a high vacuum environment is validated. It should be noted that a vacuum‐based MWD approach is only feasible for systems based on pick/place robot wafer handling in the vacuum back end. Wafer handlers based on a carousel or “indexed” approach where wafers are supported by the handling system throughout the process flow are prevented from loading wafers into a multi‐slot chamber by the fundamental nature of their design. In those circumstances, multi‐slot degas hardware can only be located in the atmospheric side of the system and potentially suffer the problems with moisture reabsorption indicated by the data in Figure 19.11. Degas at atmosphere may also produce relatively poor temperature uniformity and risk of particulates if high flow purge gases are used in an attempt to resolve temperature uniformity issues.

In contrast, the MWD degasses wafers under high vacuum and uses radiative heat transfer, producing excellent WIW temperature uniformity (<5 °C), low particle levels as there are no purge gases, and no risk of moisture reabsorption or cross‐contamination because of the low vacuum conditions employed [7].

19.4.3 Solutions for Increased I/O Density

By inserting a discontinuous metal liner in the ICP chamber between the wafer and the ceramic chamber wall (i.e. a Faraday cage), it is possible to maintain the ICP effect while sputtering metal onto the sidewalls; the design of liner and RF antenna circuit ensures that a continuous band of metal is prevented from forming. With the liner installed, etch rate stability can now be maintained at levels previously experienced with low exposed Cu contact structures (Figure 19.12).

19.4.4 Solution for Particle Management

The presence of the metal liner on the chamber sidewall for exposed metal compatibility now also allows in situ metallic pasting to be employed to adhere problematic organic material to the sidewalls. Al‐coated silicon or Al‐coated metal disks are commonly used for this purpose. Preventative maintenance intervals can be extended to match adjacent PVD module maintenance activity timelines, with no detrimental impact on system uptime.

In situ coaxial pasting (co‐pasting) during the etch process significantly improves productivity further by reducing the frequency of wafer‐based pasting (typically every 12 wafers). With the co‐pasting approach, the “RF‐live” back sputter shield located around the platen is deliberately designed to be etched, sputtering metal away from the wafer, onto the sidewalls of the chamber, pasting down organics as the wafer etch process takes place (Figure 19.13).

Vapor phase decomposition (VPD) analysis during a 5000 wafer marathon showed that the use of this co‐pasting design does not adversely impact contamination levels detected on wafer (Figure 19.14), proving that the concept of sputtering metal away from the wafer is working successfully.

The co‐pasting concept is compatible with bowed molded wafers and has been optimized to prevent arcing. This solution is now running FO‐WLP production wafers at multiple sites. Co‐pasting increases the wafer‐based pasting interval by >100×, maintaining low particle levels throughout, even at small bin sizes (>0.2 μm) (Figure 19.15).

19.4.5 Solution for R_c Management

Common approaches to tackle this problem involve limiting wafer temperature during process, thus reducing the volatility of the C by‐products. Chilled pedestals and chamber furniture are commonplace as a result. In addition to reducing contaminant volatility, vacuum pumping speed is increased to pump away contaminants before they have an opportunity to react with the exposed metal contacts. The use of in situ pasting for particle control reasons can also be used for R_c management purposes, with the co‐pasting technique producing stable R_c performance without the need for frequent wafer pasting (Figure 19.16).

19.4.6 Why Soft ICP Etch Is Best

Given the challenges of large exposed metal and organic material adhesion with ICP ceramic walls, it would be tempting to employ a CCP or diode etch approach to pre‐clean, as the single source concept in the form of a RF‐driven platen allows the chamber walls to be of metal construction. The diode etch approach has several disadvantages however. First, the diode etch concept, being single source, requires relatively high bias voltages to initiate and sustain a plasma discharge (Figure 19.17).

Where an ICP etch generates wafer biases in the <500 V range, a diode etch module typically works in bias ranges >3000 V. The higher ion bombardment energy involved produces significantly higher levels of contaminant release from the organic passivation on the wafer. For an equivalent maximum wafer temperature during etch, CO partial pressures can be an order of magnitude higher in a diode etch system compared with ICP. This has obvious implications for R_c.

The high ion energy will also cause a temperature increase that will need additional cool steps given the thermal budget restrictions of molded wafer processing. The cool steps will in turn impact module throughput, assuming the degas throughput bottleneck with an MWD approach has already been solved. With mainstream Si UBM and RDL PVD systems, these problems can be overcome through the use of ESC clamping combined with backside cooling gas to maintain wafer temperatures at low levels, minimizing contaminant volatility. With molded wafer processing, however, ESCs are not reliably compatible because of the excessive wafer bows that can be encountered.

Another disadvantage of diode etch is that etch rate is typically 30–50% of an ICP equivalent, limiting the throughput of the system after the degas bottleneck is addressed.

Finally, the diode etch process is less directional than ICP due to its single source and higher discharge pressures. As CDs reduce the aspect ratio of contact, topography will inevitably increase. For a diode configuration this will mean longer etches are needed to remove native oxide in the base of the contact. Conversely, the ICP etch, being dual source and low pressure (<2 mT), produces an anisotropic etch, directional in nature. As aspect ratios increase, the ICP etch is less affected, and throughputs can be maintained.

19.4.7 Solution for Wafer Warpage

To successfully handle substrates with increased warpages, several aspects of the system design need to be modified. At the atmospheric front end, FOUPs will use 13 slots instead of 25. This enables increased clearances for wafer transfers in and out of FOUPs by the EFEM robot arm. Vertical clearances at the EFEM Aligner and Transport Module Slot Valves are also increased.

Robot arm velocities are adjusted to prevent wafer movement during transfers, and processes are tuned to minimize additional warpage generation caused by excessive temperature change. In addition, optics in front of each process module position are used to detect wafer movement during wafer transfers. Corrective adjustments are then transmitted to the robot arm and applied during the next arm move, recentering the wafer position in time for the next process step. PVD systems have been designed to cope with wafer bows up to 10 mm. Performance has been validated in FO‐WLP production [10].

19.4.8 Solution for Capital Cost Reduction

PVD RDL seed depositions are relatively simple, and for that reason it is important to use hardware that does not exceed requirements. Traditional front‐end‐of‐line (FEOL) PVD chambers used in semiconductor device fabrication facilities are designed to offer features such as high deposition rates, directionality, and advanced uniformity control, which are not critical for FO‐WLP. A basic conventional PVD module will meet the requirements. A picture of a conventional magnetron sputter PVD module is shown in Figure 19.18 and is specifically designed for BEOL processing. The simplicity of the design allows cost savings to be passed on to the user, contributing to the overall task of minimizing the costs to run the FO‐WLP application.