Index
Note: Page numbers followed by “f” and “t” refer, respectively, to figures and tables.
A
ADVP algorithm, See Alternating direction TSV planning (ADVP) algorithm
ALD processing, See Atomic layer deposition (ALD) processing
Alpha microprocessors, 338
Always on decoupling capacitance topology, 555f
Amorphous-Si (a-Si), 40–41
Analytic placement for 3-D ICs, 236–239
Ansys quick three-dimensional electromagnetic field solver, 106
Application specific integrated circuit (ASIC), 606
Architectures, 3-D circuit
classification of wire limited circuits, 606–607
clock architecture
circuit architecture, 454–458
clock signal distribution
clock distribution network structures within test circuit, 458–463
clock distribution network topologies incorporating 3-D via impedance, 463–466
evaluation, 467–473
MITLL fabrication technology, 449–453
field programmable gate array (FPGA), 639–645
applications, 639–642
power dissipation, 644
microprocessor and memory circuits
cache memory design, 610–613
microprocessor logic blocks, 608–610
3-D microprocessor–memory circuit, 613–614
networks-on-chip
design aids
evaluation under different traffic scenarios, 635–639
3-D networks-on-chip simulator, 633–635
performance and power analysis
interconnect parameters, 623–625
network parameters, 624–625
performance tradeoffs, 625–629
3-D integrated circuit–3-D networks-on-chip, 627–629
3-D integrated circuit–2-D networks-on-chip, 626–627
2-D integrated circuit–3-D networks-on-chip, 625–626
power consumption
3-D integrated circuit–3-D networks-on-chip, 631–632
3-D integrated circuit–2-D networks-on-chip, 630–631
2-D integrated circuit–3-D networks-on-chip, 630
topologies, 616–617
zero-load latency, 617–621
overview, 605
Asynchronous data transmission and recovery, 145–147
Asynchronous inductive link, transceiver circuit of, 147f
Atomic layer deposition (ALD) processing, 181
B
Benzocyclobutene (BCB), 358–359
copper embedding in, 26
BEOL, See Back end of line (BEOL)
Bonding of three-dimensional ICs, 53–55
BOX, See Buried oxide (BOX)
Buffer delay model, 483–484
Buried oxide (BOX), 48
Burst data transmission, 148–149
C
Cache memory, 3-D design of, 610–613
CACTI tool, 225
CAD, See Computer-aided design (CAD)
CBA, See Combined bucket and 2-D array (CBA)
Chemical mechanical planarization (CMP), 42
Clock distribution networks, three-dimensional, 423–440
prebond testable 3-D clock trees, synthesis techniques for, 431–440
standard synthesis techniques, 424–431
Clock paths, effects of process variations on, 482–495
clock skew distribution in 3-D clock trees, 487–490
delay distribution of clock paths, 484–487
skew variations in 3-D clock tree topologies, 491–495
statistical delay model of clock buffers, 483–484
Closed-form temperature models, 303–309
Coefficient of thermal expansion (CTE), 51–52
Communication fabrics, 651
Compact capacitance model
physical parameters of, 78–80
through silicon via capacitance, 78–79
through silicon via model including the effects of depletion region, 79–80
of three-dimensional via, 94–103
closed-form capacitance model of a three-dimensional via, 100–102
compact models of through silicon via capacitance, 95–100
per cent variation in capacitance, 103
per cent variation in coupling capacitance, 103
Compact conductance model
physical parameters of, 81–82
through silicon via conductance, 81–82
of three-dimensional via, 104–105
compact models of through silicon via conductance, 105
Compact inductance model
physical parameters of, 75–78
high frequency effects, 76
internal and external magnetic field, 76
loop inductance, 77–78
through silicon via inductance, 75–76
of three-dimensional via, 85–94
compact models of through silicon via inductance, 85–91
inductance of equal length three-dimensional vias, 91–92
inductance of nonequal length 3-D vias, 92–93
per cent variation in inductance, 93–94
Compact resistance model
physical parameters of, 73–75
effect of barrier thickness on resistivity, 74
high frequency effects, 73–74
temperature effect, 74–75
through silicon via resistance, 73
of three-dimensional via, 82–85
closed-form resistance model of a three-dimensional via, 85–94
compact models of through silicon via resistance, 82–83
per cent variation in resistance, 85
Complementary metal oxide semiconductor (CMOS), 1
Computer-aided design (CAD)
algorithm and tool challenges, 11
Contactless 3-D ICs, 55–58
capacitively coupled 3-D ICs, 56–57
inductively coupled 3-D ICs, 57–58
Copper electroplating, 63
control logic for, 457
Crosstalk noise on adjacent on-chip components, 152–158
case study, 153–155
crosstalk effects due to an inductive link, 152–153
inductive link arrays, crosstalk noise effects caused by, 155
noise sensitivity of power network topologies, 155–158
CTS algorithms, See Clock tree synthesis (CTS) algorithms
Cylinder, modeling a three-dimensional via as, 71–73
D
DC pads, 576–577
for 3-D power distribution networks, 550–556
Delay variability model for 2-D and 3-D circuits, 479f
Design, three-dimensional integrated circuits
cache memory design, 610–613
interconnect challenges in 3-D integration, 10
Dielectric materials, system-on-package, 20–21
Die-to-die integration, 51–52
DME technique, See Deferred-merge embedding (DME) technique
Double-gate metal oxide semiconductor field effect transistors for stacked 3-D ICs, 42–44
DTM, See Dynamic thermal management (DTM)
DVFS, See Dynamic frequency voltage scaling (DVFS)
Dynamic power consumption, interconnect line with repeaters, 621–622
Dynamic thermal management (DTM), 345–358
SW/HW thermal management framework for 3-D chip multiprocessor, 349–358
of 3-D chip multiprocessors
with a single memory tier, 347–349
with multiple memory tiers, 353–358
E
EDP, See Energy delay product (EDP)
eDRAM, 421
Electrostatic discharge (ESD) diodes, 421
distributed, 268
of intertier interconnect, 257–260
ELO, See Epitaxial lateral overgrowth (ELO)
Energy delay product (EDP), 357
Enhanced thermal conductivity, thermal management through, 358–374
thermal via planning under temperature constraints, 367–368
thermal via planning under temperature objectives, 360–366
thermal wire insertion, 372–374
Environmental variability, 475
Epitaxial lateral overgrowth (ELO), 42
ESD diodes, See Electrostatic discharge (ESD) diodes
F
Fabrication steps for a 3-D IC process, 49f
Fabrication techniques for 3-D ICs, 50t
FDSOI, See Fully depleted silicon-on-insulator (FDSOI)
FEOL, See Front end of line (FEOL)
Field programmable gate array (FPGA), 8
applications, 639–642
power dissipation, 644
Finite element method (FEM) solver, 317
Finite element method (FEM) techniques, 105
Floorplanning techniques, 204–208
sequence pair technique, 205–208
thermal driven, 334–344
Floorplanning techniques for 3-D ICs with through silicon via planning, 214–226
enhanced wirelength metrics for intertier interconnects, 214–216
microarchitecture aware 3-D floorplanning, 225–226
practical considerations for floorplanning with through silicon via planning, 221–224
simultaneous floorplanning and through silicon via planning, 216–219
through silicon via planning as a postfloorplanning step, 219–221
Force directed method
placement using, 226–230
Force directed placement of 3-D ICs, 231–234
Four-bit counters, 457
FPGA, See Field programmable gate array (FPGA)
Free outline technique, 204
Front end of line (FEOL), 58
Fully depleted silicon-on-insulator (FDSOI)
3-D circuits, 582–583
G
Gallium arsenide (GaAs), 120
GENESYS tool, 225
Global 3-D clock distribution networks, 417–422
Global interconnect models, 489
GLOPTIPOLY optimization solver, 274
Green’s function, 328–329
Ground network inductance, 127–128
Ground-signal-ground (GSG) output pads, 582
Ground-signal-ground-signal-ground (GSGSG), 577
H
Heat propagation, 369
Heat transfer in 3-D ICs, 296–303
liquid cooling, 298–303
design considerations for liquid cooled heat sinks, 300–303
Heterogeneous 3-D integrated circuit, 120f
Heterogeneous substrate coupling, 120–124
common circuits and compatible substrate types, 120
noise model reduction for different substrate materials, 121–124
resistive properties of different substrate materials, 121
hMETIS algorithm, 210–212
HP 16058-60003 Personality Board, 385–386
HP 4145B Semiconductor Parameter Analyzer, 385–386
HPWL model, See Half perimeter wirelength (HPWL) model
H-tree, 417, 417–419, 418f, 419, 419f, 458–459, 460f, 461, 461–462, 461f, 469, 469, 469–470, 470–471, 472, 490
Hybrid methodologies for thermal management, 375–378
I
ILD, See Interlayer dielectric (ILD)
Inductive links, three-dimensional ICs with, 137
intertier power transfer, 158–161
on-chip inductors for intertier links, 140–143
design flow for inductive link coils, 143
geometry and electrical characteristics of inductor, 142–143
intertier coupling efficiency, 140–142
transmitter and receiver circuits, 143–149
asynchronous data transmission and recovery, 145–147
burst data transmission, 148–149
design of synchronous inductive link transceivers, 143–145
wireless on-chip communication, challenges for, 149–158
adjacent on-chip components, crosstalk noise on, 152–158
case study, 153–155
crosstalk effects due to an inductive link, 152–153
inductive link arrays, crosstalk noise effects caused by, 155
noise sensitivity of power network topologies, 155–158
inductive links, crosstalk between, 151–152
performance and area analysis, 149–151
wireless on-chip communication interfaces, 138–140
inductive links, 138–140
Intel Core i5 technology, 357
Interactive Characterization Software, 385–386
Interconnect delay
improvement in, 264–266
intertier, 260–261
Interconnect issues in integrated systems, 4–6
Interconnect tree via placement algorithm (ITVPA), 287
pseudocode of, 287f
Interconnects
architectures, 4–5
design challenges in 3-D integration, 10
optical interconnects, 6
pipelining, 5–6
prediction models
projections for 3-D integrated circuits, 170–173
3-D integrated circuits, 166–170
2-D circuits, 163–166
shielding, 5
system-in-package vertical interconnects
area array, 26–27
peripheral, 23–26
Interdigitated power/ground lines, 566–567
Interlayer dielectric (ILD), 46–47
Interposer based system integration, 188–191
interposer build-up configurations, 191
interposer manufacturing features, cost of, 189–191
cost of die-to-die interconnect processing, 190
cost of processing metal planes and metal–insulator–metal capacitors, 190–191
cost of processing microbumps and Cu pillars, 191
cost of through silicon via processing, 189–190
Intertier coupling efficiency, 140–142
Intertier interconnect delay, 260–261
Intertier interconnect models, 254–255
Intertier interconnect tree, 282f
timing driven via placement for, 282–284
Intertier interconnects, enhanced wirelength metrics for, 214–216
Intertier power transfer, 158–161
Inverse Laplace transform, 533
IoT, See Internet of Things (IoT)
J
K
Keep out zone (KOZ) of TSVs, 234–235
Keithley 2420 SourceMeter, 385–386
L
Laplace multipliers, 352
Laser crystallization, 39–41
LDPC decoder, See Low density parity check (LDPC) decoder
Leakage power, interconnect line with repeaters, 622
Liquid cooled heat sinks, design considerations for, 300–303
Liquid cooling, 298–303
Low temperature oxide (LTO), 41–42
Low density parity check (LDPC) decoder, 245
LTO, See Low temperature oxide (LTO)
M
Manhattan distance, 165
Manufacturing technologies for 3-D ICs, 37
contactless 3-D ICs, 55–58
capacitively coupled 3-D ICs, 56–57
inductively coupled 3-D ICs, 57–58
monolithic 3-D ICs, 38–48
double-gate metal oxide semiconductor field effect transistors, 42–44
laser crystallization, 39–41
molecular bonding, 45–48
seed crystallization, 41–42
through silicon via (TSV)/intertier via, 3-D ICs with, 48–55
bonding of 3-D ICs, 53–55
die-to-die integration, 51–52
wafer level integration, 48–51
vertical interconnects for 3-D ICs, 58–64
Maxwell’s equations, 105
Means-and-medians (MMM)-TB algorithm, 513–514
Mercury cadmium telluride (HgCdTe), 120
Mesh based thermal models, 310–324
thermal model of through silicon vias, 313–321
signal through silicon vias, 320–321
thermal through silicon vias, 313–320
thermal models of microchannels for liquid cooling, 321–324
Metal–insulator–metal (MIM) capacitors, 521–522
Metalorganic chemical vapor deposition (MOCVD), 63
MMM-TSV-Bound algorithm, 425
Method of moments (MOMs), 105
Microarchitecture aware 3-D floorplanning, 225–226
Microvias, 19
MIM capacitors, See Metal–insulator–metal (MIM) capacitors
Minimum spanning tree (MST), 233
MITLL fabrication technology, 449–453
design kits for, 452–453
MIT Lincoln Laboratory 3-D IC process, through silicon via characterization of (case study), 107–116, 108–109
effect of the return path on 3-D via inductance, 114–116
effects of 3-D via placement on shielding, 111–114
RLC coupling between two 3-D vias, 109–111
RLC extraction of a single 3-D via, 109
MMM algorithm, See Method of means and medians (MMM) algorithm
Molecular bonding, 45–48
MOMs, See Method of moments (MOMs)
Monolithic three-dimensional ICs, 38–48
double-gate metal oxide semiconductor field effect transistors, 42–44
laser crystallization, 39–41
molecular bonding, 45–48
seed crystallization, 41–42
Monte Carlo simulations, 484
“More Moore” path, 2
“More than Moore” path, 2
MST, See Minimum-spanning tree (MST)
Multi-group 3-D clock topology, 493f
Multi-level interconnect architectures, 4–5
N
Networks-on-chip (NoC) architecture, 342
design aids
evaluation under different traffic scenarios, 635–639
3-D networks-on-chip simulator, 633–635
performance and power analysis
interconnect parameters, 623–625
network parameters, 624–625
performance trade-offs, 625–629
3-D IC–2-D networks-on-chip, 626–627
3-D IC–3-D networks-on-chip, 627–629
2-D IC–3-D networks-on-chip, 625–626
power consumption
3-D integrated circuit–2-D networks-on-chip, 630–631
3-D integrated circuit–3-D networks-on-chip, 631–632
2-D integrated circuit–3-D networks-on-chip, 630
topologies, 616–617
zero-load latency, 617–621
NMOS synchronous rectifier, 521–522
Noise coupling, in heterogeneous 3-D ICs, 119
frequency response, 124–127
isolation efficiency, 124
transfer function, 124–127
heterogeneous substrate coupling, 120–124
common circuits and compatible substrate types, 120
noise model reduction for different substrate materials, 121–124
resistive properties of different substrate materials, 121
techniques to improve noise isolation, 127–134
distance between aggressor and victim, 128–134
ground network inductance, 127–128
Nonconductive particle paste, 27
Normalized average power consumption (NAPC), 277–278
Nusselt number, 301–302
O
On-chip decoupling capacitances, 550–551
On-chip inductors for intertier links, 140–143
geometry and electrical characteristics of inductor, 142–143
inductive link coils, design flow for, 143
intertier coupling efficiency, 140–142
Outsourced semiconductor assembly and test (OSAT) fabrication compatible tool, 178
P
Pairwise clock skew, 483
PCB, See Printed circuit board (PCB)
Performance improvement (PI), 356
Performance loss (PL), 356
Physical design techniques for 3-D ICs, 203
floorplanning techniques, 204–208
sequence pair technique, 205–208
floorplanning techniques for 3-D ICs with through silicon via planning, 214–226
enhanced wirelength metrics for intertier interconnects, 214–216
microarchitecture aware 3-D floorplanning, 225–226
practical considerations for floorplanning with through silicon via planning, 221–224
simultaneous floorplanning and through silicon via planning, 216–219
through silicon via planning as a postfloorplanning step, 219–221
layout tools, 250–251
routing techniques, 245–250
Physical vapor deposition (PVD), 63
PI, See Performance improvement (PI)
PL, See Performance loss (PL)
analytic placement for 3-D ICs, 236–239
force directed placement of 3-D ICs, 231–234
placement for 3-D ICs using simulated annealing, 239–241
placement process, objectives in, 234–235
supercell-based placement for 3-D circuits, 241–245
using force directed method, 226–230
Planar clock distribution networks, synthesis techniques for, 410–417
deferred-merge embedding method, 413–417
method of means and medians (MMM) algorithm, 411–412
Plasma enhanced chemical vapor deposition (PECVD), 32
PLL, See Phase locked loop (PLL)
Point contact transistor, historical perspective, 1
Polylithic 3-D ICs, 38
Postfloorplanning step, through silicon via planning as, 219–221
Power consumption
networks-on-chip
3-D integrated circuit–2-D networks-on-chip, 630–631
3-D integrated circuit–3-D networks-on-chip, 631–632
2-D integrated circuit–3-D networks-on-chip, 630
decoupling capacitance for, 550–556
power gated 3-D ICs, 552–556
power delivery challenge, 521–530
multi-level power delivery for 3-D ICs, 526–530
3-D power distribution networks, models for, 530–540
electro-thermal model, 536–540
through silicon via (TSV) technologies to mitigate power supply noise, 540–550
effect of TSV tapering on power distribution networks, 549–550
enhanced power integrity by exploiting TSV paths, 545–548
wire sizing methods in, 557–561
Power delivery network topologies, 157f
Power density reduction, thermal management through, 334–358
dynamic thermal management (DTM) techniques, 345–358
SW/HW thermal management framework, 349–358
of 3-D chip multiprocessors with a single memory tier, 347–349
of 3-D chip multiprocessors with multiple memory tiers, 353–358
thermal driven floorplanning, 334–344
thermal driven placement, 344–345
Power distribution networks
effect of TSV tapering on, 549–550
optimization framework for, 561f
characteristics of, 588–602
design considerations based on experimental results, 593–602
pre-layout design considerations, 590–593
experimental results, 584–588
source follower noise detection circuits, 590f
architecture, 578–582
layouts and schematics of 3-D test circuit, 567–577
3-D IC fabrication technology, 582–583
3-D power topologies, 566–567
wire bonded test circuit, 589f
Power gated 3-D ICs
decoupling capacitance topologies for, 552–556
skitter versus phase and frequency of, 507–512
Prandtl number, 301–302
Prebond testable 3-D clock trees, synthesis techniques for, 431–440
PRNG, See Pseudorandom number generators (PRNG)
Process variations in datapaths within 3-D ICs, 477–482
Processing elements (PEs), 342
Processing heterogeneity, 3
PTM 45 nm CMOS, 489
PVD, See Physical vapor deposition (PVD)
R
RDL, See Redistribution layers (RDL)
Reactive ion etching (RIE), 39
Rectilinear minimum spanning tree (RMST) algorithm, 434–435
Redistribution layers (RDL), 29
Resistive noise, 520
RF pads, 568–569
RIE, See Reactive ion etching (RIE)
RMST algorithm, See Rectilinear minimum spanning tree (RMST) algorithm
Rosa expressions, 91–92
S
Seed crystallization, 41–42
SEG, See Selective epitaxial growth (SEG)
Selective epitaxial growth (SEG), 42
Sequence pair technique, 205–208
Sequential 3-D ICs, 38
Shielding, 5
Short-circuit power, interconnect line with repeaters, 622
Silicon, 120
Silicon system, 3-D, 649
Silicon-on-insulator (SOI) substrate, 38
via placement algorithm, 273
placement for 3-D ICs using, 239–241
Simulation based models, 533
“Sink TSVs”, 494
Skitter related tradeoffs in 3-D ICs, 503–512
skitter versus length of clock paths, number of tiers, and power dissipation, 503–507
skitter versus phase and frequency of power supply noise, 507–512
Stacking methods for transistors, circuits, and dies, 16–18
Steady-state temperature (SST), 352
Substrate noise coupling, See Noise coupling, in heterogeneous 3-D ICs
Sulphurhexafluoride, 60–61
Supercell-based placement for 3-D circuits, 241–245
global 3-D clock distribution networks, 417–422
planar clock distribution networks, synthesis techniques for, 410–417
deferred-merge embedding method, 413–417
method of means and medians (MMM) algorithm, 411–412
practical considerations of 3-D clock tree synthesis, 440–446
prebond testable 3-D clock trees, synthesis techniques for, 431–440
standard synthesis techniques, 424–431
further reduction of through silicon vias in synthesized clock trees, 428–431
metalizing of walls, 27–28
overview, 17
technologies for, 21–28
vertical interconnect manufacturing
area array, 26–27
peripheral, 23–26
wire bonding, 22–23
System-on-chip (SoC), 15–16
System-on-package (SoP), 18–21
dielectric materials, 20–21
manufacturing and design challenges, 19
microvias, 19
subsystems, 19
T
TAB, See Tape adhesive bonding (TAB)
Tape adhesive bonding (TAB), 23–24
T-connection, 27–28
TEOS oxide, See Tetraethylorthosilicate (TEOS) oxide
Tetraethylorthosilicate (TEOS) oxide, 179
TFTs, See Thin film transistors (TFTs)
Thermal analysis techniques, 324–329
Thermal coupling in 3-D integrated circuits (case study), 381
design considerations based on experimental results, 395–401
additional design considerations, 401
effect of block placement on hot spot formation and mitigation techniques, 395
horizontal and vertical thermal conduits, 395–399
multiple aligned active blocks, 399
multiple nonaligned active blocks, 399–401
setup and experiments, 384–394
thermal propagation test circuit, 382–384
3-D IC fabrication technology, 383
3-D test circuit, 383–384
verification of experimental results with simulations, 401–408
comparison to experimental results, 403–407
effect of density of TSVs on thermal coupling, 407–408
simulation setup and tools, 403
enhanced thermal conductivity, thermal management through, 358–374
thermal via planning under temperature constraints, 367–368
thermal via planning under temperature objectives, 360–366
thermal wire insertion, 372–374
hybrid methodologies, 375–378
power density reduction, thermal management through, 334–358
dynamic thermal management (DTM) techniques, 345–358
SW/HW thermal management framework, 349–358
of 3-D chip multiprocessors with a single memory tier, 347–349
of 3-D chip multiprocessors with multiple memory tiers, 353–358
thermal driven floorplanning, 334–344
thermal driven placement, 344–345
Thermal modeling and analysis, 295
closed-form temperature models, 303–309
heat transfer in 3-D ICs, 296–303
liquid cooling, 298–303
design considerations for liquid cooled heat sinks, 300–303
mesh based thermal models, 310–324
thermal model of through silicon vias, 313–321
signal through silicon vias, 320–321
thermal through silicon vias, 313–320
thermal models of microchannels for liquid cooling, 321–324
thermal analysis techniques, 324–329
Thermal resistance, 298–299
Thermal through silicon vias (TTSVs), 295–296, 313, 313, 316f, 317, 318f, 321, 359, 360, 360–361, 361, 361, 361, 361–363, 363, 363, 363, 363, 363–365, 365, 365, 367, 368, 372, 372, 372, 381
Thermal wire insertion, 372–374
Thevenin network, 549
Thin film transistors (TFTs), 41
delay variation of buffer stages, 496–500
model of skitter in 3-D clock trees, 500–503
skitter related tradeoffs in 3-D ICs, 503–512
synthesis of, 423–440
synthesized clock trees, effect of skitter on, 512–516
3-D clock tree topologies, skew variations in, 491–495
Three-dimensional integration
architecture, See Architectures, 3-D circuit
challenges
computer-aided design algorithms and tools, 11
global interconnect design, 10
technological/manufacturing limitations, 9
testing, 9–10
thermal issues, 10
comparison of 3-D system cost, 195–197
components of 3-D stacked system, 193–194
cost of 3-D integration components, 194–195
dependence of 3-D system cost on active die size, 197–198
features and opportunities, 7–8
MITLL fabrication technology, 449–453
variation of interposer process yield and prestack fault coverage, 198–200
vertical integration, 6–11
Three tier FDSOI 3-D circuit, 255f
Through glass vias (TGVs), 32
Through silicon via (TSV), electrical properties of, 67
compact capacitance model of a 3-D via, 94–103
closed-form capacitance model of a 3-D via, 100–102
compact models of through silicon via capacitance, 95–100
per cent variation in capacitance, 103
per cent variation in coupling capacitance, 103
compact capacitance models, physical parameters of, 78–80
through silicon via capacitance, 78–79
through silicon via model including the effects of the depletion region, 79–80
compact conductance model of a 3-D via, 104–105
compact models of through silicon via conductance, 105
compact conductance models, physical parameters of, 81–82
through silicon via conductance, 81–82
compact inductance model, 85–94
closed-form inductance model, 91–93
inductance of equal length 3-D vias, 91–92
inductance of nonequal length 3-D vias, 92–93
compact models of through silicon via inductance, 85–91
per cent variation in inductance, 93–94
compact inductance models, physical parameters of, 75–78
high frequency effects, 76
internal and external magnetic field, 76
loop inductance, 77–78
through silicon via inductance, 75–76
compact resistance model of a 3-D via, 82–85
closed-form resistance model of a 3-D via, 85–94
compact models of through silicon via resistance, 82–83
per cent variation in resistance, 85
compact resistance models, physical parameters of, 73–75
effect of barrier thickness on resistivity, 74
high frequency effects, 73–74
temperature effect, 74–75
through silicon via resistance, 73
electrical characterization through numerical simulation, 105–107
Ansys quick three-dimensional electromagnetic field solver, 106
numerical analysis of through silicon via impedance, 106–107
electrical model, 70–71
modeling a three-dimensional via as a cylinder, 71–73
physical characteristics, 69–70
through silicon via characterization of MIT Lincoln Laboratory three-dimensional IC process (case study), 107–116, 108–109
effect of the return path on 3-D via inductance, 114–116
effects of 3-D via placement on shielding, 111–114
RLC coupling between two 3-D vias, 109–111
RLC extraction of a single 3-D via, 109
Through silicon via (TSV)/intertier via, 3-D ICs with, 48–55
bonding of 3-D ICs, 53–55
die-to-die integration, 51–52
wafer level integration, 48–51
Through silicon via (TSV) processing options, 176–188
comparison of TSV processing cost, 186–188
processing of 10×100 TSV geometry, 187
processing of 5×50 TSV geometry, 187
scaling through silicon via geometries, 187–188
cost comparison of TSV processing steps, 178–186
backside processing, 185–186
TSV barrier and Cu seed processing, 181–182
TSV chemical mechanical planarization processing, 184–185
TSV Cu plating and effect on chemical mechanical planarization, 182–184
TSV liner opening for TSV last flow, 180
TSV liner processing, 179–180
TSV lithography, 178
TSV silicon etch, 178–179
TSV flows and geometries, 177
Through silicon via (TSV) technologies, 16, 32–33, 32, 60–61, 253, 295–296, 299–300, 302, 302, 312, 313, 449–450, 491, 491, 494, 520–521, 539–540, 566, 586–587, 590–591, 650
effect of TSV tapering on power distribution networks, 549–550
enhanced power integrity by exploiting TSV paths, 545–548
equivalent electrical model of, 466f
to mitigate power supply noise, 540–550
overview, 16
Through silicon via impedance, numerical analysis of, 106–107
Timing optimization, for multiterminal interconnects
multiterminal interconnect via placement heuristics, 284–287
interconnect trees, 285–286
single critical sink interconnect trees, 286–287
notation, 283t
timing driven via placement for intertier interconnect trees, 282–284
via placement algorithms for interconnect trees
interconnect tree via placement algorithm (ITVPA), 287
optimization outcomes and comparison, 288–292
single critical sink interconnect tree via placement algorithm, 288
Timing optimization, for two terminal interconnects
intertier interconnect models, 254–255
multiple-intertier vias, two terminal interconnects with, 266–278
distributed Elmore delay model, 268
GLOPTIPOLY optimization solver, 274
two terminal via placement
algorithm, 272
heuristic, 269–272
via placement algorithm, 273–278
two terminal interconnects with multiple interplane vias
two terminal via placement
two terminal nets with a single intertier via, 256–266
Elmore delay model of intertier interconnect, 257–260
improvement in interconnect delay, 264–266
intertier interconnect delay, 260–261
optimum via location, 261–264
Timing optimization, for multiterminal interconnects
via placement algorithms for interconnect trees
single via placement optimum formal proof, 655
Transistor and circuit level stacking, 17–18
TRR, See Tilted rectangular region (TRR)
TSV technologies, See Through silicon via (TSV) technologies
TTSVs, See Thermal through silicon vias (TTSVs)
TTV, See Total thickness variation (TTV)
TTVPA, See Two terminal via placement algorithm (TTVPA)
Two-dimensional power distribution networks, 565
2.5-D and three-dimensional integration, comparison of processing cost for, 192–200
comparison of 3-D system cost, 195–197
components of 3-D stacked system, 193–194
cost of 3-D integration components, 194–195
dependence of 3-D system cost on active die size, 197–198
variation of interposer process yield and prestack fault coverage, 198–200
interposer materials, 30–31
metallization processes, 31–32
vertical interconnects, 32–34
V
Variability issues in 3-D ICs, 475
effect of process and power supply variations on 3-D clock distribution networks, 495–516
delay variation of buffer stages, 496–500
effect of skitter on synthesized clock trees, 512–516
model of skitter in 3-D clock trees, 500–503
skitter related tradeoffs in 3-D ICs, 503–512
effects of process variations on clock paths, 482–495
clock skew distribution in 3-D clock trees, 487–490
delay distribution of clock paths, 484–487
skew variations in 3-D clock tree topologies, 491–495
statistical delay model of clock buffers, 483–484
process variations in datapaths, 477–482
Vertical integration, 6–11
Vertical interconnects for 3-D ICs, 58–64
Voltage regulation module (VRM), 519–520
VRM, See Voltage regulation module (VRM)
W
Wafer bonding, materials used for, 54t
Wafer level integration, 48–51
Wavelength division multiplexing (WDM), 6
WBottom sensor, 395
Wire bonding, system-in-package, 22–23
Wire sizing algorithm, 277
Wire sizing methods in 3-D power distribution networks, 557–561
Wire variations
Wireless interchip communication, 137–138
Wireless on-chip communication, challenges for, 149–158
crosstalk between inductive links, 151–152
crosstalk noise on adjacent on-chip components, 152–158
case study, 153–155
crosstalk effects due to an inductive link, 152–153
inductive link arrays, crosstalk noise effects caused by, 155
noise sensitivity of power network topologies, 155–158
performance and area analysis, 149–151
Wireless on-chip communication interfaces, 138–140
inductive links, 138–140
X
Xilinx field programmable gate arrays (FPGAs), 8
X-tree, 417
Y
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