19.1.1 3-D Power Topologies

Interdigitated power/ground lines are used in each of the power network topologies. There are five main objectives for the test circuit: (i) determine the peak and average noise within the power and ground distribution networks, (ii) determine the effects of the board level decoupling capacitors on reducing power noise, (iii) explore the effects of a dedicated power/ground plane on power noise, (iv) investigate the effects of the TSV density on the noise characteristics of the power network, and (v) evaluate the resonant characteristic frequency of each power network topology. The three topologies are illustrated in Fig. 19.1. The difference between the left (Block 1) and central (Block 2) topologies is the number of TSVs, where the latter topology contains two-thirds the number of TSVs. The third topology (Block 3) replaces the interdigitated power and ground lines on the second device plane with two metal planes to assess the benefit of allocating dedicated power and ground planes to deliver current to the loads within a 3-D system. The interdigitated power and ground lines are both 15 μm wide and separated by a 1 μm space for all three power distribution networks. The power and ground planes of Block 3 are separated by a 1 μm space of inter-layer dielectric composed of plasma etched, chemical vapor deposited tetraethyl orthosilicate (TEOS). Based on the experimental results, greater insight into the noise propagation properties of these 3-D power network topologies is provided, as discussed below.

19.1.2 Layouts and Schematics of the 3-D Test Circuit

The components of both the noise generation and noise detection circuits are described in this section. Layout and schematic views of the various sections of the test circuit are provided. The transistor dimensions of the various circuits are also included in the circuit schematics. The minimum sized transistor length is 150 nm. Most transistors are designed, however, with a 200 nm channel length (matching the dimensions of the standard library). A few circuits, such as the ring oscillators (RO), are designed with larger channel lengths (see Fig. 19.5 and Table 19.1). A layout view of the overall test circuit is shown in Fig. 19.2. Also shown in this figure are the three blocks discussed in this chapter and a fourth block for evaluating a 3-D DC-to-DC buck converter [703].

As previously mentioned, each of the three blocks includes two sets of circuits: noise generation and noise detection circuits. In addition to these circuits, calibration circuits are included to evaluate the gain and bandwidth of the source follower noise sensing devices. Each block contains the calibration circuits, but one set of calibration circuitry is sufficient to adequately characterize the gain and bandwidth of the sense circuits. The calibration circuits are identical to the detection circuits other than the input to these circuits being directly supplied from an external source. The layout of Block 1 is depicted in Fig. 19.3. As previously noted, Block 1 includes interdigitated power and ground lines on all three device planes. The four layouts depict the three stacked device planes (Fig. 19.3A), the bottom device plane (Fig. 19.3B), the middle device plane (Fig. 19.3C), and the top device plane (Fig. 19.3D). The three different subcircuits are labeled in Fig. 19.3A. The RF pads shown in Fig. 19.3D are associated with the calibration circuits.

The layout of the logic block used to generate sequence patterns for the current mirrors is shown in Fig. 19.4. The components of the sequence generator are enclosed in boxes and labeled in Fig. 19.4B. The components included in the test circuit are the three ring oscillators (RO), buffers for the ring oscillators, four pseudorandom number generators (PRNG), and buffers for the number generators. The RO and PRNG buffers are identically sized except that the enable signal for the RO is connected to the external reset signal pin, whereas the PRNG enable signal is tied to the 1.5 volt supply. A schematic of each component and the corresponding transistor sizes are included in Figs. 19.5 and 19.6.

The layout and schematic of the current mirror and transmission gate switch used to modulate the current mirror are shown, respectively, in Figs. 19.7 and 19.8. The four figures depict the three stacked device planes (Fig. 19.7A), bottom device plane (Fig. 19.7B), middle device plane (Fig. 19.7C), and top device plane (Fig. 19.7D). The output from the PRNGs is the input to the switches of the current mirror, as shown in Fig. 19.8.

The layout of the power and ground noise detection circuits with the corresponding control logic is shown in Fig. 19.9. The four figures depict the circuits on each of the three device planes (Fig. 19.9A), bottom device plane (Fig. 19.9B), middle device plane (Fig. 19.9C), and top device plane (Fig. 19.9D). As shown in the figure, the control logic is only present on the second device plane. The power and ground detection circuits and the control logic are both shown in Fig. 19.9A.

A schematic of the logic that controls the RF output pads among the three device planes is shown in Fig. 19.10. The signal that controls the RF pads is provided for both the power and ground detection signals on each device plane and is rotated every 218 cycles. The control of the output pads has four phases; three phases rotate control amongst the three device planes, and a fourth phase connects the RF output pads for both the power and ground detection circuits to ground. The fourth phase provides a delineating time during measurement to distinguish data from each of the three device planes as the four phases are cycled.

The test circuit occupies an area of 2 mm × 2 mm. Each power distribution network is 530 μm × 500 μm. DC and RF pads surround the four test blocks. A block diagram of the DC and RF pads is shown in Fig. 19.11. The DC pads corresponding to the numbered pads shown in the figure are listed in Table 19.2. These DC pads provide the various bias voltages, reset signals, and power and ground signals. The RF pads surrounding the circuit blocks provide a pathway to probe and detect noise on the power and ground distribution networks. As shown in Fig. 19.11, there are three sets of two RF pads surrounding the blocks, one set for each of the three different 3-D power distribution networks. The RF pads internal to each block are also shown in Fig. 19.11. These RF pads are used to calibrate the source follower power and ground noise detection circuits.

There are two sets of five RF pads to calibrate the noise detection circuits, as shown in Fig. 19.11. Each set of five pads is allocated as a ground-signal-ground-signal-ground (GSGSG) pattern. Two sets of GSG RF pads are within the set of five pads with the middle ground pad shared between the two sets of pads. One set of GSG pads is dedicated to the sense circuit detecting noise on the power lines, and the other GSG is dedicated to the sense circuit detecting noise on the ground line. The set of five RF pads closest to the center of the block is used to pass a sinuisodial signal from an Agilent E8364A general purpose network analyzer (PNA) to the noise sensing circuits. The other set of five RF pads is used as an output from the sense circuits to the PNA. The input and output RF pads for calibrating both the power and ground line noise detection circuits are enclosed in boxes to emphasize that the middle pad is a shared ground pad between the two circuits, as shown in Fig. 19.11.

A microphotograph of the post wire bonded test circuit is shown in Fig. 19.12. Wirebonding is performed on a West Bond 7400 bonder with ultrasonic bonding. The aluminum wirebonds range in length from approximately 0.7 cm to 1 cm.

19.1.3 3-D Circuit Architecture

The three power networks utilize identical on-chip circuitry, with two of the topologies only differing by the total number of TSVs required to distribute power to the lower two device planes. With one network, 1,728 TSVs are placed along both the inner and outer interdigitated power/ground lines, as shown in Fig. 19.1A, while the second network includes 1,152 TSVs located along the outer peripheral interdigitated power/ground lines, as depicted in Fig. 19.1B. The third power network topology also includes 1,728 TSVs, but the interdigitated power network on the second stacked die is replaced with two metal planes, one plane for ground and one plane for power.

The basic logic blocks are illustrated in Fig. 19.13. The power supply noise generators sink different current from the power lines. These noise generators are placed on each tier of each power network topology. Voltage sense circuitry is included on each of the tiers of each test block to measure the noise on both the power and ground lines. The second tier of the power delivery network, illustrated in Fig. 19.1C, does not include noise sense circuitry or noise generation circuitry as this tier is dedicated to power and ground. The voltage range and average voltage of the sense circuitry on each tier for each test block are compared for the three topologies shown in Fig. 19.1.

A schematic of the on-chip circuitry on each tier of each power network is shown in Fig. 19.13. The circuit is designed to emulate a power load drawing current, generating noise within the power and ground networks. Two sets of circuits are present: noise generating circuits and noise detection circuits. The noise generating circuits include ten current mirrors per device plane (15 for the second device plane); 250 MHz, 500 MHz, and 1 GHz ring oscillators; and five-, six-, nine-, and ten-bit PRNGs. The clock pulses generated by the ring oscillators are buffered and fed into the PRNGs, which are again buffered before randomly driving the current mirrors as enable bits. Each current mirror requires eight enable bits, with each enable bit turning on one branch of the current mirror, and draws a maximum current of 4 mA (0.5 mA per branch). With ten current mirrors on each of the first and third device planes and 15 current mirrors on the second tier, the maximum current drawn by each power network is 140 mA at 1.5 volts, producing a maximum power density of 79 W/cm² in each 530 μm × 500 μm topology.

Separate noise detection circuits are included for evaluating power and ground noise. A schematic of the power and ground detection circuits is shown in Fig. 19.14. These single stage amplifier circuits utilize an array structured noise detection circuit, as suggested in [704]. Each device plane contains both power and ground noise detection circuits. An off-chip resistor, labeled R_bias in Fig. 19.14, biases the output node of the PMOS current mirror (with a PMOS threshold voltage of −0.56 volts) and ensures that the current mirror operates in the saturation region. The resistor is chosen to ensure that the maximum voltage at the output node of the current mirror does not exceed 400 mV, the voltage at which the current mirror enters the triode region. The measured current at the output of the current mirror ranges between 200 milliamperes and 300 milliamperes. Since R_bias is chosen as 100 Ω, the maximum voltage at the output node is 300 mV. In addition, the intrinsic impedance Z_o, shown in Fig. 19.14, is 50 Ω.

Two sets of ground-signal-ground (GSG) output pads source current from the final stage of the noise detection circuits of all three tiers, as shown in Fig. 19.13. One set of GSG output pads is dedicated to the three noise detection circuits that monitor the power network, while the other set of GSG pads supports the three noise detection circuits that monitor the ground network. Counter logic rotates the control of the output pads among the three device planes every 218 cycles (at a 250 MHz clock) for both the power and ground noise detection circuits. A second isolated power and ground network with a 2 μF board level decoupling capacitor ensures that the generated noise is not injected into the detection circuits.

19.1.4 3-D IC Fabrication Technology

The manufacturing process developed by MITLL for fully depleted silicon-on-insulator (FDSOI) 3-D circuits is described extensively in Section 16.1. This process has evolved into a more advanced technology node of 150 nm [670]. The operating voltage of the SOI transistors is 1.5 volts. The back end of the line remains the same, including one polysilicon layer and three metal layers interconnecting the devices on each wafer. A backside metal layer also exists on the upper two tiers, providing the starting and landing pads for the TSVs, and the I/O, power supply, and ground pads for the overall 3-D circuit. An enhanced feature of this process is the high density TSVs. The dimensions of the TSVs are 1.25 μm × 1.25 μm and 10 μm deep, much smaller than many existing 3-D technologies [150,155]. The step-by-step fabrication of the three tier stack is shown in Figs. 16.1 to 16.6. A microphotograph of the fabricated die is shown in Fig. 19.15.

19.3.1 Pre-Layout Design Considerations

Several considerations are accounted for in the design of the power distribution topologies. One issue is the placement of a sufficient number of TSVs to satisfy electromigration constraints between planes. The total number of TSVs required to satisfy a target current density of 1×10⁶ A/cm², a current load of 0.14 amperes, a TSV diameter of 1.25 μm, and a footprint of 530 μm by 500 μm (the footprint area of each power distribution network) verifies that the 576 and 864 TSVs per tier for, respectively, Block 2 and Blocks 1 and 3 far exceed the necessary twelve TSVs to satisfy any electromigration constraints. The number of TSVs to satisfy electromigration constraints is

${\mathrm{Area}}_{\mathrm{target}\mathrm{current}\mathrm{density}}=\frac{I_{\mathrm{load}}}{J_{\mathrm{electomigration}}},$ (19.1)

(19.1)

$\mathrm{Number}\mathrm{of}\text{TSVs}=\frac{{\mathrm{Area}}_{\mathrm{target}\mathrm{current}\mathrm{density}}}{{\mathrm{Area}}_{\mathrm{TSV}}}.$ (19.2)

(19.2)

The diameter of the TSV determines the “keep out zone” surrounding the TSV, an area where no devices can be fabricated. For the MIT Lincoln Laboratories 3-D technology, the keep out zone is approximately two times the diameter D. A square area with a width of 2×D and depth of 2×D is therefore used to determine the area penalty per TSV. An area of 1.36% and 2.04% of the 530 μm ×500 μm area is occupied by each power distribution topology on each device plane for, respectively, 576 and 864 TSVs. The area is the same for tiers 2 and 3, where all I/Os originate from tier 3. No area penalty on device plane 1 exists as no TSVs are necessary in this front-to-back bonded tier (the TSVs land on metal 3 on tier 1). For a keep out zone equivalent to 3×D, the area penalty is 3.06% and 4.58% for, respectively, 576 and 864 TSVs.

To determine the resonant frequency of each topology, a model of the 3-D power distribution networks includes the impedance of the cables, board, wirebonds, on-chip DC pads, TSVs, and the power distribution network on each device plane. The equivalent electrical parameters are listed in Table 19.5, and the capacitance of the 3-D power distribution topologies is listed in Table 19.6. The impedances listed in Table 19.5 for the cables, board, and wirebonds are divided into three equivalent π model sections to characterize the distributed nature of the lines, as shown in Fig. 19.21.

The interdigitated power and ground lines in metal 3 are 530 μm long, 15 μm wide, and exhibit a sheet resistance of 0.08 Ω per sheet, producing a 2.83 Ω resistance. Similarly, the metal 2 lines are 500 μm long and 15 μm wide with a sheet resistance of 0.12 Ω per sheet, producing a 4 Ω resistance. Each power and ground line is divided into eight equal RLC π model sections to represent the distributed nature of the on-chip metal lines. An inductance of 1 pH is included with each π model section. Three horizontal pairs (metal 3) of power and ground lines as well as three vertical pairs (metal 2) of power and ground lines are considered for each interdigitated power distribution network on each device plane. The RLC parameters for a single π section of the interdigitated topology also model the dedicated plane topology, but the connections between sections are modified to better characterize the power and ground planes, as illustrated in Fig. 19.21.

The resonant frequency for the three different power distribution networks is determined with and without board level decoupling capacitors and with and without an intentional on-chip load capacitance (separate from the intrinsic capacitance of the power distribution network). The resulting resonant frequency for the three power distribution topologies for the different capacitive configurations is listed in Table 19.7. The resonant frequencies reported in Table 19.7 consider the distributed inductance of the cables, board, wirebonds, and on-chip power distribution network. The on-chip inductance produces the highest resonant frequency, as reported in Table 19.7 for each block. The other three resonant frequencies, from the smallest to the largest, are dependent, respectively, on the cable, board, and wirebond inductances. The presence of a board level decoupling capacitor eliminates all but the highest resonant frequency, the resonance caused by the on-chip inductance.

19.3.2 Design Considerations Based on Experimental Results

Based on the experimental results, both increasing the number of TSVs by 50% and utilizing a dedicated power and ground plane lower the power noise. Although the noise is lower with both a greater number of TSVs and dedicated power planes (2% to 14.2% lower noise, as listed in Table 19.8), the power noise is limited by the small series resistance of the 3-D power network as compared with the larger series resistance of the cables and wirebonds, as described in Section 19.3.1.

Two issues in 3-D power distribution networks are considered based on the experimental results: (1) the benefits of the power and ground planes to justify the use of two metallization levels, and (2) the benefits and drawbacks of increased TSV density on area and noise. Addressing (1), the power planes provide an additional reduction of 0.2% to 5.5% in average noise as compared with the fully interdigitated topology. The reduction in average noise is primarily due to the increased capacitance of the power and ground networks, as indicated in Table 19.6. The average noise characteristics of the planes topology can be further improved by increasing the size of the power/ground planes or using multiple metal layers for both power and ground. The use of full planes to deliver current to the load does; however, require significant metal resources and therefore this issue must be considered. In addition, the power planes complicate the design of the signal interconnects, where holes are required in the power/ground planes to pass signals between device planes. For those applications where greater noise reduction is required, additional metallization and design complexity may be justified.

The choice of TSV density provides the greatest reduction in average noise, ranging from 2.7% to 14.0%, as listed in Table 19.8. The additional area penalty when increasing the number of TSVs by 50% from 576 to 864 is 0.68% (1.36% as compared with 2.04%), noting that the area penalty is also dependent on the keep out region, as described in Section 19.3.1. The increased area due to the higher TSV density is small as compared to the large reduction in average noise.