Keywords

Three-dimensional integration; vertical integration; 3-D ICs; on-chip interconnects; emerging technologies

1.1 Interconnect Issues in Integrated Systems

During the infancy of the semiconductor industry, the connections among the active devices within an integrated circuit presented an important obstacle to higher performance. The significant capacitance of the interconnects required large drivers and hindered the significant increase in performance available from the transistors. The deleterious effects of the interconnects, such as greater delay and noise coupling, had already been noticed from the earliest days of integrated circuits [15,16]. The invention of the integrated circuit temporarily alleviated some of these early interconnect related problems by placing the wires on-chip. The interconnect length was significantly reduced, decreasing the propagation delay and power consumption while enhancing yield. From a performance point of view, the delay of the transistors dominated the overall delay characteristics. Over the next three decades, the on-chip interconnects were not the major focus of the IC design process, as performance improvements reaped from scaling the devices were much greater than any degradation caused by the interconnects.

With continuous technology scaling, however, the delay, noise, and power of the interconnect grew in importance [17,18]. A variety of methodologies at the architectural, circuit, and material levels have been developed to address these interconnect performance objectives. At the material level, manufacturing innovations, such as the introduction of copper interconnects and low-k dielectric materials in the mid-1990s, helped to continue the improvements in performance gained from scaling [19–23]. This improvement is due to the lower resistivity of the copper as compared to aluminum previously used in the interconnects, and the lower dielectric permittivity of the novel insulator materials as compared to silicon dioxide (SiO₂).

Multilevel interconnect architectures [24,25], shielding [26], wire sizing [27,28], and repeater insertion [29] are only a handful of the many methods employed to cope with interconnect issues at the circuit level. Multilevel interconnect architectures, for example, support multiple levels of metal layers with different cross-sections [25], as illustrated in Fig. 1.3. Each group of layers typically consists of multiple metal layers routed in orthogonal directions with the same cross-section. The key concept of this structure is to utilize wires of decreasing resistance to connect those circuits located farther away. Therefore, the farther the distance, the thicker and wider the wire. The increase in the cross-sectional area of the wires is shown in Fig. 1.3. The thickness of the levels, however, is limited by the fabrication technology and related reliability and yield concerns.

Varying the width of the wires, also known as wire sizing, is an important means to manage the interconnect impedance characteristics. Wider wires lower the interconnect resistance, decreasing the attenuative behavior of the interconnect. Although wire sizing typically has an adverse effect on the power dissipated by the interconnect, proper sizing techniques can also decrease the power consumption [28,30].

Other practices do not modify the physical characteristics of the propagation medium. Rather, by introducing additional circuitry and wire resources, the performance and noise tolerance of an interconnect system can be enhanced. For instance, in a manner similar to the use of repeaters in telephone line systems, a properly designed interconnect system with buffers (also known as repeaters) amplifies the attenuated signals, recovering the originally transmitted signal that is propagated along a line. Repeater insertion converts the quadratic dependence of the delay on the interconnect length to a linear function of length [31], as shown in Fig. 1.4.

Shielding is an effective technique to reduce crosstalk among adjacent interconnects. Single- or double-sided shielding, as depicted in Fig. 1.5, is commonly utilized to improve signal integrity. Shield lines can also improve interconnect delay and power, particularly in bus architectures, in addition to mitigating noise. Careful tuning of the relative delay of the propagated signals [32] and signal encoding schemes [33] are other strategies to enhance signal integrity. Despite the benefits of these techniques, issues such as increased power consumption, greater routing congestion, reduction in wiring resources, and increased area arise.

At higher abstraction levels, pipelining the global interconnects and employing error correction mechanisms can partially improve the performance and fault tolerance of the wires. The related effects of these architectural techniques in terms of area and design complexity, however, have considerably increased. Other schemes, such as current mode signaling [34], wave pipelining [35], and low swing signaling [36], have been proposed as possible solutions to the impending interconnect bottleneck. These methods, however, have limited ability to reduce the length of the wire, which is the primary cause of the deleterious behavior of the interconnect.

Novel design paradigms are therefore required that do not impede the well established and historic improvements in performance in evolving generations of integrated circuits. Canonical interconnect structures that utilize internet-like packet switching for data transfer [37], optical interconnects [38], 3-D integration, and/or combinations of these technologies are possible solutions for enhancing communication among devices or functional blocks within an integrated circuit.

On-chip networks can greatly enhance the communication bandwidth among the individual functional blocks of an integrated system, since each of these blocks simultaneously utilizes the resources of the network. In addition, noise issues are easier to manage as the layered structure of the communication protocols utilized within on-chip networks provides error correction. The speed and power consumed by these networks, however, are eventually limited by the delay of the wires connecting the network links.

Alternatively, on-chip optical interconnects can greatly improve the speed and power characteristics of the interconnects within an integrated circuit, replacing the critical electrical nets with optical links [39,40]. On-chip optical interconnects, however, remain a technologically challenging issue. Indeed, integrating a modulator and detector onto the silicon within a standard CMOS process is a difficult task [38]. In addition, the detector and modulator need to exhibit sufficiently high performance to ensure the optical links significantly outperform the electrical interconnects [40]. Furthermore, an on-chip optical link consumes larger area as compared to a single electrical interconnect line. Multiplexing the optical signals using wavelength division multiplexing (WDM) can be exploited to limit the area consumed by the optical interconnect. On-chip WDM, however, imposes significant challenges.

Volumetric integration by exploiting the third dimension greatly improves the interconnect performance characteristics of modern integrated circuits while not degrading the interconnect bandwidth. In general, 3-D integration should not be seen as a competitive but rather synergistic technology with on-chip networks, optical interconnections, and other emerging technologies and architectures. The unique opportunities that 3-D integration offers to the circuit design process and the challenges that arise from the increasing complexity of these systems are discussed in the following section and throughout this book.

1.2 Three-Dimensional or Vertical Integration

Methods to vertically interconnect circuits were first proposed in 1962 during the earliest days of integrated circuits [41,42]. Although these vertical conductors intended to connect circuits fabricated on both surfaces of a wafer, these methods demonstrated that the benefits of vertical integration were appreciated by industry as early as the 1960s. Vertical integration was proposed and supported by some of the most prominent engineers and scientists at the time, such as William Shockley [43] and Richard Feynman [44]. Early enthusiasm on 3-D integration was however not followed by development and high volume production of 3-D circuits as the evolution of planar processes yielded the desired improvements in transistor density, speed, and power in integrated circuits with a commensurate decrease in manufacturing cost.

Consequently, for several decades, 3-D circuits were considered a niche with limited scientific and research importance. Efforts primarily focused on monolithic fabrication of vertical circuits, several examples of which were demonstrated in the early 1980s [45]. These structures included 3-D CMOS inverters, where the p-type metal oxide semiconductor (PMOS) and n-type metal oxide semiconductor (NMOS) transistors share the same gate, greatly reducing the total area of an inverter, as illustrated in Fig. 1.6. The term joint metal oxide semiconductor (JMOS) was used for these structures to describe the joint use of a single gate for both devices [46]. Prototypes with up to three layers of active devices were demonstrated in these early vertical monolithic systems [47]. Other examples of early uses of 3-D integration include infrared detectors, where the infrared detectors, manufactured in exotic materials such as mercadmium telluride or indium phosphate, were flipped and bonded to silicon-based detector readout circuits [48].

Since the 2000s, due to the increasing importance of the interconnect and the demand for greater functionality on a single substrate, the concept of vertical integration has been revived and has become a prominent topic of research and commercial development. Over the last 10 to 15 years, 3-D integration has evolved into a design paradigm manifested at many abstraction levels, such as the package, die, and wafer. Different manufacturing processes and interconnect schemes have been proposed for each of these abstraction levels [49]. These recent approaches highlight the advantages and disadvantages of introducing 3-D integration at these levels of the design abstraction, where 3-D technology as a systems integration platform yields significant improvements in transistor density, performance, heterogeneity, form factor, and cost. The salient features and important challenges of 3-D systems are briefly summarized in the following subsections.

1.2.1 Opportunities for Three-Dimensional Integration

The quintessence of 3-D integration is the drastic decrease in the length of the longest interconnects across an integrated circuit. To illustrate this situation, consider the simple structure shown in Fig. 1.7. A common metric to characterize the longest interconnect is to assume that the length of a long wire is twice the length of the die edge. Consequently, assuming a planar integrated circuit with an area A, the longest interconnect in a planar IC has a length $L_{\max ,2-D}=2\sqrt{A}$. The same circuitry on two bonded dies requires an area A/2 for each tier while the total area of the system remains the same. Hence, the length of the longest interconnect for a two tier 3-D IC is $L_{\max ,3-D}=2\sqrt{A/2}$. By increasing the number of dies within a 3-D IC to four, the area of each die is further reduced to A/4, and the longest interconnect would have a length of $L_{\max ,3-D}=2\sqrt{A/4}$. Consequently, the wirelength exhibits a reduction proportional to $\sqrt{n}$, where n is the number of dies or physical tiers integrated within a 3-D system. Although in this simplistic example the effect of the connections among circuits located on different dies is not considered, a priori accurate interconnect prediction models adapted for 3-D ICs also demonstrate a similar trend due to the reduction in wirelength [50]. This considerable decrease in the length of the interconnects is a promising solution for increasing speed while reducing the power dissipated by an IC.

Another characteristic of 3-D ICs of even greater importance than the decrease in the interconnect length is the ability of these systems to include disparate heterogeneous technologies. This defining feature of 3-D integration offers unique opportunities for highly heterogeneous and diverse multifunctional systems. A real-time image processing system where the image sensor on the topmost tier captures the light, the analog circuitry on the tier below manipulates and converts the analog signal to digital data, and the remaining two tiers of digital logic process the information from the upper tiers is a powerful example of a heterogeneous 3-D system-on-chip (SoC), exhibiting considerably improved performance as compared to a planar version of the same system [51,52]. Another example, where the topmost tier can include other types of sensors, such as seismic and acoustic, and an additional tier with wireless communications circuitry are vertically integrated, is illustrated in Fig. 1.8. Several application domains can greatly benefit from vertical integration including healthcare, healthy aging, military, security, and environmental monitoring to name just a few, as the proximity of the components due to the third dimension is suitable for both high performance and low power integrated systems.

Recent products demonstrate the many merits the third dimension can bring to computing. For example, the 3-D memories recently produced by Micron [53] and SK-Hynix [54] include four DRAM memory tiers which exhibit superior performance as compared to state-of-the-art planar double data rate memories [55]. The Virtex series of Xilinx field programable gate arrays (FPGAs) also utilize advanced stacking technologies [56]. This approach alleviates the issue of large die size, improving yield and cost.

1.3 Book Organization

A brief description of the challenges that 3-D integration faces is provided in the previous section. Several important problems are considered and a variety of techniques to address these problems are presented throughout this book. In the second chapter, different forms of vertically integrated systems are discussed. 3-D circuits at the package and die integration levels are reviewed. Some of these approaches, such as wire bonded stacked die and through silicon via (TSV)-based integration, have become commercially available. Although vertical integration of packaged or bare die offers substantial improvements as compared to planar multichip packaging solutions, the increasing number of I/Os hampers potential advancements in performance. This situation is primarily due to manufacturing limitations hindering the aggressive scaling of the off-chip interconnects to satisfy high I/O requirements.

Consequently, in the third chapter, emphasis is placed on those technologies that enable 3-D integration, where the interconnections between the noncoplanar circuits are achieved by short vertical vias. These interconnect schemes provide the greatest reduction in wirelength and therefore, the largest improvement in speed and power consumption. Specific fabrication processes that have been successfully developed for 3-D circuits are reviewed.

The predominant type of vertical interconnections is the through silicon vias. Due to the important role of this interconnect, Chapter 4, Electrical Properties of Through Silicon Vias, is dedicated to models of the electrical behavior of this structure. Models of differing complexity are discussed, and the appropriate model for the specific TSV process and 3-D system is described.

The effects of through silicon vias on the noise characteristics of the substrate of the tiers are presented in Chapter 5, Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs. The noise due to different types of substrates is evaluated and appropriate noise models for each type of substrate are offered. Mitigation techniques to suppress the noise from the TSVs are also discussed.

An alternative approach to TSVs to provide intertier communication is contactless interconnects. Existing efforts to enable contactless communication through inductive links are described in Chapter 6, Three-Dimensional ICs with Inductive Links. Models of crosstalk noise from inductive links to adjacent interconnects are presented. Furthermore, measures to avoid interference for specific types of interconnects are provided. A multiobjective algorithm for the design of inductive links to support intertier communication is also described.

A theoretical analysis of interconnections in 3-D ICs is offered in Chapter 7, Interconnect Prediction Models. This investigation is based on a priori interconnect prediction models. These stochastic models are used to estimate the distribution of the length of the on-chip interconnects. The remaining sections of this chapter apply the interconnect distribution model to demonstrate the opportunities and performance benefits of vertical integration.

Cost issues for vertical integration are discussed in Chapter 8, Cost Considerations for Three-Dimensional Integration. The diverse processing steps introduced in each of the manufacturing processes of TSVs have different cost requirements. Models that capture these cost implications are constructed in this chapter. In addition, a comparison between the manufacturing cost of 2.5-D and 3-D systems is provided. Several important aspects, such as the area of the active die and the prebond test coverage, are included in these models.

The following three chapters focus on issues related to the physical design of 3-D ICs. The complexity of the 3-D physical design process is discussed in Chapter 9, Physical Design Techniques for Three-Dimensional ICs. Several approaches for classical physical design issues, such as floorplanning, placement, and routing, from a 3-D perspective, are extensively reviewed. Certain fundamental methods and algorithms used in the physical design of planar circuits are also discussed to enhance the understanding of these techniques targeted to 3-D systems.

Beyond the reduction in wirelength that stems from 3-D integration, the delay of those interconnects connecting circuits located on different physical tiers of a 3-D system (i.e., the intertier interconnects) can be further improved by optimally placing the TSVs. Considering the highly heterogeneous nature of 3-D ICs including the nonuniform impedance characteristics of the interconnect structures, a methodology is described in Chapter 10, Timing Optimization for Two-Terminal Interconnects, to minimize the delay of the intertier interconnects. An interconnect line that includes only one TSV is initially described. The location of the TSV that minimizes the delay of a line is analytically determined. Any degradation in delay due to the nonoptimal placement of the 3-D vias is also discussed. To incorporate the presence of physical obstacles, such as logic cells and prerouted interconnects (for example, segments of the power and clock distribution networks), the discussion in this chapter proceeds with interconnects that include more than one TSV. An effective heuristic is described for placing TSVs to minimize the overall delay of a multi-tier interconnect.

By extending the heuristic for two-terminal interconnects, a near-optimal heuristic for multiterminal nets in 3-D ICs is described in Chapter 11, Timing Optimization for Multiterminal Interconnects. Necessary conditions for locating the TSVs are described. An algorithm that exhibits low computational complexity is also presented. The improvement in delay achieved by placing the TSVs for different via placement scenarios is discussed. For the special case where the delay of only one branch of a multiterminal net is minimized, a simpler optimization procedure is described. Based on this approach, a second algorithm is presented. Finally, the sensitivity of this methodology to the interconnect impedance characteristics is demonstrated, depicting a significant dependence of the delay on the interconnect.

In the next two chapters, techniques for 3-D ICs are extended to thermal design and management. Thermal models of different complexity and accuracy are presented in Chapter 12, Thermal Modeling and Analysis, including models for liquid cooling. Based on these thermal models and thermal analysis techniques, thermal management methodologies for 3-D systems are presented in Chapter 13, Thermal Management Strategies for Three-Dimensional ICs. Both physical and architecture level methods are discussed. These techniques either lower the overall power of the 3-D stack or carefully distribute the power densities across the tiers of a 3-D system to satisfy local temperature limitations. Moreover, design techniques that utilize additional interconnect resources to increase the thermal conductivity within a multi-tier system are also discussed.

A prototype circuit to enhance the understanding of thermal effects in 3-D structures is described in Chapter 14, Case Study: Thermal Coupling in 3-D Integrated Circuits. The test circuits are used to evaluate thermal coupling among the tiers of a three tier stack and between blocks located within the same physical tier. The effects of the TSVs on thermal coupling are also discussed.

The important issue of synchronization is the topic of Chapter 15, Synchronization in Three-Dimensional ICs. Clock tree synthesis techniques under diverse design objectives for multi-tier systems are described. As these techniques extend clock tree synthesis methods for planar circuits to 3-D structures, standard algorithms and methods used in the synthesis of planar clock trees are presented. Global clock distribution networks for 3-D circuits are also discussed in this chapter.

Following the treatment of clock tree synthesis algorithms, a prototype circuit investigating different global 3-D clock distribution networks is described in Chapter 16, Case Study: Clock Distribution Networks for Three-Dimensional ICs. A variety of clock networks, such as H-trees, rings, tree-like, and trunk-based, are explored in terms of clock skew and power consumption to determine an effective clock distribution network for 3-D ICs. A prototype test circuit composed of these networks has been designed and manufactured with the 3-D fabrication process developed at MIT Lincoln Laboratories (MITLL). The design and modeling process and related experimental results are also included in this chapter.

The effects of variations on the behavior of clock distribution networks are reviewed in Chapter 17, Variability Issues in Three-Dimensional ICs. The combined effects of die-to-die and within die variations are modeled for clock paths that span more than one tier. The distribution of skew for different clock networks is evaluated based on this model, and enhanced topologies that reduce skew variability are described. The skew model is extended to include power supply noise, and design guidelines for clock trees considering both power supply noise and process variations are presented.

The behavior of power supply noise depends strongly on the design of the power distribution network. The issues of power delivery and distribution for 3-D circuits are discussed in Chapter 18, Power Delivery for Three-Dimensional ICs. Integrating power delivery components into one tier of the 3-D stack allows smaller currents to propagate through the overall power distribution system, decreasing the power supply noise. The role of the vertical interconnects in distributing power and ground within a 3-D stack is discussed. Different approaches for distributing the decoupling capacitance throughout a multi-tier stack are treated coherently with the distribution of the TSVs to ensure that the power supply noise satisfies specified limitations. To quantify the effect of the TSVs on the switching noise, a 3-D test circuit is described that is used to evaluate the characteristics of several power distribution topologies, as described in Chapter 19, Case Study: 3-D Power Distribution Topologies and Models.

Exploiting the advantages of 3-D integration requires the development of novel circuit architectures. A 3-D version of a microprocessor-memory system is, therefore, discussed in Chapter 20, 3-D Circuit Architectures. Major improvements in throughput, power consumption, and cache miss rate are demonstrated. Communication centric architectures, such as a network-on-chip, are also discussed. On-chip networks are an important design paradigm to address the interconnect bottleneck, where information is communicated among circuits within packets in an internet-like fashion. The synergy between these two design paradigms, NoC and 3-D, can be exploited to significantly improve performance while decreasing the power consumed in communication limited systems.

Research on the design of 3-D ICs has only recently begun to produce commercially viable products. Many challenges remain unsolved and significant effort is required to provide effective solutions in the design of 3-D ICs. The major foci of this book are summarized in the last chapter, and general conclusions are offered regarding directions for research that will contribute to the maturation of this exciting solution in next generation multifunctional heterogeneous systems.