Conclusions
With FET channel lengths below 10 nm, modern silicon integrated systems support gigascale densities composed of billions of transistors. Modern on-chip systems often include several heterogeneous processing cores within a microprocessor system or a mixture of different silicon technologies, such as analog, digital, and RF, in a mixed-signal SoC. A fundamental requirement for this system-on-chip (SoC) paradigm is efficient and reliable communication among the many different system components.
High speed, low power, and low noise intercomponent communication is fundamentally limited by the increasing impedance characteristics and length of the interconnect. Three-dimensional (3-D) integration is an effective solution to the deleterious effects of these long horizontal interconnects. In vertically integrated systems, the long interconnects spanning several millimeters are replaced by orders of magnitude shorter vertical wires. This inherent reduction in wirelength provides opportunities for increased speed, enhanced noise margins, and lower power.
3-D integrated systems can also comprise a variety of different silicon technologies, such as digital, analog, RF CMOS, and SOI circuits, non-silicon semiconductor technologies, such as InP, SiGe, HgCadTd, and GaAs, nonvolatile technologies, such as Spin transfer torque magnetic tunnel junction (STT-MTJ), magnetic and resistive RAMs, and photonic integrated circuits, making 3-D systems highly suitable for a broad spectrum of applications. This salient characteristic of heterogeneous integration has greatly increased interest in 3-D systems as compared to other, more incremental solutions that simply scale CMOS technologies.
Within the context of an electronic product, circuit level enhancements can profoundly affect fundamental system requirements, such as form factor, portability, and computing power. Since the application space for these systems is broad, several different forms of 3-D technologies have been developed while other 3-D technologies are currently under development. These approaches range from monolithic 3-D circuits to polylithic and heterogeneous multi-tier systems. Interposer based approaches complete the spectrum of non-planar integrated systems with galvanic connections between dies. The fundamental element of a 3-D silicon system can be a single transistor, a functional block, a bare die, or a packaged circuit. The structural granularity of the system, in turn, determines the form of vertical interconnection which links the elements of a 3-D circuit in the vertical direction. The cost of manufacturing is directly related to the processing capabilities offered by these technologies. Fabrication processes that utilize TSVs for vertical interconnects are an economic form of vertical integration, while exhibiting considerable improvement in system performance.
An alternative to TSV-based 3-D systems is the contactless integration of physical tiers utilizing capacitive or inductive coupling. Between these two schemes, inductive coupling can support higher communication distances and, therefore, greater integration densities. Although the silicon area required by the on-chip inductors within the links is significant, interest exists for this type of 3-D integration in niche applications where the manufacturing complexity of the TSV cannot be justified. As discussed in this book, the performance of the inductive links can be comparable to the TSVs, particularly at large TSV diameters. The capabilities of contactless 3-D circuits have not yet been sufficiently explored and design methodologies are far from complete and systematic.
A major focus of this book is that effective physical design methodologies and algorithms for 3-D circuits have been developed, emphasizing the significant role of the TSVs. In the 3-D design process, the through silicon vias are treated as a means to improve signaling among the physical tiers within a 3-D stack. The TSVs in a 3-D circuit provide synchronization, power delivery, and signaling among the tiers and—in contrast to mainstream two-dimensional (2-D) circuits—thermal cooling. The primary challenges and novel solutions for satisfying these objectives are discussed throughout the book.
The electrical characteristics of the TSVs affect all of these objectives. Consequently, the impedance characteristics of the TSV structures are considered in design algorithms and techniques to enhance the speed, power, and area of 3-D systems. These methods increase the benefits of the shorter interconnect length. The effectiveness of physical design techniques is considerably improved by exploiting the electrical behavior of these vias. Interestingly, not all TSV technologies yield improvements in speed, power, and area. For those circuits where the speed is primarily determined by the logic gates, the gains from 3-D integration are constrained. Furthermore, an electronic storm is produced within this multi-tier system. The TSVs can produce significant noise coupling with adjacent devices in specific types of substrates. As 3-D integration targets highly heterogeneous systems, coupling between a TSV and different types of substrates is modeled and explored. Low resistivity substrates, for example, can produce high coupling, which needs to be considered during the design process.
To assess the gains and limitations of TSVs in integrated systems, systematic approaches are provided for inserting and distributing the vertical interconnects to improve the overall thermal conductivity of a 3-D stack. By including the thermal objective in 3-D physical design algorithms and techniques, significant thermal gradients and high temperatures, which can degrade the reliability and performance of a 3-D circuit, are significantly reduced. Due to the high power densities, the thermal objective is an integral element of the physical design process for 3-D integrated systems.
Thus, thermal issues are tackled during every step of the design process, including floorplanning, placement, and routing, as described in several chapters of this book. Thermal management strategies applied during runtime are also beneficial. These methods exploit different techniques for lowering the power dissipated by a system to better manage the local temperatures and distribute the heat within a 3-D stack. Another method to address thermal issues is to cool between the tiers of a 3-D stack. This approach is efficient but is currently unavailable in production systems as the cooling channels in the thinned substrate within the tiers significantly complicate the manufacturing process.
The lack of advanced packaging technologies has increased the role of on-chip solutions in removing heat from multi-tier systems. Design methodologies for circuit/package thermal codesign offer superior solutions caused by the high temperatures within 3-D circuits. Consequently, although difficulties exist in applying some of these approaches, the material presented in this book offers broad coverage of different thermal management techniques to reinforce research into this paramount issue for 3-D systems.
The role of TSVs in enhancing power delivery and distribution is also described. An interesting outcome of several studies is that those 3-D technologies that support more than one TSV diameter have a distinct advantage in addressing power integrity issues in multi-tier systems. Each use of TSVs, including for signaling, synchronization, power delivery, and heat transfer, is evaluated in several case studies of three fabricated 3-D circuits. Different methods to efficiently distribute the clock signal in the gigahertz regime are explored, both temporally and within the three spatial dimensions. In addition, several topologies to distribute power and ground are evaluated. In the third test circuit, the important issue of intra and intertier thermal coupling is experimentally evaluated and validated. In a nutshell, enhanced intertier signaling is a prerequisite for high performance, high bandwidth 3-D computing.
A topic in 3-D circuits that has, somewhat surprisingly, received limited interest to date is process variability, which has been extensively explored in 2-D circuits. The diverse technologies comprising a 3-D system and the disparate behavior of the circuits within these tiers require statistical and probabilistic models to characterize process, environmental, and power noise variations, while methods that exploit the broader sources of variability to mitigate variations across a 3-D system are currently nascent and require attention. These topics are discussed in great detail in this book.
High performance applications typically include communications limited architectures, such as a processor-memory system. Communication fabrics, such as on-chip networks, and FPGAs also greatly benefit from the short vertical interconnects. Different architectural configurations are explored in this book, demonstrating the many possible power and latency tradeoffs that can result from exploiting the third dimension. Appropriate latency and power models supporting this discussion are also presented.
The primary achievement of this book is the thorough and integrated exploration of the multiple aspects of 3-D integration, ranging from manufacturing to physical design and algorithms, to thermal analysis and management, to system level architectures. This comprehensive approach targets the design and analysis of 3-D integration, primarily from a circuits perspective. With this point of view, the primary objective of this book is to provide physical and electrical intuition into the most sensitive issues regarding the vertical interconnect, which is intertwined within each step of the 3-D design process.
As a final concluding remark, consider that although early 3-D systems have already appeared in the marketplace, the commercial growth of 3-D integration will be greatly enhanced once an appropriate business model and supply chain are in place. Unfortunately, the major stakeholders have not yet managed to present a successful paradigm for the design and manufacture of 3-D systems; rather, an ad hoc mix-and-match approach is applied. This wait for an effective business model has greatly slowed the evolution of this fascinating and promising systems integration platform.
Looking beyond these unresolved non-technical issues, the material described in this book is intended to shed light on those areas related to the design of 3-D integrated systems. The primary objective of the entire 3-D ecosystem is to develop large scale multi-functional, multi-tier heterogeneous systems while continuing the microelectronics revolution.