3.1.1 Laser Crystallization

Following the work in [97], several techniques using beam recrystallization were developed to successfully fabricate 3-D ICs. In these techniques, the first device layer is fabricated with a traditional CMOS or SOI process. Note that only a device layer is fabricated on the first tier. The interconnect layers are not fabricated at this initial stage. Fabrication of the transistors on the upper layers satisfies a twofold objective. The devices on the upper layers should exhibit satisfactory transistor electrical characteristics, such as field mobility, threshold voltages, and leakage currents (i.e., I_on/I_off ratio) and the characteristics of the transistors on the lower layer should not be degraded by the high temperatures incurred during the manufacturing process.

The first layer of devices is formed with a common MOS process. Depending upon the fabrication process, this layer can include both PMOS and NMOS devices [98] or only one of the two devices [99]. In the latter case, the complementary type of devices is fabricated exclusively on the upper layer(s). Alternatively, the upper layer(s) can include only SOI devices [100].

Prior to the development of the upper device layer, an insulating layer of SiO₂ is deposited [98]. To protect the devices of the first layer from the elevated temperatures during the recrystallization phase, a thick layer with an approximate thickness of 1 μm is deposited on top of the insulating SiO₂ layer. This layer is a standard feature of the recrystallization technique and is composed of various materials, such as polysilicon [98], phosphosilicate glass [99], and silicon nitride (Si₃N₄).

To grow the devices on the upper layers, polysilicon islands or thin polysilicon films are crystallized to single grains by an Argon laser [101]. The resulting 3-D IC is shown in Fig. 3.2, where the different layers are also indicated. The temperature during the recrystallization phase can be as high as 950°C [100], while device formation with a lower temperature of approximately 600°C has been demonstrated [98].

Since the temperature used in these manufacturing steps approaches or exceeds the melting point of the metals commonly used for interconnects, doped semiconductor materials are used to interconnect the devices located on different tiers. These materials can include n⁺ doped polysilicon [98] or phosphorous-based polysilicon [100]. Alternatively, the interconnect layers can be fabricated after the upper layer devices are formed, where the contact holes are produced through reactive ion etching (RIE). The intertier interconnects are manufactured by sputtering aluminum [99]. A cross-section of a 3-D IC fabricated with aluminum interconnects is shown in Fig. 3.3.

The major drawbacks of the laser recrystallization technique are the quality of the grown devices on the upper layers and the effect of the high temperatures on the electrical characteristics of the devices on the lowest layer. Comparison of the device characteristics for the two layers shows that the threshold voltage is sufficiently controlled, while the mobility of the devices on the upper layer is slightly worse than the transistors on the bottom layer [99]. Since the mobility of the devices on the upper layers is degraded, the PMOS devices which exhibit lower mobility are fabricated on the lower layer [46]. In addition, simple shift registers [98] and ring oscillators [99] have been shown to operate correctly, demonstrating that the devices on the first layer remain stable despite the high temperature steps utilized to manufacture the devices on the upper layer.

More advanced recrystallization techniques can provide up to three device layers, where the lowest layer is a CMOS layer while the other two layers are composed of SOI devices [100]. Since there are three device layers in this structure, two isolation layers are required to protect the devices on the lower layers. Measurements from sample structures demonstrate that the threshold voltage of the devices is well controlled with low subthreshold currents for the devices on the upper layers [100]. The mobility of these transistors can, however, vary significantly.

Alternatively, E-beam has been used to recrystallize the polysilicon to form the devices on the upper layers [101]. A three-layer prototype 3-D IC performing simple image processing has been demonstrated [102]. On the topmost layer, consisting of amorphous-Si (a-Si), the light is captured and converted to a digital signal and stored on the bottom layer composed of the bulk-Si transistors. The intermediate layer, which includes the SOI transistors, compares the digital data from one pixel to the digital data in adjacent pixels to produce an edge detection operation. Measurements show a narrow distribution of the threshold voltage of the devices on the SOI layer with satisfactory I–V device characteristics. Although correct operation of the circuitry is confirmed, demonstrating the capabilities of a monolithic 3-D circuit, 34 mask steps are required, including five layers of polysilicon and two layers of aluminum interconnects. Although several recrystallization approaches have been developed, none of these techniques has demonstrated the capability of manufacturing complex, high performance 3-D circuits, primarily due to the inferior quality of the devices on the upper layers of the 3-D stack.

3.1.2 Seed Crystallization

Another technique to fabricate multiple device layers on bulk-Si is crystallizing a-Si into polysilicon grains. Thin film transistors (TFTs) are formed on these grains. The seed utilized for recrystallization can be a metal, such as nickel (Ni), or another semiconductor, such as germanium (Ge).

The basic processing steps of this technique are illustrated in Fig. 3.4. A film of amorphous silicon is deposited with low pressure chemical vapor deposition. A second film of low temperature oxide (LTO), SiO₂, is deposited and patterned to form windows at the drain or both drain and source terminals of the devices for Ge or Ni seeding. Consequently, two kinds of TFTs are produced. One type is seeded only at one terminal while the second type is seeded at both terminals. The deposition of the LTO SiO₂, patterning, and the deposition of the seed are additional steps as compared to a conventional process for TFTs. Thermal annealing is necessary to completely crystallize the channel films. Finally, the LTO and seeds are etched, permitting the TFTs to be fabricated with a standard process. A thermal layer of SiO₂ is used as the gate dielectric, and boron and phosphorous doping is used for the junctions. The gate electrode is formed by in situ doped polysilicon and the interconnections are fabricated by modified interconnect and plug technologies from conventional 2-D circuits. The peak temperature of the process is 900°C.

Certain factors can degrade the quality of the fabricated TFTs, such as the size of the grains and the presence of defects within the channel region. Controlling the size and distribution of the grains contributes significantly to the quality of the manufactured devices. Comparisons among unseeded devices, produced by crystallizing a-Si, single seeded, and dual seeded TFTs, have shown that seeded devices exhibit enhanced device characteristics, such as higher field effect mobility and lower leakage currents. The greatest improvement in these characteristics is achieved by dual seeded TFTs. However, as compared to single seeded transistors, the improvements of dual seeded transistors diminish with device size. Consequently, for small devices where the grain size of a single seeded device is approximately the entire channel region, the performance of those TFTs is close to double seeded TFTs as grain boundaries are unlikely to appear within the channel. Grain sizes over 80 μm have been fabricated [104]. High performance TFTs formed by lateral crystallization on the upper layers exhibit low leakage currents and high mobility as compared to the SOI devices on the first layer, while significantly reducing the area of the logic gates [103,104].

Selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) have also been combined to fabricate multiple layers of SOI devices [105,106]. The various steps of these techniques are summarized in Fig. 3.5. The first device layer is formed on a thick layer of SiO₂. The oxide is patterned with photolithography and etching procedures to define the SOI islands (Fig. 3.5A). A thinner SiO₂ layer, acting as the insulator, is deposited (Fig. 3.5B). With photolithography, a window for SEG is opened within the silicon island patterns (Fig. 3.5C). Using SEG and ELO, the patterns are filled by vertical and lateral growth of silicon within the SEG window (Fig. 3.5D). The redundant silicon is etched with chemical mechanical planarization (CMP) (Fig. 3.5E). A second layer of devices is fabricated with the same process, unlike oxide deposition, which is achieved with plasma enhanced chemical vapor deposition. The transistors are fabricated on islands using conventional SOI techniques (see Figs. 3.5F to H). The smaller island has an area of 150 nm×150 nm, enabling a high degree of integration on a single die [105]. The photolithography and etching steps limit the dimensions of the SOI islands. Satisfactory device characteristics have been reported with stacking faults only appearing on the first device layer [105].

3.1.3 Double-Gate Metal Oxide Semiconductor Field Effect Transistors for Stacked Three-Dimensional ICs

Similar to 2-D circuits where standard cell libraries include a compact physical layout of individual logic gates or more complex logic circuits, standard cell libraries for 3-D circuits include “volumetric” logic cells with minimum volume and a smaller load as compared to 2-D cells. Fabrication techniques that use local clusters of devices to form standard 3-D cells have been developed [107] based on double-gate MOSFETS [108,109]. The major fabrication stages for a 3-D inverter cell are illustrated in Fig. 3.6, where a decrease of 45% in the total capacitance is achieved. Similar improvements are demonstrated for more complex circuits, such as a 128-bit adder, where a 42% area reduction is observed [107].

An SOI wafer is used as the first layer of the 3-D IC. The top silicon layer is thinned by thermal oxidation and oxide etching. A thin layer of oxide and a layer of nitride are deposited as shown in Fig. 3.6A. The wafer is patterned and shallow trench etching is used to define the active area (Fig. 3.6B). A layer of LTO is deposited to fill the trench, which is planarized with CMP, where the nitride behaves as the stop layer (Fig. 3.6C). The nitride film is removed and LTO is utilized as a dummy gate. The LTO, silicon, and oxide are patterned and etched, followed by depositing a nitride film (Fig. 3.6D). The drain and source regions for the first device layer are created with an As⁺ implantation. As depicted in Fig. 3.6E, a via is opened at the drain side to connect the terminals of the NMOS and PMOS transistors located on the second layer. The contact is implemented as a tunneling ohmic contact. A polysilicon layer is deposited and planarized by CMP utilizing the nitride film as the stop layer. The nitride film is etched to expose the silicon for the channel region (Fig. 3.6F). Boron doping is used to fabricate the source and drain regions of the PMOS transistor on the top layer (Fig. 3.6G). The active area for the devices is defined by removing the LTO and the buried oxide (Fig. 3.6H). Before forming the gates for the stacked transistors, the gate oxide is grown by thermal oxidation, as shown in Fig. 3.6I. Finally, in situ deposition of doped polysilicon forms the gate electrodes. Note that for the gate below the channel region of the PMOS transistor (see Fig. 3.6J), a slow deposition rate is required to completely fill this region.

3.1.4 Molecular Bonding

Monolithic 3-D circuits utilizing molecular bonding demonstrate several advantages over the previously described approaches. An important trait of this technique is that an entire wafer can be transferred onto the bottom layer at low temperature (200°C), where the transistors for the upper layers are formed. There are several advantages associated with this approach, for example, the quality of the substrate, which is not limited by defects as in the case of seed crystallization and recrystallization-based methods. Furthermore, the integration density is the same as the bottommost layer, whereas the seed windows and the polycrystalline nature of the substrate in other approaches limit this density. Additional benefits of a high quality monocrystalline substrate are better bonding and improved control of the substrate thickness [110].

Although this technique includes the transfer of the substrate onto another wafer, resembling the case of 3-D integration with TSVs, the devices on the upper layers are not yet fabricated, which greatly differentiates the manufacturing process. The manufacturing process includes a number of sequential steps, which commences with the fabrication of the devices in the bottom layer with standard fully depleted silicon on insulator (FDSOI) processes. These steps are summarized in Fig. 3.7. A thin layer of dielectric is deposited and planarized before the transfer of the substrate. The thickness of the dielectric layer is an important factor, which can be adapted to exploit the coupling between the stacked devices [111], where thicknesses ranging from 60 nm to 110 nm have been tested. In the next step, molecular bonding is used to transfer an SOI substrate (see Fig. 3.7B) (other substrates can also be transferred, which makes this technology appealing).

Having a high quality substrate, the devices are formed where the orientation of these devices can be controlled to achieve specific transistor characteristics [110,111]. Furthermore, non-Si devices, such as Ge p-MOSFETs [112] and devices other than bulk MOSFETs, can be grown, including FinFETs and trigate transistors [113,114] (see Fig. 3.7C). One critical step for the performance of the transistors in the upper layers is activation of the dopants, which for the bottom layer is achieved with high temperatures (e.g., >1000°C) [96]. These temperatures, however, are prohibitive for thermal activation of the dopants in the upper layer(s). Consequently, solid phase epitaxy regrowth is applied at 600°C irrespective of the type (n or p) of the transistor. The last major step of the process includes the interlayer interconnects, which are similar to standard contacts used in the BEOL of planar circuits (see Fig. 3.7D). Case studies with tungsten contact plugs have been demonstrated [96]. The similarity of an interlayer contact with a typical contact between two metal layers is illustrated in Fig. 3.8.

Since different types of devices can be manufactured, several applications can be supported by monolithic 3-D circuits. This situation is also due to monolithic 3-D technology able to support integration at both the device and cell level. Thus, the integration of different device types leads to heterogeneous applications, while integration at the cell level leads to considerable gains in performance and area for the logic and memory circuits. The disparate applications enabled by this technology are listed in Table 3.1.

Integrating monolithic circuits at the device level allows for adapting the behavior of the devices in several ways. For example, the choice of substrate, the material used for the channel, the orientation of the crystal, and the strain can each be used to produce devices that are best adapted for the target application [96]. An example of this approach is 4T SRAM (loadless) cells, where the transistors are vertically aligned to ensure that the stored bit of information back biases the access transistors (grown in the upper layer), shifting the threshold voltage of these transistors [115]. The transistors should be carefully aligned to modulate the threshold voltage of the devices in the upper layer based on the applied gate voltage to the devices in the lower layer. Furthermore, the thickness of the interlayer dielectric (ILD) separating the two layers of transistors should be appropriately adapted. Simulations have shown that if this thickness is 300 nm, no noticeable change in the threshold voltage is observed due to the gate voltage of the transistors in the bottom layer. If this thickness decreases to 10 nm, the shift in voltage threshold can be as high as 130 mV [115].

The benefit of this approach is improved stability of the memory cell. The read noise and static noise margins are, respectively, 320 and 150 mV [115]. Additionally, the noise margins are achieved without any modification to the size of the devices. Both the transistor width and length are, therefore, the same for all four of the transistors in the SRAM cell.

Although transistor level integration is beneficial in this specific example, significant and higher gains are demonstrated when integration occurs at the cell level. In this approach, cells are placed on top of other cells, yielding more compact circuits. To compare the gains produced from each integration technique, the area savings and performance improvements are evaluated for some basic logic gates and circuits. A flip flop in these two styles exhibits a density gain of 28.5% and 38% for integrating, respectively, nFETs on top of pFETs and CMOS gate-on-gate integration. For more complex circuits, such as a 16-bit multiply accumulate unit, the savings are, respectively, 42% and 52% for the two integration styles [112]. Alternatively, if the area is maintained constant, increased performance can be achieved. Thus, for a NAND gate with a driving strength of 8×, the gain in current is 20% and 100%, respectively, when integrating at the transistor and cell level.

These examples demonstrate that integration at the cell level offers considerable improvements. Application of this integration style has also been applied to FPGA fabrics, where the fabric is partitioned to ensure that the memory cells are placed on the bottom layer whereas the logic cells are placed on the upper layer. The savings in area and energy delay product are, respectively, 55% and 47%.

Although monolithic integration exhibits appealing characteristics, integrating several layers of devices with a single stack of interconnect layers (i.e., BEOL) is a challenging task. Alternatively, fabricating a 3-D system with vertically bonded ICs or wafers that are individually processed can reduce the total manufacturing time without sacrificing the quality of the devices on the upper tiers of the stack. Consequently, parallel or polylithic integration, through where circuits from individual wafers are stacked to form multi-tier systems, is discussed in the following sections.

3.2.1 Wafer Level Integration

Although none of the developed wafer level techniques has been standardized, nearly all of these methods share similar fabrication stages, which are illustrated in Fig. 3.9. The order of these stages, however, may not be the same or some stages may not be used, depending upon the TSV fabrication scheme and the bonding approach and mechanism.

Initially, CMOS or SOI wafers are separately processed to produce the physical tiers of the 3-D stack, while a certain amount of active area is reserved for the TSVs. The TSVs are etched and filled with metal, such as tungsten (W) or copper (Cu), or even low resistance polysilicon. To decrease the length of the TSVs, the wafers are attached to an auxiliary wafer, usually called a “handle” or “carrier” wafer, and thinned to a different thickness depending upon the target aspect ratio for the TSVs. After the TSVs are revealed, backside metallization provides electrical connections between the tiers. The alignment and bonding phase follows, as shown in Fig. 3.9D. Finally, the handle wafer is removed from the thinned wafer and, if required, the appropriate side of the wafer is processed and attached to another tier. A broad gamut of materials and methods exist for each of these phases, some of which are listed in Table 3.2.

Several of the proposed techniques for 3-D ICs support the integration of both CMOS and SOI circuits [120,122]. From a fabrication point of view, however, SOI facilitates the wafer thinning step as the buried oxide (BOX) serves as a natural etching stop layer. This situation is due to the high selectivity of the etching solutions. Solutions with a Si to SiO₂ selectivity of 300:1 are possible [116]. In addition, SOI technology can yield particularly thin wafers or tiers (<10 μm), resulting in short TSVs. Alternatively, SOI circuits inherently suffer from poor thermal properties due to the low thermal conductivity of the oxide [124].

The formation of the TSVs is an important issue in the design of high performance 3-D ICs. This fabrication stage includes opening deep trenches through the silicon substrate (and potentially the inter layer dielectric and metal layers), passivation of the trench sidewalls from the conductive substrate (for CMOS circuits), and (partially or fully) filling the opening with a conductive material to electrically connect the tiers of the 3-D system. Due to the importance of this fabrication stage a more complete discussion of TSVs follows in Section 3.4.

Before stacking the tier, the wafers are thinned to decrease the overall height of the 3-D system and, therefore, the length of the TSVs. The diameter and length of the TSVs are interdependent and are typically characterized by the TSV aspect ratio (length/diameter). Processes that produce TSVs with aspect ratios over 20:1 [125] have been demonstrated. Typical ratios range from six to ten [126,127], where six is a common ratio. Furthermore, the minimum diameter of the TSVs depends upon the preferred integration granularity in addition to the capabilities of the manufacturing processes. In general, the finer the level of integration, the more aggressive the TSV aspect ratio or wafer thinning process.

A reduced wafer thickness, however, cannot sustain the mechanical stresses incurred during the handling and bonding phases of the 3-D process. A handle wafer is therefore attached to the original wafer prior to the thinning step. The handle wafer should possess several properties including the following:

Thinning can proceed with a variety of methods, such as grinding and etching or both, accompanied by polishing. Various combinations can also be applied, such as a silicon wet etch followed by CMP, mechanical grinding with CMP, mechanical grinding succeeded by a spin etch, and dry chemical etching [119]. Several requirements relating to the wafer thinning step also exist, including [128]:

Accurate alignment of the thinned wafers is a challenging task. A variety of techniques are utilized to align the wafer based on the precise registration of the alignment marks. These mechanisms include infrared alignment, through wafer via holes, transparent substrates, wafer backside alignment, and inter-substrate alignment [129]. Typical alignment precisions range from 1 to 5 μm (see Table 3.2). Submicrometer accuracies have also been reported [123,129].

Once the wafers are aligned, the bonding step follows. Disparate methods to perform this step are listed in Table 3.3. If die-to-wafer or die-to-die bonding is preferred to avoid the integration of faulty dies, each wafer is diced prior to bonding and the dies are successively bonded. An increase in the turnaround time, however, is inevitable with this approach as discussed in the following subsection.

3.2.2 Die-to-Die Integration

With die-to-die 3-D stacking, the wafer is diced and each die is separately tested. The known good dies are placed on supporting wafers and these carrier wafers are bonded, producing a two-tier system. This approach has a better manufacturing throughput than individual die-to-die bonding but a lower throughput than direct wafer level bonding where some of the dies can be defective.

Another approach to allow multiple die-to-die stacking rather than only two-tier systems is the cavity alignment method where multiple tiers are assembled, improving manufacturing throughput. The method utilizes a silicon substrate with metal layers, which provides mechanical support for the entire stack. A template that forms the cavity is deposited with the use of an optical microscope to obtain precise placement of the template. The template is composed of a metal plate with a thickness of 0.5 mm and exhibits a small coefficient of thermal expansion (CTE). Upon alignment, the template is bonded to the substrate with a removable adhesive [130]. The tiers of the system are placed sequentially into the cavity where bonding is achieved by compression. A final bonding step is applied to the entire system based on thermal compression, where a typical applied temperature is 250°C and the exerted force is 10 N. The process is completed by removing the template. The stages of the process are illustrated in Fig. 3.10. The alignment accuracy of this method is within ±1 μm.

Other die-to-die integration techniques that can produce up to four-tier systems have also been demonstrated, which, although based on conventional bonding through thermal compression, utilize scrubbing and heating to enhance bonding strength [131]. In this process, the first die is of regular thickness, while the upper tiers are thinned to 50 μm. Scrubbing improves the TTV of the bump height of the TSV, and the surface flatness of the copper bumps. With the introduction of a scrubbing force the bonding temperature can be lowered to less than 200°C, while the pressure is also decreased to less than 100 MPa. Key parameters of this technique are the scrubbing time and force [131]. Tests on daisy chain connections of TSVs bonded with this approach demonstrate a resistance of approximately 170 mΩ, close to the theoretically expected resistance of 113 mΩ [131].

Alternatively, wafer scale bonding exhibits the highest manufacturing throughput. Wafer level bonding can be applied with a high initial yield for each tier within a 3-D system (the overall yield can be affected by later processing steps, e.g., bonding). Thus, wafer scale stacking results in an acceptable overall yield for the 3-D system, assuming the yield for each tier is high.

3.2.3 Bonding of Three-Dimensional ICs

In addition to the level of bonding, different bonding styles also exist. For example, back-to-face tier bonding is illustrated in Fig. 3.9D. In addition, face-to-face bonding can be utilized to efficiently bond two tiers. An advantage of face-to-face bonding is that if only two tiers are bonded, the TSVs can be removed, as shown by the process illustrated in Fig. 3.11. In this process, the “mother” circuit is considerably larger and provides the interconnections to the package. For this reason, two different types of bumps are utilized. Microbumps with a fine pitch (25 to 35 μm) connect the two tiers, while Cu pillars at a 185 μm pitch interconnect the two tier system to the package. Adding, however, a third tier to a two tier stack is not straightforward since TSVs are required. In this case, the third (or other) tier is added in a back-to-face manner, which requires TSVs. Back-to-back bonding is also possible, resulting, however, in longer and, therefore, lower performance TSVs.

Bonding can be achieved with adhesive materials, metal-to-metal bonds, oxide fusion, and eutectic alloys deposited among the tiers of a 3-D system [117]. A list of the traits and challenges of these disparate bonding technologies are reported in Table 3.3. Epoxies and polymers possess good adhesive properties and are widely used. Some of these polymers are listed in Table 3.4. Metal-to-metal bonding requires the growth of (square) bumps on both candidate tiers for stacking and can consist of, for example, Cu, Cu/Ta, In/Au, and Cu/Sn. A portion of these bumps is deposited at the edge of the TSVs, providing enhanced electrical connection between the tiers. In the case where metals with different melting points are utilized (for example, Cu and Sn), the metal with the lower melting point is placed between the Cu pillars with the higher melting point [130]. An inter-metallic compound (IMC) is formed by applying thermal compression to ensure that the metal with the lower melting point diffuses into the metal with a higher melting point.

An epoxy filler can also be used to reinforce the bonding structure. An issue that arises in this case, however, is that the resin can result in bonding failure due to differences in the height of the metal bumps. To avoid these failures, pyramid or conic shaped bumps have been proposed [133]. The compressive bonding force causes the bumps to spread, excluding the resin from the bond region, as illustrated in Fig. 3.12. Eutectic solders are also used for tier bonding, where tin is plated on the tier surface followed by heating and compression [120]. Additionally, the temperature profile depends upon the material used for the interface and typically ranges from 200 to 400°C to not degrade the copper interconnections. Other highly refractory metals, such as tungsten or doped polysilicon, can be used if higher temperatures are necessary, increasing, however, the resistance of the TSVs.

Oxide fusion is another typical technique for bonding, where bonding films are used for this purpose. The advantages of oxide bonding include avoidance of high stresses due to the thermal compression, higher tolerance to the alignment accuracy thereby enhancing reliability, and the suitability of this approach for dense and fine pitch TSVs [128,134]. Alternatively, issues with oxide bonding primarily relate to the bonding films, where key requirements include [128,130]

Depending upon the bonding mechanism and material, certain requirements should be satisfied to avoid delamination and cracking of the tiers:

Achieving a reliable bond throughout the lifetime of a 3-D stack is an important requirement for any bonding and/or assembly process. A host of tests based on industry standards are applied to ensure the reliability of the manufactured 3-D stack [140]. These reliability tests include [130,141]:

The final processing step for a 3-D IC with TSVs is removal of the handle wafer and cleaning the tier surface if subsequent bonding is required. A variety of solutions can be used to detach the handle wafer. The time to accomplish this step also depends upon the size of the wafer [120].

3.3.1 Capacitively Coupled Three-Dimensional ICs

In capacitively coupled signaling, the TSVs are replaced with small on-chip parallel plate capacitors that provide intertier communication to the upper tier. A schematic of a capacitively coupled 3-D system is illustrated in Fig. 3.13 [142]. A buffer drives the capacitor. The receiver circuitry, however, is more complex, as the receiver must amplify the low voltage signal to produce a full swing output. In addition, the receiver circuit should be sufficiently sensitive and fast to detect and respond to the voltage transferred through the coupling capacitors. The maximum voltage level that can be propagated through a coupling capacitance C_c is [143]

$\Delta V_{\max }=\frac{C_c}{C_c+C_P+\sum C_{\mathit{tr}}}\Delta V_{\mathrm{in}},$ (3.1)

(3.1)

where C_p is the capacitance of the capacitor plate to the substrate and adjacent interconnect preceding the receiver. The denominator in (3.1) includes the capacitance of the transistors at the input of the receiver.

A 5 fF capacitance has been used in [143] to transmit a signal to several receiver architectures. This capacitance uses 20 μm×20 μm electrodes with a separation of 2.5 μm (e.g., dielectric thickness) and a dielectric constant of 3.5. Simulations indicate correct operation for frequencies up to 500 MHz, while measurements show successful operation for signal transmission up to 25 MHz for a 0.5 μm CMOS technology. Smaller parallel plate capacitor structures and improved transceiver circuitry have also been reported, yielding a communication bandwidth of 1.23 Gb/s [144]. For a 0.13 μm CMOS technology the size of the capacitor electrodes is 8 μm×8 μm. Comparing capacitively coupled 3-D ICs with SiP, where the intertier wiring is over the edge of the IC (the total interconnect length is on the order of a centimeter), a 30% improvement in delay is demonstrated. In addition, significant dynamic power is saved with this interconnect scheme. The static power consumed by the receiving circuitry, however, decreases the overall power savings.

The parasitic capacitance of the devices is greatly reduced with a silicon-on-sapphire technology, an early type of SOI technology [142]. This situation is particularly advantageous for power transfer circuits realized with a charge pump. The transceivers and charge pump circuits have been fabricated in a 0.5 μm CMOS technology [142], utilizing capacitors with dimensions of 90 μm×90 μm. The distance between the two tiers is 10 μm. Decreasing the separation between the tiers can increase the coupling, requiring smaller capacitor plates to propagate a signal. The capacitors used for the power exchange should be large, though, for enhanced coupling. A prototype based on this technique provides approximately 0.1 mA current to the devices on the upper tiers. Successful operation up to 15 MHz has been demonstrated [142].

Critical factors affecting this technique are the size of the capacitors, which affects the interconnect density, the intertier distance, and the dielectric constant of the material between the tiers, which determine the amount of coupling. Face-to-face bonding is preferable as the distance between the tiers is shortened. Interconnecting a 3-D IC consisting of more than two tiers with this approach, however, is a challenging task.

3.3.2 Inductively Coupled Three-Dimensional ICs

Inductive coupling can be an alternative for contactless communication in 3-D ICs. Each tier in a two-tier 3-D IC accommodates a spiral inductor, located at the same horizontal coordinates (see Fig. 3.14). The size and diameter of the inductors are based on an on-chip differential transformer structure [145]. Inductors with a diameter of 100 μm have been shown to be suitable for signal transmission, where the inductors are separated by a distance of 20 μm. In contrast to capacitively coupled 3-D ICs, signal propagation is achieved through current pulses. As compared to the capacitive coupling technique, specialized circuitry both for the transmitter and receiver is required, dissipating greater power. A current-mode driver generates a differential signal. The receiver amplifies the transmitted current or voltage pulses, producing a full swing signal. Alternatively, inductive coupling does not require as small a separation of the tiers as with the capacitive coupling technique, relaxing the demand for thin spacing between tiers. This advantage supports the integration of more than two tiers for inductively coupled 3-D ICs. Simulations indicate 5 Gb/s throughput with 70 ps jitter at the output, consuming approximately 15 mW [145].

The main limitations of this technique include the size of the inductors, which yields a low interconnect density as compared to the size of the TSVs, increased power consumption of the transceiver circuitry, and interference among adjacent on-chip inductors. Additionally, power delivery to the upper tiers is realized with galvanic connections for high performance applications. Consequently, the fabrication process and cost for this type of 3-D IC is not greatly simplified as the TSV formation step is not eliminated for this type of applications. Alternatively, applications that lie in the low power regime can benefit more from this approach by eliminating the galvanic connections between tiers and supporting contactless power transfer in addition to wireless signaling. Due to the potential of this contactless scheme, Chapter 6, Three-Dimensional ICs with Inductive Links, is dedicated to the design and modeling of inductive links for contactless 3-D systems.