Table of Contents
1.1 Interconnect Issues in Integrated Systems
1.2 Three-Dimensional or Vertical Integration
Chapter 2. Manufacturing of Three-Dimensional Packaged Systems
2.1 Stacking Methods for Transistors, Circuits, and Dies
2.3 Technologies for System-in-Package
2.4 Technologies for 2.5-D Integration
Chapter 3. Manufacturing Technologies for Three-Dimensional Integrated Circuits
3.1 Monolithic Three-Dimensional ICs
3.2 Three-Dimensional ICs with Through Silicon Via or Intertier Via
3.3 Contactless Three-Dimensional ICs
3.4 Vertical Interconnects for Three-Dimensional ICs
Chapter 4. Electrical Properties of Through Silicon Vias
4.1 Physical Characteristics of a Through Silicon Via
4.2 Electrical Model of Through Silicon Via
4.3 Modeling a Three-Dimensional Via as a Cylinder
4.5 Through Silicon Via Impedance Models
4.6 Electrical Characterization Through Numerical Simulation
4.7 Case Study—Through Silicon Via Characterization of the MITLL TSV process
Chapter 5. Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs
5.1 Heterogeneous Substrate Coupling
5.3 Techniques to Improve Noise Isolation
Chapter 6. Three-Dimensional ICs with Inductive Links
6.1 Wireless On-Chip Communication Interfaces
6.2 On-Chip Inductors for Intertier Links
6.3 Transmitter and Receiver Circuits
6.4 Challenges for Wireless On-Chip Communication
Chapter 7. Interconnect Prediction Models
7.1 Interconnect Prediction Models for Two-Dimensional Circuits
7.2 Interconnect Prediction Models for Three-Dimensional ICs
7.3 Projections for Three-Dimensional ICs
Chapter 8. Cost Considerations for Three-Dimensional Integration
8.1 Through Silicon Via Processing Options
8.2 Interposer-Based Systems Integration
8.3 Comparison of Processing Cost for 2.5-D and Three-Dimensional Integration
Chapter 9. Physical Design Techniques for Three-Dimensional ICs
9.2 Floorplanning Three-Dimensional ICs
9.4 Placement in Three-Dimensional ICs
Chapter 10. Timing Optimization for Two-Terminal Interconnects
10.1 Intertier Interconnect Models
10.2 Two-Terminal Nets With a Single Intertier Via
10.3 Two Terminal Interconnects With Multiple Intertier Vias
Chapter 11. Timing Optimization for Multiterminal Interconnects
11.1 Timing Driven Via Placement for Intertier Interconnect Trees
11.2 Multiterminal Interconnect Via Placement Heuristics
11.3 Via Placement Algorithms for Interconnect Trees
11.4 Discussion of Via Placement Results
Chapter 12. Thermal Modeling and Analysis
12.1 Heat Transfer in Three-Dimensional ICs
12.2 Closed-Form Temperature Models
12.3 Mesh-Based Thermal Models
12.4 Thermal Analysis Techniques
Chapter 13. Thermal Management Strategies for Three-Dimensional ICs
13.1 Thermal Management Through Power Density Reduction
13.2 Thermal Management Through Enhanced Thermal Conductivity
13.3 Hybrid Methodologies for Thermal Management
Chapter 14. Case Study: Thermal Coupling in 3-D Integrated Circuits
14.1 Thermal Propagation Test Circuit
14.3 Design Considerations Based on Experimental Results
14.4 Verification of Experimental Results with Simulations
Chapter 15. Synchronization in Three-Dimensional ICs
15.1 Synthesis Techniques for Planar Clock Distribution Networks
15.2 Global Three-Dimensional Clock Distribution Networks
15.3 Synthesis of Three-Dimensional Clock Distribution Networks
15.4 Practical Considerations of Three-Dimensional Clock Tree Synthesis
Chapter 16. Case Study: Clock Distribution Networks for Three-Dimensional ICs
16.1 MIT Lincoln Laboratories Three-Dimensional IC Fabrication Technology
16.2 Three-Dimensional Test Circuit Architecture
16.3 Clock Distribution Network Structures Within the Test Circuit
Chapter 17. Variability Issues in Three-Dimensional ICs
17.1 Process Variations in Data paths Within Three-Dimensional ICs
17.2 Effects of Process Variations on Clock Paths
17.3 Effect of Process and Power Supply Variations on Three-Dimensional Clock Distribution Networks
Chapter 18. Power Delivery for Three-Dimensional ICs
18.1 The Power Delivery Challenge
18.2 Models for Three-Dimensional Power Distribution Networks
18.3 Through Silicon Via Technologies to Mitigate Power Supply Noise
18.4 Decoupling Capacitance for Three-Dimensional Power Distribution Networks
18.5 Wire Sizing Methods in Three-Dimensional Power Distribution Networks
Chapter 19. Case Study: 3-D Power Distribution Topologies and Models
19.1 3-D Power Distribution Network Test Circuit
19.3 Characteristics of 3-D Power Distribution Topologies
Chapter 20. 3-D Circuit Architectures
20.1 Classification of Wire Limited 3-D Circuits
Appendix A. Enumeration of Gate Pairs in a 3-D IC
Appendix B. Formal Proof of Optimum Single Via Placement
Appendix C. Proof of the Two-Terminal Via Placement Heuristic
Appendix D. Proof of Condition for Via Placement of Multi-terminal Nets
Appendix E. Correlation of WID Variations for Intratier Buffers
Appendix F. Extension of the Proposed Model to Include Variations of Wires