Keywords

Multi-level power delivery in 3-D ICs; decoupling capacitance; TSV power distribution paths; TSV tapering; wire sizing for power integrity

18.1 The Power Delivery Challenge

Vertically integrating multiple circuit tiers affects a power network in two ways. First, the horizontal dimensions of the power distribution network are significantly reduced as compared to the footprint of a 2-D circuit. The power distribution networks within the different tiers are connected with TSVs. These vertical interconnections increase the resistance seen by the active circuits of the stack located farther from the package. This situation is aggravated as the number of tiers increases. At the circuit package boundary, as the footprint of the stack decreases, a smaller number of power/ground (P/G) C4 connections are available to supply current for the entire stack. Consequently, a large current flows through these connections and the TSVs, producing significant resistive losses across the circuit stack.

As 3-D systems support the integration of heterogeneous technologies and functionalities within a circuit stack, an efficient scheme to deliver power across a 3-D circuit employs a single tier dedicated to power delivery [666]. This approach is similar to the strategy discussed in Chapter 15, Synchronization in Three-Dimensional ICs, where an entire tier within a 3-D circuit is utilized for deploying the synchronization circuitry. Rather than allowing a large current to flow from the VRM at a low voltage compatible with the on-chip power supply, as shown in Fig. 18.1, conversion to the voltage level of the integrated circuits takes place in one of the tiers within the 3-D stack. A lower current flowing through the power distribution system reduces the resistive losses across the board and package.

There are several advantages for this approach, where the most important advantage is the decrease in interconnect parasitic impedances between the source of power (i.e., VRM) and the logic tier. Additionally, the multiple voltage levels required in modern ICs are distributed on-chip with lower losses. This on-chip converter enables local dynamic scaling of voltages. Since all of the voltages are produced on-chip, the number of P/G pins can also be reduced.

Integration of a buck converter is demonstrated in a 180 nm SiGe bipolar CMOS (BiCMOS) process [666] where the operating frequency of the converter is 200 MHz and the control bandwidth is about 10 MHz. This converter is integrated into the tier adjacent to the logic tier (e.g., a processor), as schematically shown in Fig. 18.2. The passives required for the buck converter are placed in the third tier and can therefore be separately optimized to minimize the parasitic losses of the converter.

A first order circuit diagram of the tested converter is shown in Fig. 18.3, where the gate drivers, control switch, synchronous rectifier, output LC filter, and active load are illustrated. Two converters drive the logic tier. An input of 1.8 volts is converted to 0.9 volts to drive the load. An operating frequency of 200 MHz ensures that the area of the LC filter is not excessive. Within the power stage the PMOS control switch has an equivalent width of 16.6 mm, with an on-resistance of 152 mΩ. The NMOS synchronous rectifier has an equivalent width of 11 mm with an on-resistance of 62 mΩ. The tapered buffers driving both the control switch and synchronous rectifier have a tapering ratio of nine. The output capacitor of the LC filter uses a metal oxide semiconductor (MOS) capacitance to limit the area as compared to metal–insulator–metal (MIM) capacitors. An 8.22 nF capacitance is utilized. The effective series resistance of the MOS capacitor is 1 mΩ.

For the inductor of the converter, two shunted metal layers are used. The width of the windings of the inductor is 25 μm to reduce the resistance of the inductor while maintaining a high quality factor. The DC resistance (no skin and other high frequency effects are considered) of the inductor is 201 mΩ. 3.5 windings are spaced at a distance of 5 μm. The resulting diameter of the inductor is 290 μm, yielding an inductance of 2.14 nH. Furthermore, the quality factor of the inductor is enhanced by placing a patterned metal as a ground plane to reduce eddy current losses within the substrate. The primary design parameters for this converter are listed in Table 18.1. The prototype circuit exhibits an efficiency of 64% while operating at 200 MHz, providing an output current of 500 mA.

Integration of DC–DC converters within a 3-D stack can also be performed in a more systematic approach, where these converters are placed within more than one tier of the stack. As these components, however, occupy significant area, these circuits should be appropriately modeled to better evaluate any benefits of a multitier approach. The primary benefit of on-chip buck converters is to reduce the resistance of the power distribution paths, where the contribution of the TSV resistance is not negligible. To quantify any gains from the integrated buck converters, the architecture of a 3-D stack shown in Fig. 18.4 is assumed where the buck converters are integrated within the tiers at both ends of the 3-D system. The use of a buck converter at the uppermost tier in this example is justified by the long distance from the tier to the package.

To address the potentially high resistive voltage drop, the buck converters can be configured as follows. The buck converter within the uppermost tier supplies the upper half of the stack, while the buck converter within the bottommost tier supplies the lower half. Thus, if the 3-D circuit comprises n tiers, tiers 1 to n/2 are supplied by the converter in tier 1 and tiers n/2+1 to n are supplied by the converter in tier n. Consequently, the longest vertical path within the n tier stack is reduced from n−1 TSVs to n/2−1 TSVs; the path is essentially halved.

To ascertain the merits of this approach, a closed-form model is provided, assuming that each tier draws the same current and the density of the P/G TSVs is the same for all of the tiers. Although these assumptions are unlikely to be precise, this assumption allows a first order model to offer insight into the efficiency of this scheme [667]. An equivalent circuit for a 3-D stack that includes only one converter in one of the tiers, as in [666], is illustrated in Fig. 18.5. The total IR drop across n tiers is [667]

$V_{\mathrm{drop}}\left(n,k_{\mathrm{TSV}}\right)=\left(n-1\right)I\frac{r_{\mathrm{TSV}}}{\frac{k_{\mathrm{TSV}}}{2}}+\left(n-2\right)I\frac{r_{\mathrm{TSV}}}{\frac{k_{\mathrm{TSV}}}{2}}+\cdots +I\frac{r_{\mathrm{TSV}}}{\frac{k_{\mathrm{TSV}}}{2}}+\left(n-1\right)I\frac{r_{\mathrm{TSV}}}{\frac{k_{\mathrm{TSV}}}{2}}$

$+\left(n-2\right)I\frac{r_{\mathrm{TSV}}}{\frac{k_{\mathrm{TSV}}}{2}}+\cdots +I\frac{r_{\mathrm{TSV}}}{\frac{k_{\mathrm{TSV}}}{2}}=\frac{2{\mathit{Ir}}_{\mathrm{TSV}}}{k_{\mathrm{TSV}}}n\left(n-1\right),$ (18.1)

(18.1)

with the help of the arithmetic progression formula. In this expression, k_TSV is the total (i.e., both power and ground) number of TSVs in each tier, and I is the current drawn by each tier. If two buck converters are employed, the equivalent 1-D model for the power distribution system is illustrated in Fig. 18.6, where each converter is responsible for providing current to only half of the tiers. Consequently, the IR drop decreases to $V_{\mathrm{drop}}^{\prime }(n/2,k_{\mathrm{TSV}})=({\mathit{Ir}}_{\mathrm{TSV}}/{2k}_{\mathrm{TSV}})n\left(n-2\right)$. This reduction is the ratio of the voltage drop in the single converter approach [667]

$\frac{V_{\mathrm{drop}}^{\text{'}}\left(\frac{n}{2},k_{\mathrm{TSV}}\right)}{V_{\mathrm{drop}}\left(n,k_{\mathrm{TSV}}\right)}=\frac{1}{4}·\frac{n-2}{n-1}<\frac{1}{4}.$ (18.2)

(18.2)

This reduction, however, incurs some power and area overhead due to the TSVs connecting V_DDH to the uppermost tier of the 3-D circuits. To determine the power overhead of these TSVs, assume the power consumed by the resistance of these TSVs is [667],

$P_{\mathrm{TSV},H}=2\frac{r_{\mathrm{TSV}}}{\frac{k_{\mathrm{TSV},H}}{2}}\left(n-1\right)I_H^2=\frac{4r_{\mathrm{TSV}}}{k_{\mathrm{TSV},H}}\left(n-1\right)I_H^2,$ (18.3)

(18.3)

where k_TSV,H is the number of P/G TSVs for each tier. Note that only the voltage drop on the power TSVs is computed. The number of power TSVs is k_TSV,H/2. Furthermore, as the current drawn by each tier is I, the power consumed by the load for the single buck converter approach is P_load=nIV_DDL. If two buck converters are used, the efficiency of the converter located within the tier farthest from the package pins, connected to V_DD,H through the TSVs, is

$\eta =\frac{P_{\mathrm{out}}}{P_{\mathrm{in}}}=\frac{P_{\mathrm{load}}/2}{V_{\mathrm{DDH}}{I}_H}.$ (18.4)

(18.4)

Combining (18.3) and (18.4), the ratio of the power overhead of the additional TSVs for the buck converter over the total power is

$\frac{P_{\mathrm{TSV},H}}{P_{\mathrm{load}}}=\frac{r_{\mathrm{TSV}}{P}_{\mathrm{load}}\left(n-1\right)}{{\eta }^2{V}_{\mathrm{DDH}}^2}\left(\frac{k_{\mathrm{TSV},L}}{k_{\mathrm{TSV},H}}\right)\frac{1}{k_{\mathrm{TSV},L}}.$ (18.5)

(18.5)

Similarly, the number of TSVs in the downstream power distribution network is obtained by combining V_drop(n/2, k_TSV,L) and P_load into [667],

$\frac{1}{k_{\mathrm{TSV},L}}=\frac{2V_{\mathrm{DDL}}^2}{r_{\mathrm{TSV}}{P}_{\mathrm{load}}(n-2)}\left(\frac{V_{\mathrm{DDL}}}{V_{\mathrm{DDH}}}\right).$ (18.6)

(18.6)

The combination of (18.5) and (18.6) provides an analytic description of the TSV area and power overhead for different target efficiencies, which are

$\frac{k_{\mathrm{TSV},H}}{k_{\mathrm{TSV},L}}\frac{P_{\mathrm{TSV},H}}{P_{\mathrm{load}}}=\frac{2}{{\eta }^2}\frac{n-1}{n-2}\left(\frac{V_{\mathrm{drop}}^{\prime }}{V_{\mathrm{DDL}}}\right){\left(\frac{V_{\mathrm{DDL}}}{V_{\mathrm{DDH}}}\right)}^2=\frac{1}{2{\eta }^2}\frac{n-2}{n-1}\left(\frac{V_{\mathrm{drop}}}{V_{\mathrm{DDL}}}\right){\left(\frac{V_{\mathrm{DDL}}}{V_{\mathrm{DDH}}}\right)}^2.$ (18.7)

(18.7)

For a large number of tiers the ratios, (n−1)/(n−2) and (n−2)/(n−1), can be considered equal to one. From (18.7), several tradeoffs can be explored. For example, assuming V_DDH=3.3 V and V_DDL=1.2 V, if an efficiency of η=0.8 is desired, the area of the TSVs increases by 35%. These additional TSVs add a power overhead of about 3%. The IR drop simultaneously decreases from 10% to 2.5%, a factor of four improvement.

Using two buck converters in a large vertical stack has been evaluated through a daisy chain connection of TSVs in a single tier, where this chain connection represents a vertical path of P/G TSVs [667]. The diameter of the TSVs is 20 μm with a pitch of 50 μm. The typical resistance of a single TSV is 29 mΩ. A buck converter drives the TSV chain where several active loads are interspersed among the TSVs, mimicking the load for each tier of a 3-D stack. This structure is shown in Fig. 18.7, where the resistance of the TSV shown in the diagram corresponds to a signal path crossing eight tiers. Each of the active loads is 200 mA and, therefore, the output current of the converter is 1,600 mA.

The inductor of the buck converter exhibits a resistance of 40 mΩ and inductance of 3.9 nH. The dimensions of the inductor are 1.6 mm×0.8 mm×0.8 mm and the inductor is placed off-chip. The capacitor is also off-chip, exhibiting a capacitance of 1 μF with dimensions 1.0 mm×0.5 mm×0.5 mm. These sizes are chosen based on [668]. The fabricated converter has an efficiency of 72% and bandwidth of 62 MHz. Measurements of a prototype test circuit with the eight daisy chained TSVs demonstrate that two buck converters each supplying half of the tiers reduces the IR drop by 78% as compared to employing a single converter supplying all of the active loads through the entire TSV stack, consistent with the analytic model [667].

18.1.1 Multilevel Power Delivery for Three-Dimensional ICs

The primary advantage of integrating DC–DC converters within several tiers of a 3-D circuit is lower current flow through the power distribution system, incurring lower losses. 3-D systems lend themselves to another interesting power distribution strategy. Differential rails are used between adjacent tiers [669]. Consequently, the power network of a specific tier is connected to those voltage levels that ensure a voltage difference V_dd appears between the power and ground lines. Assuming, for example, m power supply levels where each level is a multiple of V_dd, the power network of the m^th and m−1 levels is connected, respectively, to mV_dd and (m−1) V_dd. Only one network has a ground rail connected to zero voltage. An illustration of this “multi-level” V_dd scheme is depicted in Fig. 18.8 for a three tier system, where in this topology each tier is connected to a pair of voltage levels. The main advantage of the multilevel approach is that charge is recycled among differential pairs of power supply rails. In this way, power supply noise is considerably reduced [669]. This charge recycle is ideal when each tier draws the same current. Although this requirement may be feasible for homogeneous 3-D circuits, for example, memory stacks, this demand cannot be satisfied in a straightforward manner for other more heterogeneous systems and requires additional measures, as discussed in this subsection.

To assess the benefits of a multilevel power delivery system employed in 3-D circuits, consider the example illustrated in Fig. 18.9 [669]. In Fig. 18.9A, the sum of the resistance of the vertical P/G paths, with 2k_TSV TSVs for a 3-D circuit composed of n tiers, is substituted by a resistance within a single tier. The load of all of the tiers is modeled as a single current source with amplitude I. The total resistance of each vertical path (i.e., power or ground) is notated as r, and is inversely proportional to the number of TSVs used for power and ground distribution, r∝1/k_TSV. The total number of TSVs is 2k_TSV and is assumed to be split equally among the tiers, unless mentioned otherwise. For the circuit shown in Fig. 18.9A, the resistive voltage drop and power dissipated by the vertical path of the power distribution network are, respectively, 2Ir and I²r. If multilevel power delivery is applied where only one pair of voltage levels is assigned to a tier, each tier draws I/n current and the resistance of each TSV path is 0.5r(n+1) and consists of 2k_TSV/(n+1) TSVs, as illustrated in Fig. 18.9B.

If all of the tiers are active, the current only flows through the paths at the edges of the circuit (see Fig. 18.9B), thereby incurring the smallest voltage drop. The worst case situation in terms of IR drop occurs when the current is not balanced among the tiers, which only happens if one tier is active. In this case, the resistive supply noise is Ir(n+1)/n, which is lower than a single V_dd for n>1. Furthermore, the power consumed by the stack is maximum whenever successive tiers operate alternately, which in the case of two pairs of voltages yields the greater reduction in noise as compared to a single V_dd. Increasing the number of power levels returns diminishing gains.

Based on this discussion, different mappings of a multi-level power delivery scheme can be applied to a 3-D circuit. An example of a three tier system is considered where two tiers are memory tiers and another tier hosts a processor, as depicted in Fig. 18.10. The memory tiers are assumed to sink current I, while the processor tier draws twice as much current. The technology assumed for this system is the MIT Lincoln Laboratories (MITLL) 3-D technology [670]. In this technology, a TSV spans each of the three tiers and is comprised of two stacked single TSVs, where the extracted resistance of a single TSV is 1 Ω. The resistance of a stacked TSV, in this example, is split into three resistive segments with values of 0.5, 1, and 0.5 Ω, which are the vertical resistance of the corresponding tier.

Assuming that this circuit is manufactured with the MITLL technology and these TSV resistances, if the resistance of the vertical path in the first tier is denoted by r and since the total number of TSVs is equally distributed among the tiers, the resistance of the vertical path across the tiers is r, 2r, and r for, respectively, the first, second, and third tier. Based on these assumptions the power supply noise in the tier farthest from the power supply tier (see Fig. 18.10) is 2(r4I+2r3I+r2I)=24rI. To reduce this power supply noise, two pairs of voltage levels (i.e., 2V_dd to V_dd and V_dd to V_gnd) are used within each tier, as depicted in Fig. 18.11A. This two level power delivery system yields a maximum IR drop of 18Ir. If some part of the circuit is power gated, as illustrated in Figs. 18.11B and C, the leakage current, assumed to be aI, of the inactive circuits opposes the current flow in the active part of the system, reducing the resulting power supply noise [669]. In both Figs. 18.11B and C, the power supply noise becomes 18Ir−9aIr. For large leakage currents, a=0.5. The decrease in noise as compared to the fully active system of Fig. 18.11A is 44%.

The use of multiple power supply pairs within a tier, however, incurs considerable overhead, requiring, for example, many level shifters. A more straightforward power delivery topology is consequently shown in Fig. 18.12, where the two memory tiers are connected, respectively, to 2V_dd and V_dd, and the processor tier is connected to V_dd and V_gnd. As this tier consumes equal current in both of the memory tiers, the resulting power delivery topology is balanced, leading to a maximum decrease in IR drop. Similar to the previously mentioned topologies, the worst IR drop appears when current imbalances exist between the two power networks. Two cases are illustrated, respectively, in Figs. 18.12B and C. The power supply noise when the memory tiers are inactive is V_drop1=12Ir−12aIr. If the processor tier is power gated, the power supply noise is V_drop2=24Ir−6aIr. Consequently, the highest power supply noise is V_drop=max[(24Ir−6aIr), (12Ir−12aIr)].

In all of these different topologies for the multi-level power delivery system, the number of TSVs per tier is considered the same, which limits the benefits obtained from this power delivery approach. If the number of TSVs can be adjusted on a per tier basis, the problem of determining the power supply noise becomes an optimization problem, which can be roughly described as follows. Consider a three tier system similar to those discussed thus far. For each tier i, determine the number of TSVs k_TSVi ensuring that the total number of TSVs is equal to k_TSV and the power supply noise is minimum which is described by max(V_drop1, V_drop2). For different leakage currents, different TSV distributions reduce the power supply noise to between 22% and 34%. The resulting TSV distribution among the tiers is typically greatest for the two highly imbalanced cases (see Figs. 18.12B and C). Alternatively, the TSVs can be optimally distributed across tiers to reduce the resistive power consumed by the power distribution network.

Although this first order analysis illustrates the potential of a multi-level power delivery system, several difficulties exist that may limit application of this approach. The predominant issue emerges from the requirement to maintain balanced currents among the tiers (assuming each tier employs a single pair of voltage levels). Furthermore, intertier signals may require voltage level conversion which adds nonnegligible latency and area overhead. Since intertier signals typically belong to the critical paths, this overhead can greatly degrade the performance of the system. Additionally, applying commonplace techniques for power savings, such as dynamic voltage scaling, is not straightforward.

One way to overcome this issue of imbalanced currents is to add converters to produce a voltage difference of V_dd between the power and ground rails in each tier. The power efficiency of a system that employs these converters is proportional to the imbalance in current across the system, since the larger the current imbalance, the more charge the converter needs to provide, thereby reducing the power efficiency. Although using a large number of converters requires significant area, this overhead can be compensated by reducing the density of the TSVs used to distribute power.

Simulations of an eight tier stacked processor architecture based on the ARM Cortex A9 dual-core demonstrate that a multilevel power delivery system exhibits similar supply noise as compared to a standard single V_dd supply system if the workload imbalance across the tiers remains under 50% with the same area overhead [671]. The overhead in the standard supply system is the area occupied by the power TSVs while for the multilevel power delivery system, the overhead comprises the area of the converters and the fewer number of power TSVs.

Although modern EDA tools yield robust and high quality power networks in planar circuits, no provision exists for the vertical wires, which produce significant power supply noise [672,673]. The role of these wires in modeling and designing power distribution networks for 3-D circuits is discussed in the following sections.

18.2 Models for Three-Dimensional Power Distribution Networks

All of the 3-D power delivery techniques discussed in the previous section utilize a 1-D model of the on-chip power distribution network and emphasize resistive IR voltage drops. Consequently, a simple resistive network is used. Additionally, the TSV are modeled as a resistor, which adds resistance to the on-chip power distribution network. Although these models are useful in demonstrating the benefits of these power delivery approaches, these models do not provide an accurate analysis of the behavior of 3-D power distribution networks.

Several models with different accuracy and complexity have been developed to characterize the behavior of these networks. The impedance of these networks is modeled across a large range of frequencies, utilizing a combination of lumped and distributed models for the disparate components of the power distribution system. Analytic models are first discussed in this section, listing the assumptions that allow a closed-form treatment of these complex interconnection structures. More advanced models that support a more practical analysis with fewer assumptions are also presented. These models simplify the power distribution networks, enabling analysis with reasonable simulation times and accuracy over a large range of frequencies which exceed by several times the typical operating frequency of digital circuits.

As interconnect meshes are typical topologies for power distribution networks [205], most models assume that the power distribution network of each tier is composed of two or more global metal layers, which are densely connected with metal contacts. Pads are periodically inserted in one of the tiers (the tier connected to the package), forming an array of power and ground pads. The other tiers within the 3-D circuit are connected through P/G TSVs to this tier. The illustrative example shown in Fig. 18.13A includes three tiers where the uppermost tier is assumed to be connected to the package. The power and ground networks are decoupled and can be analyzed separately, as shown in Fig. 18.13B. Assuming that the same network is used in every tier and is uniformly structured, the network can be divided into multiple identical cells, which are electrically modeled as shown in the same figure. The boundary of this cell is illustrated by a dashed rectangle (see Fig. 18.13B) and is adjacent to the (V_dd or V_gnd) pads where a quarter of a pad is included at each corner of the cell to maintain symmetry across cells.

As depicted in Fig. 18.13B, each interconnect segment is modeled by a single resistor R_w, while the TSVs are modeled as a lumped LR element, notated as L_TSV and R_TSV. Within each cell, Δx and Δy are, respectively, the length of the x and y edges of the cell. The circuits within the area ΔxΔy of each cell are modeled as a current source of density J(s) in the frequency domain. The capacitor connected in parallel to the current source shown in Fig. 18.13B models the capacitance of the circuit and the intentional capacitance added as a decoupling capacitance. The package pins connected to the pads of one tier (the first tier in the example of Fig. 18.13A) are modeled as a lumped resistance R_p and inductance L_p. The number of cells constituting a power mesh is typically large to model the mesh as a continuous power (or ground) plane [675].

In this case, the power supply noise V_i(x,y,s) in tier i at coordinates (x, y) of the power (or ground) network and frequency s can be described by a partial differential equation [674],

${\nabla }^2{V}_i\left(x,y,s\right)=R_{\mathit{wi}}{J}_i\left(s\right)+2V_i\left(x,y,s\right)s{R}_{\mathit{wi}}{C}_{\mathit{di}}+{\Phi }_i\left(x,y,s\right),$ (18.8)

(18.8)

where Φ_i(x,y,s) is the source function which is the same for all but the tier connected to the package, and is [676]

${\Phi }_i\left(x,y,s\right)=R_{\mathit{wi}}\sum _{j=1}^{k_{\mathrm{TSV}}}\left(\frac{V_{\left(i-1\right)\mathrm{TSV}j}-V_{i\mathrm{TSV}j}}{s{L}_{\mathrm{TSV}j}+R_{\mathrm{TSV}j}}-\frac{V_{i\mathrm{TSV}j}-V_{(i+1)\mathrm{TSV}j}}{s{L}_{\mathrm{TSV}j}+R_{\mathrm{TSV}j}}\right)\delta \left(x-x_{\mathrm{TSV}j}\right)\delta \left(y-y_{\mathrm{TSV}j}\right).$ (18.9)

(18.9)

V_iTSVj is the voltage of the TSV j connected to tier i, k_TSV is the number of TSVs in each tier (which in this model is considered the same among tiers), and δ(x−x′) is the step function. The source function for the tier connected to the package (here assumed to be tier 1) differs from (18.9) and is

${\Phi }_1\left(x,y,s\right)=-\frac{R_{w1}}{4s{L}_p}{V}_{\mathrm{pad}}\left(s\right)\delta \left(x\right)\delta \left(y\right)+R_{w1}\sum _{j=1}^{k_{\mathrm{TSV}}}\left(-\frac{V_{1\mathrm{TSV}j}-V_{2\mathrm{TSV}j}}{s{L}_{\mathrm{TSV}j}+R_{\mathrm{TSV}j}}\right)\delta \left(x-x_{\mathrm{TSV}j}\right)\delta \left(y-y_{\mathrm{TSV}j}\right),$ (18.10)

(18.10)

where V_pad is the voltage of the P/G pads in tier 1. To provide a closed-form solution, boundary conditions for (18.8) are defined. Assuming that a quarter of the P/G pads at the corner of the cell supply all of the current in this cell and no current flows outwards or inwards at an upright angle to the boundary of the cell, the boundary conditions are

${\frac{\vartheta V_i}{\vartheta y}|}_{x=0}=0,{\frac{\vartheta V_i}{\vartheta y}|}_{x=\mathrm{\Delta }x}=0,{\frac{\vartheta V_i}{\vartheta x}|}_{y=0}=0,{\frac{\vartheta V_i}{\vartheta x}|}_{y=\mathrm{\Delta }y}=0,$ (18.11)

(18.11)

where the upper left corner of the cell is assumed to be located at (x, y)=(0,0). To solve (18.8), the following transformation is applied to yield a Helmholtz equation [677],

$V_i\left(x,y,s\right)=u_i\left(x,y,s\right)-\frac{J_i\left(s\right)}{2s{C}_{\mathit{di}}}.$ (18.12)

(18.12)

The PDE in (18.8) is rewritten as

${\nabla }^2{u}_i\left(x,y,s\right)={2u}_i\left(x,y,s\right)\mathrm{s}{R}_{\mathit{wi}}{C}_{\mathit{di}}+{\Phi }_{\mathit{ui}}\left(x,y,s\right),$ (18.13)

(18.13)

which also complies with the boundary conditions of the second kind

${\frac{\vartheta u_i}{\vartheta y}|}_{x=0}=0,{\frac{\vartheta u_i}{\vartheta y}|}_{x=\mathrm{\Delta }x}=0,{\frac{\vartheta u_i}{\vartheta x}|}_{y=0}=0,{\frac{\vartheta u_i}{\vartheta x}|}_{y=\mathrm{\Delta }y}=0.$ (18.14)

(18.14)

The transformed PDE (18.13) can be solved in the frequency domain using the Green’s function G(x, y, u, v, s) [677] of the Helmholtz equation, where x, y, u, and v, correspond to the mesh coordinates and the boundary conditions in (18.14). The resulting closed-form solution for the power supply noise in tier i (i ≠ 1) and 1 is, respectively,

$V_i\left(x,y,s\right)=R_{\mathit{wi}}\sum _{j=1}^{k_{\mathrm{TSV}}}\left(\frac{V_{\left(i-1\right)\mathrm{TSV}j}-2V_{i\mathrm{TSV}j}+V_{\left(i+1\right)\mathrm{TSV}j}}{s{L}_{\mathrm{TSV}j}+R_{\mathrm{TSV}j}}\right)G(x,y,x_{\mathrm{TSV}j},y_{\mathrm{TSV}j},s)-\frac{J_i\left(s\right)}{2s{C}_{\mathit{di}}},$ (18.15)

(18.15)

and

$V_1\left(x,y,s\right)=\frac{R_{w1}}{4s{L}_p}{V}_{\mathrm{pad}}\left(s\right)G(x,y,0,0,s)+R_{w1}\sum _{j=1}^{k_{\mathrm{TSV}}}\left(-\frac{V_{1\mathrm{TSV}j}-V_{2\mathrm{TSV}j}}{s{L}_{\mathrm{TSV}j}+R_{\mathrm{TSV}j}}\right)G(x,y,x_{\mathrm{TSV}j},y_{\mathrm{TSV}j},s)-\frac{J_1\left(s\right)}{2s{C}_{d1}}.$ (18.16)

(18.16)

In both of these expressions, the voltage of the pads V_pad and TSVs V_TSVj is unknown and, in addition to V_i, needs to be determined. This task can be achieved by transferring these unknowns to the left hand side and solving the resulting system of equations. A unique solution exists as there is the same number of equations and unknowns. The inverse Laplace transform is applied as a final step to obtain the power supply noise in the time domain, and the overall noise is the addition of the noise component from the power and ground networks.

The accuracy of these closed-form expressions is compared with SPICE simulations of structures similar to those illustrated in Fig. 18.13A for a five tier system assuming a 45 nm CMOS technology. The electrical characteristics of each tier are based on a 65 nm Intel processor [678], where the interconnect characteristics are not scaled to the 45 nm technology node. Comparisons of both the magnitude and phase of the power supply noise with SPICE exhibit an error of less than 4% for all of the investigated scenarios [674].

Although this model provides a fast estimate of the power supply noise and is easily integrated into mathematical software packages, the assumption of uniform traits, for example, the same current demand per cell and decoupling capacitance make the model over-restrictive. More elaborate models have been developed to relax these constraints. No closed-form solution however is available for these more elaborate models. Numerical methods and/or simulations are used to estimate the power supply noise. The salient feature of these models is the order of magnitude decrease in the number of elements that comprise the power distribution network, reducing the number of nodes for which the voltage is evaluated. Consequently, these models, in terms of complexity and computational time, are between the analytic models and the numerical simulation of a fully extracted netlist characterizing a power distribution network.

These simulation based models utilize the concept of unit cells; however, the cells contain additional circuit elements. More specifically, the effect of the silicon substrate is included [679]. This effect is expected to be more significant for memory tiers in 3-D systems as memory circuits utilize fewer metal layers as compared to logic circuits. In this configuration, the distance of the metal power distribution layers in a memory tier are closer to the substrate, and are therefore more strongly coupled with the silicon substrate.

From these observations, a unit cell of a power distribution network, similar to the circuit shown in Fig. 18.13B, is modeled to ensure that the decoupling capacitance and silicon substrate are both included. In a closed-form model, the pitch of the pads determines the boundary of the unit cells, whereas the size of the unit cells in this model is based on the frequency. One guideline is to limit the size of a unit cell in the x and y directions to be shorter than one tenth of the wavelength [679], as determined by the effective dielectric constant and highest frequency. In this way, a lumped model of a unit cell does not significantly affect the accuracy. Furthermore, each unit cell is modeled as a two port electric network.

These two port networks are assembled using the segmentation method [679] to form a model of a complete power network. This method connects the two port networks in appropriate matrices to characterize the overall power distribution network. An example of the segmentation method linking the different unit cells to form a larger network is shown in Fig. 18.14. Within a unit cell, the decoupling capacitance is modeled by an RC lumped section while the P/G TSVs are modeled by a RLC lumped sections. Note that in this model the power and ground networks are not decoupled but rather are treated as a single network where each grid cell contains both power and ground segments.

An example of decomposing a unit cell into different segments along the x and y directions is shown in Fig. 18.15. Each of these segments is modeled as an RLGC lumped sections. Some of these segments are identical and share the same RLGC section; for instance, segments A_x and A_y. The corresponding RLGC lumped sections for segments A_x(y), B_x(y), and C_x(y) are depicted in Fig. 18.16. To limit the number of elements in the RLGC section, certain assumptions are applied to the modeling process. The most important assumption is that the lateral electric field between neighboring ground and power interconnects in the first metal layer (M1) is considerably lower than the field between a conductor and the substrate. Consequently, the conductors within these segments can be modeled as coplanar waveguides with infinitely distant ground planes.

Some components of the RLGC section are common for all of the different segments, A, B, and C. These components include the conductance of the silicon substrate G_sub, the power (ground) to substrate capacitance C_pSi (C_gSi), the substrate capacitance C_sub, and the coupling capacitance between power and ground lines C_pg which are described, respectively, by [679]

$G_{\mathrm{sub}}=2{\sigma }_{\mathrm{Si}}\frac{K(k_i)}{K(k_i^{\prime })},$ (18.17)

(18.17)

$C_{\mathrm{psi}}=C_{\mathrm{gsi}}={\epsilon }_{r,\mathrm{IMD}}{\epsilon }_0\left(\frac{W_1}{H_2}+0.77+1.06{\left(\frac{W_1}{H_2}\right)}^{0.25}+1.06{\left(\frac{T_1}{H_2}\right)}^{0.5}\right),$ (18.18)

(18.18)

$C_{\mathrm{sub}}=2{\epsilon }_{r,\mathrm{Si}}{\epsilon }_0\frac{K(k_i)}{K(k_i^{\prime })},$ (18.19)

(18.19)

and

$C_{\mathit{pg}(x)}={\epsilon }_{r,\mathrm{IMD}}{\epsilon }_0{C}_3^{\prime \mathrm{air}}.$ (18.20)

(18.20)

The inductance for each segment is determined from the capacitance of the structure assuming a lossless transmission line where the dielectric is air,

$L_x=\frac{1}{c^2{C}_x^{\prime \mathrm{air}}}.$ (18.21)

(18.21)

$C_x^{\prime \mathrm{air}}$ is different for A, B, and C and is based on the expressions listed in Table 18.2. The resistance R_x for each segment is also listed in the same table.

Table 18.2

Formulae for Computing the Components of the RLGC Lumped Model of a Unit Cell [679]

Segment A	Segment B	Segment C
$C_x^{\prime \mathrm{air}}=C_1^{\prime \mathrm{air}}+C_3^{\prime \mathrm{air}}$ (18.22) (18.22)	$C_x^{\prime \mathrm{air}}=2C_1^{\prime \mathrm{air}}$ (18.23) (18.23)	$C_x^{\prime \mathrm{air}}=C_1^{\prime \mathrm{air}}$ (18.24) (18.24)
$R_x=\frac{R_{M1}\left(\frac{W_1}{2}\right)}{W_1}+\left(\frac{0.5R_{M1}\left(\frac{W_1}{2}\right)}{\frac{W_1}{2}}\right)//\frac{R_{M2}\left(\frac{W_1}{2}\right)}{{5W}_1}$ (18.25) (18.25)	$R_x=\frac{R_{M1}{S}_1}{W_1}+\left(\frac{0.5R_{M1}{S}_1}{\frac{W_1}{2}}\right)$ (18.26) (18.26)	$R_x=\frac{R_{M1}\left(\frac{W_1}{2}\right)}{W_1}+\left(\frac{0.5R_{M1}\left(\frac{W_1}{2}\right)}{\frac{W_1}{2}}\right)$ (18.27) (18.27)
$C_i^{\prime \mathrm{air}}=2{\epsilon }_0\frac{K(k_i)}{K(k_i^{\prime })}$ (18.28) (18.28)	$\frac{K(k_i)}{K(k_i^{\prime })}=\left(\begin{array}{c}\frac{1}{\pi }\ln \left(\frac{2\left(1+\sqrt{k_i}\right)}{\left(1-\sqrt{k_i}\right)}\right),(0.5\le k_i^2\le 1)\\ \pi /\ln \left(\frac{2\left(1+\sqrt{k_i^{\prime }}\right)}{\left(1-\sqrt{k_i^{\prime }}\right)}\right),(0.0\le k_i^2\le 0.5)\end{array}\right)$ (18.29) (18.29)	$k_i^{\prime }=\sqrt{1-k_i^2}$ (18.30) (18.30)
$k_1=\frac{W_1}{W_1+2S_1}$ (18.31) (18.31)	$k_2=\frac{\mathrm{sin }h\left(\frac{{\pi W}_1}{4H_2}\right)}{\mathrm{sin }h\left(\frac{{\pi (W}_1+2S_1)}{4H_2}\right)}$ (18.32) (18.32)	$k_3=\frac{\mathrm{tan }h\left(\frac{{\pi W}_1}{4H_3}\right)}{\mathrm{sin }h\left(\frac{{\pi (W}_1+2S_1)}{4H_3}\right)}$ (18.33) (18.33)

To evaluate the accuracy of the model, a 3-D power distribution grid with an area of 1 mm×1 mm is utilized as a case study. This grid is simulated with a commercial EM solver and a frequency domain model for frequencies ranging from 0.1 GHz up to 20 GHz [679]. Any inaccuracy between the EM solver and model is low (around 10%) for frequencies far from the resonant frequency but increase significantly, exceeding 100% at the resonant frequencies. As the resonances occur at frequencies above 10 GHz, these inaccuracies are attributed to the large size of the cell. In other words, the accuracy is improved by increasing the number of cells to model the network while degrading the computational gains (as compared to a full electromagnetic (EM) solver).

18.2.1 Electro-Thermal Model of Power Distribution Networks

In Chapter 12, Thermal Modeling and Analysis, and Chapter 13, Thermal Management Strategies for Three-Dimensional ICs, the importance of thermal issues in 3-D circuits is discussed where the effects of temperature are integrated into several physical design techniques to avoid thermal hot spots. In addition to affecting the timing of signals and the leakage current, elevated temperatures also increase the resistance of the power and ground lines, thereby increasing the resistive voltage drop on these lines. Thermal issues are more important for P/G TSVs as these interconnections also act as the primary means to conduct heat towards the heat sink [673]. Consequently, in addition to thermal aware physical design, thermal issues are considered in the sign-off phase of the IC design process when the power distribution network is typically developed. Extending the models discussed in the previous section to the design of power distribution networks to consider temperature is a straightforward process due to the electro-thermal duality that enables the formulation of the heat equations as a linear system of equations.

Thermal models that utilize the electro-thermal duality are discussed in Chapter 12, Thermal Modeling and Analysis. These models utilize resistive or RC networks to evaluate the temperature across a circuit. The system of equations consists of known resistances and current sources, and the unknowns are the voltage at the nodes within a network. This formulation is similar to the linear system obtained for power grid analysis. By solving the thermal model to determine the temperature, and the electrical model to evaluate power supply noise, as illustrated in Fig. 18.17, the analysis converges to the temperature aware power supply noise. The thermal aware model of a power network discussed in this subsection enables a more accurate treatment of the design of power distribution grids as thermal issues affect the allocation of the P/G TSVs [673].

A mesh structure of the power and ground networks, similar to the structure shown in Fig. 18.13, allows the electrical RLC model of these networks to be obtained. To determine the voltage at the nodes of the network, a modified nodal analysis can be used [680]. With this method, first order differential equations are used to formulate the problem of determining the voltage at the network nodes. A portion of the power mesh for a three tier system is illustrated in Fig. 18.18 to describe the notation used in these differential equations. With this notation, the voltage node q in tier i is [472]

$V_q^i=\frac{\sum _{j\in s_q}{V}_j^i{g}_{\mathit{qj}}^i+\sum _{k\in \{i+1,i-1\}}{V}_q^k{g}_{\mathrm{TSV}}^{i,k}+{I(s)}_q^i}{\sum _{j\in s_q}{g}_{\mathit{qj}}^i+\sum _{k\in \{i+1,i-1\}}{g}_{\mathrm{TSV}}^{i,k}+{\mathit{sC}}_q^i},$ (18.34)

(18.34)

where s_q is the set of neighboring nodes of q, and i+1 and i−1 are adjacent to the i^th tier. The admittance between two nodes (e.g., j and q) is notated by g_qj, while the admittance of a TSV connecting two tiers at node q is denoted as g_TSV. The term I(s) models the current load and the capacitance at node q and tier i is notated as C_qⁱ. These quantities are also depicted in Fig. 18.18.

The voltage nodes can be written in matrix format for the entire mesh as [472]

$\left(\left[\begin{array}{ccc}{G}^1& G_{\mathrm{TSV}}^{12}& 0\\ G_{\mathrm{TSV}}^{21}& G^2& G_{\mathrm{TSV}}^{23}\\ 0& G_{\mathrm{TSV}}^{32}& G^3\end{array}\right]+s\left[\begin{array}{ccc}{C}^1& 0& 0\\ 0& C^2& 0\\ 0& 0& C^3\end{array}\right]\right)·\left[\begin{array}{c}{V}^1\\ V^2\\ V^3\end{array}\right]=\left[\begin{array}{c}{P}^1\\ P^2\\ P^3\end{array}\right],$ (18.35)

(18.35)

where Gⁱ_ni×ni, is a symmetric and sparse matrix of the conductance for the power network of tier i, while a similar system of matrices also applies to the ground network. The subscript ni×ni indicates that the network in each tier can be of different size. The terms $G_{\mathrm{TSV}}^{21}$ and $G_{\mathrm{TSV}}^{32}$ are diagonal matrices that contain the conductance of the TSVs that, respectively, connect the network of tier 1 to tier 2, and tier 2 to tier 3. The other two TSV conductance terms are the transpose of these matrices. The sparsity of the TSV conductance matrices depends upon the density of TSVs that connect the adjacent networks. The decoupling capacitance within the network of tier i is captured by the matrices Cⁱ_ni×ni, whereas the unknown voltage nodes in each tier are represented by the column vector Vⁱ_ni×ni. Finally, the current and voltage sources contained in the network of each tier are included in the vectors Pⁱ_ni×ni.

This linear system can be solved with respect to the voltage nodes with different methods, where multigrid methods as in [681] are good candidates. From the voltage nodes, the current flowing within each branch of the network in tier i (required for the thermal analysis) is

$J_{q-j}^i=\frac{I_{q-j}^i}{h_{q-j}{w}_{q-j}}=\frac{(V_q^i-V_j^i)g_{q-j}^i}{h_{q-j}{w}_{q-j}},$ (18.36)

(18.36)

where Iⁱ_q−j is the current flowing along branch q–j, and hⁱ_q−j and wⁱ_q−j are, respectively, the thickness and width of the wire used for branch q–j.

Due to the electro-thermal duality, the heat equation describing the temperature across the power distribution network can be described by a similar system of matrices as in (18.35). This description is more computationally efficient if the same number of nodes between the two matrices is utilized [472]. Both the power distribution and thermal networks for a 3-D circuit are mapped to the same geometric mesh.

In formulating the matrices of the thermal model, each matrix element is the thermal conductance of each branch of the power network between two metal contacts. Approximating this thermal conductance with a lumped element is valid if the length of this branch is not longer than the characteristic thermal length [437]. The notion of this length is that the heat from Joule heating of the wire (from the current flowing through this wire) flows to the adjacent metal layer located closer to the heat sink through the metal contacts (or TSVs) rather than the intermetal dielectric. The temperature of the wire is therefore determined by the temperature at the contacts, which facilitates the modeling process as the thermal and electrical networks have the same structure (i.e., the same nodal voltage and temperature (thermal voltage) are determined).

The thermal conductance is analogous to the electrical conductance, as described by [682]

$g_{\mathit{th}}=\rho {\kappa }_{\mathrm{metal}}{g}_{\mathrm{elec}},$ (18.37)

(18.37)

where ρ and κ_metal are, respectively, the electrical resistivity and thermal conductivity of the metal layer. Although both of these material properties are temperature dependent, only the dependence of the resistivity on temperature is considered in this model. The dependence of the metal resistivity on temperature is

$\rho ={\rho }_0\left[1+\beta \left(T-T_0\right)\right],$ (18.38)

(18.38)

where ρ₀ is the thermal resistivity at a reference temperature, and T₀ and β are temperature coefficients for the resistance. Typical values for these terms are T₀=27 °C and β=0.0039/°C. Consequently, the thermal resistance of a power (or ground) line of length L, width W, and thickness H in tier i is

$R_i=\rho \frac{L_i}{H_i{W}_i}\left[1+\beta \left(T-T_0\right)\right].$ (18.39)

(18.39)

The thermal capacitance models the heat capacity stored in the material as the temperature of the material changes. In ICs, heat is primarily stored within the silicon substrate. Thus, the thermal capacitance of a tier is

$C_{\mathit{th}}=c_p\mathit{tA},$ (18.40)

(18.40)

where c_p is the heat capacity of silicon, and t and A are, respectively, the thickness and area of the substrate of the tier. This thermal capacitance is uniformly distributed across the nodes of the thermal network.

Similar to the parasitic impedances of the package in an electrical model, the off-chip components of the thermal network should also be considered within the thermal model. Two paths for the heat to flow are typically modeled. Transfer of heat to the heat sink is the primary heat flow path, while the package boundary is the secondary path for the propagation of heat. A thermal resistor between the heat sink and each node of the thermal network models the propagation of heat between the IC and the heat sink. For the secondary path, a thermal resistance is employed for each C4 pin [550]. Finally, the TSVs are thermally modeled as an RC section based on [683]. These individual thermal components are combined into a thermal network with the same components as the dual electrical network shown in Fig. 18.18 (except for at the boundary of the heat sink and package), enabling computation of the temperature at the node q by

$T_q^i=\frac{\sum _{j\in s_q}{T}_j^i{g}_{{\mathit{th}}_{\mathit{qj}}}^i+\sum _{k\in \{i+1,i-1\}}{T}_q^k{g}_{{\mathit{th}}_{\mathrm{TSV}}}^{i,k}+Q_q^i}{\sum _{j\in s_q}{g}_{{\mathit{th}}_{\mathit{qj}}}^i+\sum _{k\in \{i+1,i-1\}}{g}_{{\mathit{th}}_{\mathrm{TSV}}}^{i,k}+{\mathit{sC}}_{{\mathit{th}}_q}^i},$ (18.41)

(18.41)

where T_j is the temperature at the neighboring nodes of q determined by the node set s_q, and $g_{{\mathit{th}}_{\mathit{qj}}}$ is the thermal conductance between any pair of nodes q and j. The term $Q_q^i$ denotes the heat generated at node q, which includes the power of the circuit and the Joule heating described by I²/g_qj for each wire segment between nodes q and j.

This combined electro-thermal model facilitates the exploration of several tradeoffs among the TSV density, sizing, number of horizontal wires, and decoupling capacitance, leading to the effective design of 3-D power distribution networks. The important role of TSVs in the behavior of these networks is discussed in the following section.

18.3 Through Silicon Via Technologies to Mitigate Power Supply Noise

As discussed in Chapter 3, Manufacturing Technologies for Three-Dimensional Integrated Circuits, TSV fabrication processes can be categorized as via-last, via-middle, and via-first. In addition to the fabrication process, different bonding styles, such as face-to-back or back-to-back exist. These combinations produce a variety of vertical interconnections for 3-D systems, with the TSVs connecting: (1) local-to-global, (2) global-to-global, and (3) local-to-local interconnect layers from adjacent tiers. For power and ground TSVs, this situation can provide additional paths to distribute power to reduce the distance to the current load. Furthermore, the TSVs can be of different diameter within each tier or with TSVs that are not solid but rather ring structures [684]. Several of these rings can be manufactured, resulting in coaxial TSVs (CTSVs). The effects of these manufacturing choices on the behavior of 3-D power distribution networks are reviewed in this subsection.

A CTSV consists of two or more metal rings separated by an inner layer of dielectric material. An example of one standard and one CTSV is, respectively, depicted in Figs. 18.19A and B. The choice of dielectric material and thickness of the separation layer primarily affects the electrical properties of the CTSV. The naturally higher capacitance of a CTSV does not significantly reduce the decoupling capacitance within the overall system; however, area gains exist from halving the number of required P/G TSVs. A CTSV can provide both power and ground; for example, at the outer and inner ring, requiring fewer TSVs to distribute power.

Other ways to reduce power supply noise emerge for the via-middle and via-first TSV processes. In these processes, the TSVs connect a global metal layer to an intermediate or local metal layer of an adjacent tier. For P/G TSVs, this connectivity provides an additional local path to distribute power and ground. Consider the one-dimensional model of two segments of a power distribution network within the 3-D circuit shown in Fig. 18.20, where a via-first process is assumed. A via-middle process can be treated similarly. The equivalent circuit of these two segments is illustrated in Fig. 18.21. Note that each circuit contains two paths with different impedance characteristics.

The primary difference between the two power delivery systems depicted in Figs. 18.20A and B is that the TSV in Fig. 18.20B connects only to the topmost metal layer (MT), while in Fig. 18.20A the TSV also connects to the first metal layer (M1). With the latter approach, additional paths are formed, which are shown by the thick solid curves in Fig. 18.20A. These paths are called “TSV paths” in the remainder of this section. To investigate the physical behavior of a TSV path, a current source is assumed to be connected to MT through a stack of intratier vias (i.e., metal contacts). Note that devices can only be placed at a certain distance from a TSV due to manufacturing constraints.

The current only flows through two metal layers (e.g., MT and M1). Inclusion of any other metal layer would increase the impedance of the path as MT is the least resistive layer. The on-chip inductance is omitted in this analysis due to the local (within a few micrometers) and fast decay of the effect that inductance has on the on-chip power distribution network [662]. The inductive component of the TSV impedance is, however, included in this analysis. Furthermore, the capacitance of the TSV is not considered, since for power and ground TSVs this capacitance behaves as a decoupling capacitance, improving the impedance characteristics of the power delivery system over a range of frequencies. Including the capacitance of the TSV in the analysis further demonstrates the effectiveness of the TSV path.

Based on the circuits shown in Fig. 18.21, a first order analysis is used to determine the greatest current that each of the circuits can carry while satisfying the voltage drop constraints. The maximum current that the circuits shown in Figs. 18.21A and B can carry is, respectively,

$I_L\le \frac{\left(1-V_{\mathrm{dropmax}}\right)V_{\mathit{dd}}}{\left(R_{M1}+Z_{\mathrm{TSV}}\right)\Vert \left(R_{\mathit{MT}}+R_{\mathrm{via}}\right)},$ (18.42)

(18.42)

and

$I_L\le \frac{\left(1-V_{\mathrm{dropmax}}\right)V_{\mathit{dd}}}{\left(R_{M1}+R_{\mathrm{via}}\right)\Vert \left(R_{\mathit{MT}}+R_{\mathrm{via}}\right)}.$ (18.43)

(18.43)

Z_TSV and R_via are, respectively, the impedance of a TSV and the resistance of a stack of vias connecting the topmost and lowest metal layers (see Fig. 18.20). The resistance of the topmost and lowest metal layers are, respectively, R_MT=r_MTl and R_M1=r_M1l, where r_MT and r₁ are the resistance per length and l is the distance of the current source from the TSV. The width of the power and ground lines on the topmost layer is 20 times wider than the minimum width. The width of the lowest metal layer is twice the minimum width. Consequently, for an industrial 0.18 μm CMOS technology with six metal layers, the resistance per unit length is r_M1=29.78r_MT and r_MT=4.62 Ω/mm. In addition, the resistance of a stack of vias between M6 and M1 is R_via=32.5 Ω [685].

Assuming that V_dd=1 volt and l=30 μm, the voltage drop at the current source, V_L for both circuits, is plotted in Fig. 18.22. The TSV is assumed to have a resistance of 1 Ω, including the resistance of a large number of parallel connected metal vias, and an inductance of L_TSV=20 pH [676]. The maximum switching frequency is f=10 GHz to consider the high frequency components of a digital signal. Additionally, the TSV resistance is larger than typically reported, depicting a worst case resistance for the TSV [147].

From Fig. 18.22, when the TSV path is exploited, a significantly larger current is supplied to the transistors without exceeding the allowed voltage ripple. Thus, for the circuit shown in Fig. 18.21B, the maximum voltage drop (V_dropmax=5%V_dd) is reached when I_Lmax=3.3 mA, while for the circuit that includes the TSV path, the maximum current that can be sustained is I_Lmax=9.4 mA; a considerable 2.8× increase.

Alternatively, the maximum distance of the current source from the TSV, where the circuit draws a fixed current, is plotted in Fig. 18.23. When the TSV path is considered, the current source can be placed farther from the power and ground pads or, equivalently, a smaller number of stacked vias can distribute the current within the circuit.

The difference in the voltage drop for a fixed current load of I_L=3 mA between the two circuits shown in Fig. 18.21 is significant for small distances and gradually decreases with increasing distance. For larger distances, on the order of millimeters, both circuits produce a similar voltage drop. This behavior can be explained by considering the current flow through the different paths that exist within the circuit shown in Fig. 18.21A. In this power distribution network, the current propagates through the low resistance TSV and M1, exhibiting a higher resistance as compared to M6. Alternatively, the current flows through the less resistive M6 as compared to M1 and the stacked vias, which in turn, is at least an order of magnitude more resistive than a single TSV.

For short distances (i.e., hundreds of micrometers), the path through the TSV and M1 (e.g., the TSV path) exhibits a lower impedance as compared to the path consisting of M6 and the stacked vias. Consequently, most of the current flows through the TSV path, resulting in a substantially smaller voltage drop as compared to the circuit shown in Fig. 18.21B. For the circuit shown in Fig. 18.21B, the greatest portion of the current flows through M6 and the stacked vias since the alternative path comprising M1 and stacked vias exhibits a considerably greater impedance.

As the distance between the current source and the TSV in the structure shown in Fig. 18.21A increases, the resistance along M1 also increases faster than the resistance of the path to M6. Beyond a specific distance, which depends on the impedance characteristics of the interconnects, the path that consists of M6 and a via stack exhibits a lower impedance than the path that includes M1 and the TSV. Beyond this distance, most of the current flows through M6 and, eventually, the voltage drop in both circuits is approximately the same.

This behavior, therefore, suggests that the TSV path within power and ground distribution networks has a local effect and is efficient for those transistors within a specific region around the TSV. This distance is determined by the current demand in the vicinity of the TSV and the interconnect impedance characteristics of the TSV and intratier metal layers.

These ancillary paths should not be perceived as another means to globally distribute power and ground within a 3-D circuit. These paths, however, can locally enhance the distribution of power within a circuit. Different ways exist to exploit this advantage. For example, the TSVs are a crucial element of a 3-D circuit as these interconnects provide intertier communication and power. The size of the TSVs, however, greatly increases routing congestion. To mitigate this issue, several stacked vias within the power grid in a region close to each TSV can be removed as most of the current flows through the TSV and M1. Alternatively, the intentional decoupling capacitance can be reduced since the voltage drop from the power supply to the transistors is considerably less.

18.3.1 Enhanced Power Integrity by Exploiting Through Silicon Via Paths

The effect of the TSV paths on the behavior of a power grid is explored in this subsection. Two pairs of 10 by 10 resistive metallic grids are used to model a portion of a power distribution network. Each pair corresponds to the topmost (i.e., M6) and lowest (i.e., M1) metal layer, which is depicted, respectively, in Figs. 18.24A and B. At each grid node other than the node in the middle, a stack of vias connects the two grids. At the center of the grids, a TSV connects to a power pad. The only difference between the two pairs of grids is that in one of the grids the TSV is connected to both M6 and M1 in addition to the power pad (i.e., the TSV path). Alternatively, in the other grid, the TSV is only connected to the power pad and M6, while the node at the center of the M6 and M1 grids is connected to a stack of intratier vias. The ground distribution network is similarly modeled.

Each stack of vias is modeled as a resistor, while the impedance of the TSV includes a resistive and an inductive component. The resistance and inductance are as assumed in Section 18.3. Specific nodes of the grid that model layer M1 are connected to a current source, as shown in Fig. 18.24B. Furthermore, a decoupling capacitor notated as C_dec is connected to each grid node, as illustrated in Fig. 18.24B. Each current source is modeled with a triangular waveform [686]. The rise and fall times are, respectively, 30 and 70 ps and the switching period is 100 ps. No intermediate quiet time between successive switching is therefore assumed. A voltage ripple of 5% of the power supply is assumed and V_dd=1 volt.

To demonstrate the effects of the low impedance path on the power grid formed by connecting the TSV to both M6 and M1, two different switching scenarios are considered. Initially, all of the sources shown in Fig. 18.24B draw current, while in the second scenario, only three sources switch. The length of the grid segments is notated by l and is varied to explore the resulting voltage drop.

For the first scenario, each current source draws a peak current of I_L=0.8 mA. In addition, the decoupling capacitors are removed to evaluate the voltage drop across the entire grid caused by switching the current sources. Both of the grids are simulated with SPICE.

The voltage drop at specific nodes of the M1 grid (including the node where the maximum voltage drop occurs) are plotted in Fig. 18.25 for increasing length l of the grid segment. These nodes are located at the upper left corner of the grid (S1), at a 4l distance to the right of the TSV (S2), and at the TSV (S3). The voltage drop at these nodes is illustrated in Fig. 18.25 by the curves denoted by, respectively, the circles, squares, and triangles. For the grid where the TSV path is present (depicted in Fig. 18.25 by the group of solid curves), the voltage drop is significantly lower as compared to the grid where the TSV path is not considered. Note that the voltage drop at the current source located at the upper left corner of the grid (S1) (i.e., the pair of curves denoted by the circles) is affected less by the TSV path as compared to the other two nodes. This situation demonstrates the locality of the effect caused by the TSV path.

A negligible increase (~5 mV) of the voltage at the TSV location is noted, as shown by the solid curve with increasing l. This counterintuitive behavior can be explained by considering the current that flows through the TSV path and the neighboring paths through the stacked vias. As l increases, the impedance of each M1 segment becomes comparable to the impedance of a stack of vias. Consequently, the current that flows through the TSV and M1 decreases. Alternatively, the current that flows through M6 to the TSV stacked vias increases. This change in the flow of current causes the voltage to increase at the TSV node with increasing l.

The decrease in the voltage drop due to the TSV path can be used to improve routability within a tier. This improvement is important since TSVs greatly increase routing congestion. To demonstrate that a smaller number of stacked vias within the power grid is required when the TSV path is considered, the stacked vias are removed within increasing radius from the TSV notated as d. The resulting voltage drop is depicted in Fig. 18.26 where l=30 μm. Note that fewer paths provide current to the transistors. Since the stacked vias are removed from the grid, the TSV path supports greater current. The voltage drop specification is therefore maintained up to d=3 or, equivalently, with 22% fewer intratier vias (see the dashed curves in Fig. 18.26).

The stacked vias are also removed from the grid when the TSV path is not present. The voltage drop on this grid is also shown in Fig. 18.26 by the solid curves. In this grid, the TSV is not connected to M1 and, consequently, the voltage drop rapidly increases as the stacked vias are removed to decrease routing congestion.

In the second scenario, only three sources switch. These three sources are located at the upper left corner of the grid (S1) and at the adjacent nodes (in the east and west direction) of the node where the TSV is connected (S2). The peak current of these sources is I_L=8 mA, while the rise and fall times are the same as in the previous scenario. The voltage drop at these current sources (i.e., S1, S2) and the center of the M1 grid (S3) is depicted in Fig. 18.27. The voltage drop within the two grids with (solid curves) and without (dashed curves) the TSV path is illustrated. The simulation results indicate that the additional path again decreases the voltage drop for this current source configuration. The locality of the TSV path is also demonstrated, since the voltage drop at the remote current source (S1) does not significantly change when the length of the grid segment is varied. Note the solid and dashed curves for S1 denoted by the circles in Fig. 18.27, which are practically indistinguishable.

These local power distribution paths can also decrease the extrinsic or intentional decoupling capacitance used to compensate for the voltage drop on the power grid. For the first scenario, the peak current of the sources is increased to I_L=1 mA, while the decoupling capacitors satisfy the voltage drop constraint. The decoupling capacitance is listed in Table 18.3 where the TSV path is both present and not present. The grid including the TSV path requires 25% less capacitance to satisfy the voltage drop constraint, an important savings in the area of a tier within a 3-D system.

Table 18.3

Minimum Node Voltage Across the Power Grids With and Without Considering the TSV Path

	Minimum Node Voltage (mV)
Total Decoupling Capacitance (nF)	With TSV Path	Without TSV Path
0.05	952	945
0.0625	956	952

18.3.2 Effect of Through Silicon Via Tapering on Power Distribution Networks

In all of the power delivery schemes presented in Section 18.1 and the models of 3-D power distribution networks discussed in Section 18.2, the TSVs contribute to the power supply noise along the vertical flow of current within a 3-D circuit. To lower the parasitic impedance of the TSV, one approach is to increase the number and/or diameter of the TSVs, which increases the area occupied by these interconnects. These approaches assume that the same number and size of TSVs are employed within each tier. This constraint is however a strict and inappropriate constraint as the overall current carried by the TSVs within each tier is not the same.

Those TSVs within the tiers closer to the package typically carry current drawn from all of the other tiers. The TSVs in the upper tiers closer to the heat sink carry an increasingly lower current (assuming all of the tiers are active). This behavior supports the use of a nonuniform radius for the TSVs across the 3-D stack. For those tiers closer to the package, the TSVs exhibit a greater diameter [673], as illustrated in Fig. 18.28A. Although uniform sizing can be applied to all of the TSVs, uniform sizing wastes silicon area in those tiers where the TSVs carry less current.

The TSVs, however, constitute primary paths for the flow of heat within 3-D circuits, as discussed in Chapter 12, Thermal Modeling and Analysis. By following this same approach, to resize the TSVs to ensure the efficient flow of heat throughout a 3-D stack, increasing TSV sizing occurs in the opposite direction as compared to sizing TSVs for controlling power supply noise [673]. The electrical and thermal networks are separately evaluated to determine the optimum TSV size to satisfy each of these objectives. From this evaluation, those sizes that satisfy both objectives (without being optima for each individual objective) are selected, as illustrated in Fig. 18.28B.

A Thevenin network is utilized to determine the TSV size, where the same current through each tier is assumed. The maximum TSV resistance for the minimum TSV radius allowed by the target fabrication process is also known. By sweeping the TSV radius (or by applying an optimization method), the optimal TSV size to satisfy voltage constraints and minimize the area of the TSVs is determined. In a similar manner, the size of the TSVs to satisfy the temperature constraints is determined where the thermal resistance is utilized in this case.

To demonstrate the effects of nonuniform sizes of the TSVs, an exemplary 3-D circuit with ten tiers is considered [673]. Two different sizing ratios are considered. In the first case, the tapering step is 2 μm (Case 1), while in the second case, the tapering step is 0.2 μm (Case 2). In both cases, a minimum radius of a TSV of 1 μm is assumed. To satisfy both the thermal and power supply noise objectives, the resulting radii of the TSVs for the two cases are: (1) R_9–10=9 μm, R_8–9=7 μm, R_7–8=5 μm, R_6–7=3 μm, R_5–6=1 μm, R_4–5=3 μm, R_3–4=5 μm, R_2–3=7 μm, and R_1–2=9 μm for the tapering step of 2 μm; (2) R_9–10=1.8 μm, R_8–9=1.6 μm, R_7–8=1.4 μm, R_6–7=1.2 μm, R_5–6=1 μm, R_4–5=1.2 μm, R_3–4=1.4 μm, R_2–3=1.6 μm, and R_1–2=1.8 μm for the tapering step of 0.2 μm.

Comparing these two cases with the case of uniform sizing across all of the tiers within this stack, the uniform TSVs yield a voltage drop of 90 mV for the TSV farthest from the package tier. For Case 1, the noise in the same tier is only 65 mV [673]. Furthermore, the noise in Case 1 is lower than in Case 2, demonstrating that a relatively small difference in TSV radius produces limited gains. The temperature also drops when a nonuniform radius is applied to the TSVs. Similarly, the temperature decreases from 43°C to 30°C for the tier located farthest from the heat sink if tapering is applied. The drop in temperature due to the use of nonuniform TSVs is considerable. In addition, a greater tapering step will further lower the temperature.

Another well known method to limit power supply noise is the use of decoupling capacitance. Techniques for allocating decoupling capacitance within 3-D circuits are discussed in the following section, where the contribution of a decoupling capacitance from neighboring tiers to decrease power supply noise in some other tier is described.

18.4 Decoupling Capacitance for Three-Dimensional Power Distribution Networks

Decoupling capacitors are an indispensable component at every level of the power distribution system. In on-chip power distribution networks, this capacitance is achieved by either a MOS capacitance or a MIM capacitance [325]. The typical difference between the two types of on-chip decoupling capacitances is a MOS capacitor provides a higher density capacitance at the expense of higher leakage current as compared to a MIM capacitor [687]. Trench decoupling capacitors can also be used as an alternative to reduce the leakage current of a MOS capacitance although this technology is fairly expensive [688]. Typical decoupling capacitors are efficient for a small distance from the switching load. This effective distance has been analyzed for 2-D systems [686]. For 3-D circuits, however, the decoupling capacitance of an adjacent tier can be located within a distance of tens of micrometers from the switching load due to the short and low resistive path of the TSVs. Allocation of the decoupling capacitance within a 3-D system should therefore consider the overall 3-D stack rather than individual tiers.

To explore the effects of the decoupling capacitance among the tiers, some simple cases are discussed based on the analytic model of power supply noise presented in Section 18.2. These systems consist of a varying number of tiers, where each tier is an Intel microprocessor manufactured in a 65 nm CMOS technology node [678]. Each tier comprises five circuit blocks with the same footprint and the same current density of 100 A/cm² [674]. All of the blocks switch simultaneously to produce the worst case power supply noise. The current waveform is a ramp function with a rise time of 0.7 ns.

The power network contains 43 power (ground) tracks between each pair of power (ground) pads. The resistance of a wire segment R_w in (18.8) is 0.22 Ω. The inductance of the package pins is 0.5 nH. The TSVs are 200 μm in height with a diameter of 50 μm. The effective inductance (one half of the loop inductance) for one TSV is determined from an EM solver as 0.06 nH. Finally, 20% of each tier is assumed to be available for the MOS decoupling capacitors.

Several scenarios illustrated in Fig. 18.29 are evaluated in terms of the worst case power supply noise. The 2-D system (single tier) exhibits the lowest noise, V_drop=182 mV, as shown in Fig. 18.29A. Stacking these tiers increases the noise in the topmost tier (farthest from the package pins) to 400 mV, as depicted in Fig. 18.29B. Adding a fifth tier as a decoupling capacitance tier adjacent to the package, as illustrated in Fig. 18.29C, decreases this noise by 22% to 312 mV. The rationale for placing this tier close to the package is to offer a low recharge time for the decoupling capacitance. The efficiency of the decoupling capacitance tier however is highest if this tier is placed on the top of the 3-D stack, as shown in Fig. 18.29D. In this case, the noise is 256 mV.

Although the noise decreases, this noise is considerably higher than in the single tier case. The use of a second tier as a decoupling capacitance is depicted in Fig. 18.30 to further lower the noise. As shown in Figs. 18.30B and C, interleaving the decoupling capacitance tiers with the processor tiers does not yield the lowest noise. Rather, placing both of these tiers on top of the stack, as illustrated in Fig. 18.30D, produces the lowest noise V_drop-3D=199 mV, which is much closer to the noise produced by a 2-D system.

In each of these scenarios, the decoupling capacitance is the same across each tier which may not be possible for several reasons. These reasons include, for example, the limited whitespace for the decoupling capacitance in each tier, the different technology nodes among the tiers, and the operating conditions of the circuits. A particular situation arises when the circuits in the adjacent tiers are power gated to save power. In these cases, the decoupling capacitance (intentional or intrinsic) from these tiers is no longer available since those transistors act as power switches that isolate this capacitance from the power distribution network of the overall system. This situation enhances the beneficial effects of the capacitance from the neighboring tiers. Specific topologies that overcome this variation in decoupling capacitance are discussed in the following subsection.

18.4.1 Decoupling Capacitance Topologies for Power Gated Three-Dimensional ICs

Power gating is a broadly used technique to greatly reduce the power of an integrated system. Those circuits that do not perform a task during a certain time are temporarily disconnected from the power supply to eliminate leakage and dynamic current. Large transistors, usually called “sleep transistors,” disconnect the power supply rails from the “virtual” power supply which is connected to the circuits [689]. A side effect of power gating is the decrease in the overall capacitance of the system. Consequently, the capacitance in these circuits cannot behave as decoupling capacitors and help alleviate abrupt current surges in adjacent circuits. This situation is more subtle in 3-D circuits for two reasons. First, due to the potentially greater power densities as compared to 2-D circuits, low power methods, such as power gating, may be applied more aggressively. Second, the short and low impedance vertical paths provided by the TSVs enable the capacitance of adjacent tiers to more effectively satisfy abrupt current demands within a tier.

Another aspect of power gating is the process of transitioning the power gated circuit to an operating state. If several circuits simultaneously transition to an active state, the sudden current demand can cause a significant dip in the power supply voltage. This voltage drop appears as power supply noise on nearby active circuits [690]. Considering these two issues, methodologies to effectively utilize decoupling capacitance in 3-D circuits are discussed in this subsection.

A topology that allows the decoupling capacitance to be utilized despite the circuit block being power gated is illustrated in Fig. 18.31 [691]. The primary difference from a standard power gated circuit is that the decoupling capacitor is connected both to the global voltage supply and to the virtual power rail through two switch transistors, which select one of the two power lines.

If transistor switch 2 is on and switch 1 is off, the decoupling capacitor is connected to the virtual V_dd. If the circuit is active, the sleep transistors are on, and the decoupling capacitor provides charge to the local circuit blocks, shown in Fig. 18.31, rather than to more distant circuits as the path to the V_dd rail is more resistive. Alternatively, if the circuit is power gated, switch 2 is off and switch 1 is on, the decoupling capacitor supplies charge to the other circuits, disconnecting the V_dd rail from the virtual power supply.

A tradeoff between the switch transistor and decoupling capacitor exists for this topology as the overall area overhead from these components should be as small as possible while satisfying any voltage constraints. Further increasing the decoupling capacitance is not useful as the area and, consequently, the on-resistance of the switch transistors is high, limiting the efficiency of the capacitor. Alternatively, if the switch transistor is large, lowering the impedance of the discharge path of the capacitor, the leakage current is greater. Therefore, choosing an appropriate size for these two components is required to achieve a decoupling capacitor system with the highest efficiency.

Another topology for connecting the decoupling capacitance is illustrated in Fig. 18.32, where the decoupling capacitor is directly connected to the V_dd rail. The capacitor provides sufficient charge to the adjacent circuits irrespective of whether the local circuit blocks are power gated. The discharge path for the local circuit blocks, however, includes the sleep transistor. Consequently, this topology can exhibit greater power supply noise as compared to the reconfigurable topology shown in Fig. 18.31. As the sleep transistors, however, are typically large (the equivalent transistor width is on the order of millimeters), the voltage drop across these devices is extremely small.

To evaluate the efficiency and explore tradeoffs between these two topologies, a power grid for a 3-D circuit with three tiers is considered. The topmost tier is connected to a package with C4 connections. Ten metal layers are used in this topology [693]. The top two layers are the global power grid, and layers 7 and 8 are the virtual grid. In addition, a via-last manufacturing process for the TSVs is assumed. The grid is 1 mm×1 mm. The segments of the power grid and the TSVs are modeled with multiple RLC π segments. The C4 connections are modeled as RL sections. Furthermore, the load consists of an inverter pair of different size distributed across the circuit. Finally, the voltage drop constraint is set to 5% of V_dd, 50 mV.

As the 3-D circuit includes three tiers, several scenarios with one or more active tiers are evaluated. These scenarios are listed in columns 1 to 3 of Table 18.4 where the maximum power supply noise for all of these scenarios is also listed. The decoupling capacitance ensures that the voltage constraint is satisfied for the standard topology with all tiers active (and, consequently, connected to global V_dd). As reported in Table 18.4, for the other scenarios where some tiers are power gated, the traditional topology violates the voltage constraint. This behavior is due to the lower decoupling capacitance available across the entire 3-D stack. Alternatively, both of the other topologies exhibit a considerably smaller power supply noise.

Table 18.4

Peak Voltage Noise for Different Scenarios of Activity Among the Three Tiers of a 3-D Circuit for the Standard, Reconfigurable, and Always On Topologies of Decoupling Capacitance [692]

Operating State of Tiers			Power Supply Noise of Decoupling Capacitance Topologies (mV)
Top Tier	Middle Tier	Bottom Tier	Standard	Reconfigurable		Always On
					Decrease		Decrease
On	On	On	50	50	–	50	–
On	Off	On	48.16	43.48	9.7%	43.40	9.9%
Off	Off	On	52.22	39.64	24.1%	38.07	27.1%
Off	On	On	48.55	44.50	8.3%	42.89	11.7%
Off	On	Off	52.51	38.78	26.1%	37.55	28.5%

Another important parameter that affects power noise in power gated circuits is the wake-up time of the inactive circuits, which affects the operation of the active systems. This behavior is common to both 2-D and 3-D circuits. A straightforward method to decrease the current demand during the wake-up process (the transition from the power gated to the operating state) is to slightly delay the turn-on time of the sleep transistors to ensure that the drawn current increases at a slower rate. A daisy chain of buffers is utilized for this approach, as illustrated in Fig. 18.33. The drawback of this approach, however, is the prolonged wake-up time of the circuit. To avoid this situation, a wake-up controller initiates the wake-up process in two steps, where a small number of sleep transistors is switched on, followed by the remaining transistors switching on [694]. The duration of each step is constant and is typically several clock cycles.

This two step method is also applicable to 3-D circuits; however, the situation is more complicated since the power supply noise exhibited on each tier strongly depends upon the location of the tier within the stack [695]. For 3-D stacks assuming that each tier is either active, inactive, or transitions to the active state, several cases exist where the power supply noise varies across all of the possible operating scenarios. Different wake-up times are therefore used between the two steps depending upon the tier that transitions to the active state and the tiers that are already active. This information is utilized to guide an adaptive wake-up controller, where the time duration of each step is carefully controlled [695]. The objective of this adaptive controller is to reduce the total wake-up time, while satisfying any power supply noise constraints.

This adaptive two step wake-up controller has been evaluated for a 3-D circuit with five tiers, where a 22 nm technology node is assumed. In the first step, 5% of the sleep transistors are switched on, whereas the remaining transistors are switched on during the second step. The duration of each step, however, is adjusted according to the operating conditions of the overall 3-D stack. A comparison of the efficiency of the wake-up controller is performed with both constant and adaptive steps. The adaptive controller exhibits an average decrease of 28% in the wake-up time of the 3-D stack, without violating the power supply noise constraint. Although not discussed here, the number of sleep transistors switched on between the two steps is another variable to control the wake-up time at the expense of a more highly complex controller.

18.5 Wire Sizing Methods in Three-Dimensional Power Distribution Networks

A straightforward approach to design a 3-D power distribution network is to independently generate a power network for each tier of the stack and connect these networks with TSVs. Unfortunately, this approach does not consider several traits of 3-D power distribution networks, leading to suboptimal networks that either do not satisfy the power supply noise constraints throughout the stack or results in overdesign, wasting vital interconnect and power resources.

As described in the previous sections of this chapter, the behavior of 3-D power distribution networks depends on the number and size of the TSVs, the TSV technology, and the decoupling capacitance of the adjacent tiers. These features are relevant only to 3-D circuits. Moreover, most case studies are based on simple assumptions. Although these assumptions are useful to understand the behavior of 3-D power distribution networks, more formal techniques are required.

Optimizing power distribution networks for 3-D systems requires consideration of several parameters in addition to the parameters of 2-D circuits, such as the size of the horizontal wires. Moreover, specific assumptions, such as uniform power dissipation for each tier should be relaxed to consider more practical cases. An algorithm which optimizes the area of the power network within each tier while simultaneously satisfying global power noise and thermal objectives throughout a 3-D system is presented in this section. Several other constraints are also added to the optimization process.

The power supply noise objective of the algorithm is

$V_{\mathrm{drop}}^i=\frac{V_{\mathrm{dropmax}}\mathrm{for}\mathrm{all}\mathrm{tiers}}{\mathrm{number}\mathrm{of}\mathrm{tiers}}-\frac{1}{g_{\mathrm{TSV}}^{i-1,i}}\sum _{j=1}^{\mathrm{top}\mathrm{tiers}}{I}_j-r_{\mathrm{int}}^i{I}_i,$ (18.44)

(18.44)

where V_dropmax for all tiers is the overall noise allowed across the system. The term $g_{\mathrm{TSV}}^{i-1,i}$ is the total conductance of all of the TSVs connecting tier i−1 to tier i (for i>1). The current flowing through each of these TSVs is denoted by I_j. Furthermore, the bonding style is face-to-back, which implies that the topmost global layer of a tier connects by TSVs to the bottommost local layer in the next tier. For this bonding approach, $r_{\mathrm{int}}^i$ notates the total impedance from all of the metal layers of the power network within each tier.

For the three tier circuit shown in Fig. 18.34, the corresponding constraints for the power supply noise based on (18.44) are [472]

$V_{\mathrm{drop}}^1=\frac{V_{\mathrm{dropmax}}\mathrm{for}\mathrm{all}\mathrm{tiers}}{3}-r_{\mathrm{int}}^1{I}_1,$ (18.45)

(18.45)

$V_{\mathrm{drop}}^2=\frac{V_{\mathrm{dropmax}}\mathrm{for}\mathrm{all}\mathrm{tiers}}{3}-\frac{1}{g_{\mathrm{TSV}}^{12}}\left(I_2+I_3\right)-r_{\mathrm{int}}^2{I}_2,$ (18.46)

(18.46)

and

$V_{\mathrm{drop}}^3=\frac{V_{\mathrm{dropmax}}\mathrm{for}\mathrm{all}\mathrm{tiers}}{3}-\frac{1}{g_{\mathrm{TSV}}^{23}}{I}_3-r_{\mathrm{int}}^3{I}_3,$ (18.47)

(18.47)

where the term relating to the resistive voltage drop of the TSVs is not included in (18.45) since this tier is the bottommost tier connected to the package.

An expression for the temperature constraint is similar to (18.44) based on the electro-thermal duality, and is [472]

$T_{\max }^i=\frac{\max {\mathrm{\Delta }T}_{\mathrm{between}\mathrm{tiers}}}{\mathrm{number}\mathrm{of}\mathrm{tiers}}-\frac{1}{g_{\mathrm{TSV}}^{i-1,i}}\sum _j^{\mathrm{bottom}\mathrm{tiers}}{Q}_j-r_{\mathrm{thint}}^i{Q}_i,$ (18.48)

(18.48)

where max_ΔT_{between tiers} is the maximum allowed temperature difference between the uppermost and bottom tiers. The term $g_{\mathrm{TSV}}^{i-1,i}$ denotes the total thermal resistance of all of the TSVs connecting two adjacent tiers. The heat produced within a tier i is notated as Q_i. These constraints for the power supply noise and temperature, respectively, facilitate the analysis of the optimization problem as the size of the power grid and TSVs of each tier are treated separately. Satisfaction of these constraints (see, for example (18.44)) ensures that the noise and temperature limits are maintained across the entire 3-D stack.

With these constraints and utilizing the electro-thermal model presented in Section 18.2.1 to determine the temperature and voltage at any node within the power distribution network of a 3-D circuit, the problem of optimizing resources in these networks is stated as follows. Minimize the cost function,

$\sum \beta w_{\mathrm{track}}+\sum (1-\beta )D_{\mathrm{TSV}},$ (18.49)

(18.49)

to ensure that the following constraints are satisfied [472]:

(C1) for the voltage of the node q in tier i (see (18.34) and (18.44)),

$V_q^i\ge V_{\mathit{dd}}-V_{\mathrm{drop}}^i,$ (18.50)

(18.50)

(C2) for the voltage of the node q in tier i (see (18.41) and (18.48)),

$T_q^i\le T_{\mathrm{amb}}+T_{\max }^i,$ (18.51)

(18.51)

(C3) for the width of the power and ground lines,

$w_{\min }\le w\le w_{\max },$ (18.52)

(18.52)

(C4) for the diameter of the TSVs,

$D_{\min }^{*}\le D\le D_{\max },$ (18.53)

(18.53)

(C5) for ensuring reliability, an electromigration constraint can be added (see (18.36)) where

$J_{q-j}^i\le J_{\max },$ (18.54)

(18.54)

and (C6) is a constraint that emphasizes either the voltage drop or the temperature objective. The weighted function is

$a·V_q^i+\left(1-a\right)T_q^i.$ (18.55)

(18.55)

In the cost function (18.49), w_track is the width of the horizontal wire tracks within the power distribution network within each tier, and D_TSV is the diameter of the TSVs within each tier. Note that the TSVs at different tiers can have different diameters but the TSVs within a tier are all uniformly sized. The coefficient β is a weighting factor to determine the significance of each term in (18.49). The overall optimization process is illustrated in Fig. 18.35. Since the tiers towards the middle of the stack are more sensitive to power supply noise and thermal issues, the TSV sizing process is initially applied only to these tiers, as shown in Fig. 18.35A [472]. The resulting TSV diameter for these tiers is a lower bound for the other tiers, denoted as D*_min (see C4). Note also that in step 4 of the algorithm depicted in Fig. 18.35C, the objectives O_Vqdrop and O_Tq are dimensionless. If any of these objectives is equal to unity, the maximum allowed voltage drop or temperature has been achieved.

Per the cost function given by (18.49), the algorithm minimizes the area of the horizontal and vertical wires while simultaneously satisfying the objectives, O_Vqdrop and O_Tq. The diameter of the TSVs has a lower bound that is not set by the specifications of the technology but rather from the TSV diameter in the middle tiers D*_min. In the flowchart depicted in Fig. 18.35B, the width of each horizontal wire within the power network of a tier is successively reduced, ensuring constraints C1 to C6 are not violated. This procedure is also applied to the TSVs and is iterated across all of the tiers. The algorithm terminates when any horizontal wire or TSVs within a tier can no longer be decreased without violating constraints C1 to C6.

This optimization algorithm is applied to a 3-D circuit with three tiers where the allowed voltage drop is 100 mV (10% of V_dd) and the allowed temperature difference between the two extreme tiers is 10°C. The ambient temperature is assumed to be 27°C. To demonstrate the effects of parameter a, the power density is set the same for all tiers. The applied power density in this case is 0.6 μW/μm². If temperature is emphasized (a=0), the savings in area reaches 43%. If supply noise is the primary focus (a=1), the savings in area reaches 55%. For equally important voltage drop and temperature constraints (a=0.5), the savings in area is 53%. The greatest savings in area is produced for a=0.9.

The algorithm is also evaluated for several power densities to reflect different levels of power dissipation among tiers. The following power densities are considered: (1) 1.5 μW/μm² as the high power density, (2) 1 μW/μm² as the medium power density, and (3) 0.8 μW/μm² as the low power density. For β=1 and a=0.5, the area savings for the different cases of power densities are reported in Table 18.5. In columns 3 and 5, the listed objectives correspond to the use of w_max for all metal layers within the power distribution network. In columns 4 and 6, the same objectives are reported where the optimization algorithm is applied.

In all of the reported cases, the algorithm produces a wire size that satisfies the voltage drop target, while the temperature is considerably less than originally specified. This situation indicates that the wires can be further decreased in size without violating the maximum temperature constraint. Any further decrease in size will however violate the voltage drop constraint. The resulting gains in area, however, are considerable, reaching 41%.

18.6 Summary

The behavior and related models and design issues for 3-D power distribution systems are discussed in this chapter. The primary concepts are summarized below: