Extension of the Proposed Model to Include Variations of Wires

The model described in Section 17.2 can be extended to include variations in the horizontal wires. This extended model is presented in this appendix. Consider the 3-D clock tree shown in Fig. 17.8, where the delay variations of a buffer stage Δd_stage(i) include the variations due to the capacitance ΔC_int and resistance ΔR_int of the wires,

$\begin{array}{ll}\mathrm{\Delta }{d}_{\mathrm{stage}(i)}\hfill & =\mathrm{\Delta }{d}_i+0.69\left({R\prime }_{b(i)}+\mathrm{\Delta }{R}_{b(i)}\right)\mathrm{\Delta }{C}_{\mathrm{int}}+0.38\left({R\prime }_{\mathrm{int}}\mathrm{\Delta }{C}_{\mathrm{int}}+\mathrm{\Delta }{R}_{\mathrm{int}}{C\prime }_{\mathrm{int}}+\mathrm{\Delta }{R}_{\mathrm{int}}\mathrm{\Delta }{C}_{\mathrm{int}}\right)\\ & +0.69\left({R\prime }_{\mathrm{int}}\mathrm{\Delta }{C}_{b(i+1)}+\mathrm{\Delta }{R}_{\mathrm{int}}{C\prime }_{b(i+1)}+\mathrm{\Delta }{R}_{\mathrm{int}}\mathrm{\Delta }{C}_{b(i+1)}\right).\hfill \end{array}$ (F.1)

(F.1)

According to the definition of $\mathrm{\Delta }{d}_i$ in (17.24), the term $0.69{R\prime }_{\mathrm{int}}\left(\mathrm{\Delta }{C}_{b\left(i+1\right)}\right)$ is included in Δd_i+1. Consequently, Δd_stage(i) is rewritten as

$\begin{array}{ll}\mathrm{\Delta }{d}_{\text{stage}(i)}\hfill & =\mathrm{\Delta }{d}_i+0.69\left({R\prime }_{b(i)}+\mathrm{\Delta }{R}_{b(i)}\right)\mathrm{\Delta }{C}_{\mathrm{int}}+0.38\left({R\prime }_{\mathrm{int}}\mathrm{\Delta }{C}_{\mathrm{int}}+\mathrm{\Delta }{R}_{\mathrm{int}}{C\prime }_{\mathrm{int}}+\mathrm{\Delta }{R}_{\mathrm{int}}\mathrm{\Delta }{C}_{\mathrm{int}}\right)\\ & +0.69\left(\mathrm{\Delta }{R}_{\mathrm{int}}{C\prime }_{b(i+1)}+\mathrm{\Delta }{R}_{\mathrm{int}}\mathrm{\Delta }{C}_{b(i+1)}\right)=\mathrm{\Delta }{d}_i+\mathrm{\Delta }{d}_{\mathrm{int}(i)},\hfill \end{array}$ (F.2)

(F.2)

where delay variations due to the wires are denoted by Δd_int(i).

As discussed in [637], since the variations of the characteristics of the metal wires are relatively low as compared with nominal values, the variations of the wire delay can be approximated by a first order Taylor series expansion without significant loss of accuracy. Similar to (17.26), Δd_int(i) can be approximated as

$d_{\mathrm{int}(i)}\approx \sum _{p_j\in \overrightarrow{P}}\left({\left[\frac{\partial \mathrm{\Delta }{d}_{\mathrm{int}(i)}}{\partial R_{\mathrm{int}}}\frac{\partial \mathrm{\Delta }{R}_{\mathrm{int}}}{\partial p_j}\right]}_0\mathrm{\Delta }{p}_j+{\left[\frac{\partial \mathrm{\Delta }{d}_{\mathrm{int}(i)}}{\partial {\mathrm{C}}_{\mathrm{int}}}\frac{\partial \mathrm{\Delta }{C}_{\mathrm{int}}}{\partial p_j}\right]}_0\mathrm{\Delta }{p}_j\right),$ (F.3)

(F.3)

where p_j is the j^th parameter of the wire, and P is the vector of the parameters of those wires affected by process variations. For example, consider the variations in the width and thickness of the metal and the thickness of the ILD [637,638], P(W_int, h_int, t_ILD). Assuming these parameters are modeled by a Gaussian distribution and are independent of each other [637], the distribution of Δd_int(i) can be approximated by a Gaussian distribution,

$\mathrm{\Delta }{d}_{\mathrm{int}(i)}~\mathcal{N}\left(0,{\sigma }_{\mathrm{dint}\left(i\right)}^2\right),$ (F.4)

(F.4)

${\sigma }_{\mathrm{dint}(i)}^2=\sum _{p_j\in \overrightarrow{P}}{\left({\left[\frac{\partial \mathrm{\Delta }{d}_{\mathrm{int}(i)}}{\partial R_{int}}\frac{\partial \mathrm{\Delta }{R}_{\mathrm{int}}}{\partial p_j}\right]}_0+{\left[\frac{\partial \mathrm{\Delta }{d}_{\mathrm{int}(i)}}{\partial C_{\mathrm{int}}}\frac{\partial \mathrm{\Delta }{C}_{\mathrm{int}}}{\partial p_j}\right]}_0\right)}^2{\sigma }_{p_j}^2,$ (F.5)

(F.5)

$R_{\mathrm{int}}=\frac{\rho l}{h_{\mathrm{int}}{W}_{\mathrm{int}}},$ (F.6)

(F.6)

$C_{\mathrm{int}}=2\left(C_g+C_c\right)l,$ (F.7)

(F.7)

where ρ, l, h_int, and W_int are, respectively, the resistivity, length, thickness, and width of the interconnect, C_g includes both the ground and fringe capacitance, and C_c is the coupling capacitance. Expressions of C_g and C_c are available, respectively, in [252] and [766].

Considering the delay variations caused by both the clock buffers and wires in (F.2), the skew variations Δs_u,v includes two terms,

$\mathrm{\Delta }{s}_{u,v}=\mathrm{\Delta }{s}_{b(u,v)}+\mathrm{\Delta }{s}_{\mathrm{int}(u,v)}.$ (F.8)

(F.8)

The distribution of Δs_b(u,v) is obtained from (17.24)–(17.45). The distribution of Δs_int(u,v) is obtained from (17.30)–(17.45) by substituting Δd_int(i) for Δd_i. Consequently, Δs_u,v can be described by a Gaussian distribution,

$\mathrm{\Delta }{s}_{u,v}~\mathcal{N}\left(0,{\sigma }_{s_{b\left(u,v\right)}}^2+{\sigma }_{s_{\mathrm{int}\left(u,v\right)}}^2\right).$ (F.9)

(F.9)

The extended model is compared with Monte Carlo simulations including the variations of r_int and c_int in a π interconnect model. Based on the parameters in [637], the nominal value and standard deviation of the parameters of the wires are listed in Table F.1. The multi-via and single via trees described in Section 17.2 are used to verify the accuracy of the extended model. The results for the independent WID variations are reported in Table F.2, where the accuracy of the model including variations in the wires is reasonably high (<8% for a multi-via clock network topology).