26.3.1 Inverting Op-Amp with Noninverting Positive Reference

The ideal transfer equation is given in Equation 26.4

(26.4)

The transfer equation for this circuit (Figure 26.5) takes the form of Y = –mX + b. The transfer function slope is negative, and the DC intercept is positive. R_F and R_G are contained in both halves of the equation, thus it is hard to obtain the desired slope and DC intercept without modifying V_REF. This is the minimum component count configuration for this transfer function. When the reference voltage is 0, the input voltage is constrained to negative voltages because positive input voltages would cause the output voltage to saturate at ground.

26.3.2 Inverting Op-Amp with Inverting Negative Reference

The transfer equation takes the form of Y = –mX + b and is given in Equation 26.5

(26.5)

The transfer function slope is negative, and the DC intercept is positive (Figure 26.6). R_G1 and R_G2 are contained in the equation, thus it is easy to obtain the desired slope and DC intercept by adjusting the value of both resistors. Because of the virtual ground at the inverting input, R_G2 is the terminating impedance for V_REF. When the reference voltage is 0, the input voltage is constrained to negative voltages because positive input voltages would cause the output voltage to saturate at ground.

26.3.3 Inverting Op-Amp with Noninverting Negative Reference

The transfer equation takes the form of Y = −mX − b and is given in Equation 26.6

(26.6)

The transfer function slope is negative, and the DC intercept is negative. R_F and R_G are contained in both halves of the equation, thus it is hard to obtain the desired slope and DC intercept without modifying V_REF. This is the minimum component count configuration for this transfer function. The slope and DC intercept terms in Equation 26.6 are both negative, hence, unless the correct input voltage range is selected, the output voltage will saturate at ground. The negative input voltage must be limited to less than −400 mV because op-amp inputs either break down or have protection circuits that forward bias when large negative voltages are applied to the inputs.

26.3.4 Inverting Op-Amp with Inverting Positive Reference

The transfer equation takes the form of Y = −mX − b and is given in Equation 26.7

(26.7)

The transfer function slope is negative, and the DC intercept is negative. R_G1 and R_G2 are contained in the equation, thus it is easy to obtain the desired slope and DC intercept by adjusting the value of both resistors. Because of the virtual ground at the inverting input, R_G2 is the terminating impedance for V_REF. The slope and DC intercept terms in Equation 26.7 are both negative, hence, unless the correct input voltage range is selected, the output voltage will saturate.

26.3.5 Noninverting Op-Amp with Inverting Positive Reference

The transfer equation takes the form of Y = mX – b and is given in Equation 26.8

(26.8)

The transfer function slope is positive, and the DC intercept is negative. This is the minimum component count configuration for this transfer function. The reference termination resistor is connected to a virtual ground, so R_G is the load across V_REF. R_F and R_G are contained in both halves of the equation, thus it is hard to obtain the desired slope and DC intercept without modifying V_REF or placing an attenuator in series with V_IN.

26.3.6 Noninverting Op-Amp with Noninverting Negative Reference

The transfer equation takes the form of Y = mX – b and is given in Equation 26.9.

(26.9)

The transfer function slope is positive, and the DC intercept is negative. The reference is terminated in R₁ and R₂. R₁ and R₂ can be selected independent of R_F and R_G to obtain the desired slope and DC intercept. The price for the extra degree of freedom is two resistors.

26.3.7 Noninverting Op-Amp with Inverting Negative Reference

The transfer equation takes the form of Y = mX + b and is given in Equation 26.10

(26.10)

The transfer function slope is positive, and the DC intercept is positive. This is the minimum component count configuration for this transfer function. The reference termination resistor is connected to a virtual ground, so R_G is the load across V_REF. R_F and R_G are contained in both halves of the equation. Thus, it is hard to obtain the desired slope and DC intercept without modifying V_REF or placing an attenuator in series with V_IN.

26.3.8 Noninverting Op-Amp with Noninverting Positive Reference

The transfer equation takes the form of Y = mX + b and is given in Equation 26.11

(26.11)

The transfer function slope is positive, and the DC intercept is positive. The reference is terminated in R₁ and R₂. R₁ and R₂ can be selected independent of R_F and R_G to obtain the desired slope and DC intercept. The price for the extra degree of freedom is two resistors.

26.3.9 Differential Amplifier

When R_F is set equal to R₂ and R_G is set equal to R_1, Equation 26.12 reduces to Equation 26.13

(26.12)

(26.13)

These resistors must be matched very closely to obtain good differential performance. The mismatch error in these resistors reduces the common-mode performance, and the mismatch shows up in the output as an amplified common-mode voltage.

Consider Equation 26.13 Note that only the difference signal is amplified, thus this configuration is called a differential amplifier. The differential amplifier is a popular circuit in precision applications where it is used to amplify sensor outputs while rejecting common-mode noise.

The inverting input impedance is R_G because of the virtual ground at the inverting op-amp input. The noninverting input impedance is R_F + R_G because the noninverting op-amp input impedance approaches infinity. The two input impedances are different, and this leads to two problems with this circuit.

First, mismatched input impedances preclude any attempts to cancel input bias currents through resistor matching. Often R₂ is set equal to R_F || R_G so that the bias currents develop equal common-mode voltages which the op-amp rejects. This is not possible when R₂ = R_F and R₁ = R_G unless the source impedances are matched. Second, high output impedance sensors are often used, and when high output sensors work into mismatched input impedances, errors occur.

26.3.10 Differential Amplifier with Bias Correction

When R_F is set equal to R₂ and R_G is set equal to R₁, Equation 26.14 reduces to Equation 26.15

(26.14)

(26.15)

When an offset voltage must be eliminated from or added to the input signal, this differential amplifier circuit is employed. The reference voltage can be positive or negative depending upon the polarity offset required, but care must be taken to protect the op-amp inputs and not exceed the output range.

26.3.11 High Input Impedance Differential Amplifier

When R_F is set equal to R₁ and R_G is set equal to R₂, Equation 26.16 reduces to Equation 26.17

(26.16)

(26.17)

Each input signal is connected to an op-amp noninverting input that is very high impedance. The input impedance of the circuit is very high, and it is matched, so this circuit is often used to interface to high-impedance sensors. Each op-amp has a signal propagation time, and V_IN1 experiences two propagation delays versus V_IN2’s one propagation delay. At high frequencies, the propagation delay becomes a significant portion of the signal period, and this configuration is not usable at that frequency.

R_F and R₂, and R_G and R₁ should be matched to achieve good common-mode rejection capability. Bias current cancellation resistors equal to R_F || R_G should be connected in series with the input sources for precision applications.

26.3.12 High Common-Mode Range Differential Amplifier

When all resistors are equal, Equation 26.18 reduces to Equation 26.19

(26.18)

(26.19)

R₁ and R_G2 are equal-value resistors terminated into a virtual ground; hence, the input sources are equally terminated. This configuration has high common-mode capability because R₁ and R_G2 limit the current that can flow into or out of the op-amp. Thus, the input voltage can rise to any value that does not exceed the op-amp’s drive capability. The voltage references, V_REF1 and V_REF2, are added for bias purposes. Without bias, the output voltage of the op-amps would saturate at ground, and the bias voltages keep the output voltage of the op-amp positive.

26.3.13 High-Precision Differential Amplifier

When R₇ = R₆, R₅ = R₂, R₁ = R₄, and V_REF1 = V_REF2, Equation 26.20 reduces to Equation 26.21

(26.20)

(26.21)

In this circuit configuration, both sources work into the input impedance of a noninverting op-amp. This impedance is very high, and if the op-amps are identical, both impedances are very nearly equal. The propagation delay is still equal to two op-amp propagation delays, but the propagation delay is very nearly equal, so any distortion resulting from unequal propagation delays is minimized.

The equal resistors should be matched with more precision than is expected from the circuit. Resistor matching eliminates distortion due to unequal gains, and it reduces the common-mode voltage feed through. Resistors equal to (R₁ || R₃)/2 may be placed in series with the sources to reduce errors resulting from bias currents. This differential amplifier has the unique feature that the gain can be changed with only one resistor, and if the gain setting resistor is R₃, no resistor matching is required to change gain.

26.3.14 Simplified High-Precision Differential Amplifier

When RF is set equal to R2, RG is set equal to R1, and VREF1 = VREF2, Equation 26.22 reduces to Equation 26.23

(26.22)

(26.23)

Both input sources are loaded equally with very high impedances in the simplified high precision differential amplifier. This configuration eliminates three resistors, two of which are matched, but it sacrifices flexibility in gain setting capability because the gain must be set with a matched pair of resistors.

26.3.15 Variable Gain Differential Amplifier

When R₁ is set equal to R₃ and R₂ is set equal to R₄, Equation 26.24 reduces to Equation 26.25

(26.24)

(26.25)

When a function is enclosed in a feedback loop, the function acts inverted on the closed loop transfer function. Thus, the gain stage R_F/R_G ends up being an attenuator. The circuit shown in Figure 26.19 can be used with any of the differential amplifiers to change gain without affecting matched resistors. R₁, R₃ and R₂, R₄ must be matched to reduce the common-mode voltage.

26.3.16 T Network in the Feedback Loop

Sometimes it is desirable to have a low-resistance path to ground in the feedback loop. Standard inverting op-amps cannot do this when the driving circuit sets the input resistor value and the gain specification sets the feedback resistor value. Inserting a T network in the feedback loop yields a degree of freedom that enables both specifications to be met with a low DC resistance path to ground in the feedback loop.

(26.26)

26.3.17 Buffer

The buffer input signal polarity must be unipolar because the output voltage swing is unipolar. When this limitation precludes the buffer, a differential amplifier with the negative input correctly biased is used, or a reference voltage is added to the buffer to offset the output voltage. R_F must be included when the op-amp inputs are not rated for the full supply voltage. In that case, R_F limits the current into the op-amp inputs, thus preventing latch up. Most new op-amp inputs can withstand the full supply voltage, so they often leave R_F out as cost savings. The main attraction of the buffer is that it has very high input impedance and very low output impedance. The impedance transformation capability is why buffers are often added to the input of other circuits.

(26.27)

26.3.18 Inverting AC Amplifier

V_CC and resistors R set a DC level of V_CC/2 at the inverting input. R_G is connected to ground through a capacitor, thus the circuit functions as a buffer for DC. This causes the DC output voltage to be V_CC/2, so the quiescent output voltage is the middle of the supply voltage, and it is ready to swing to either rail as the input signal commands.

The AC gain is given in Equation 26.28 R_G and C form a coupling network for the AC signal. Good coupling networks should be constant low impedance at the signal frequencies, so Equation 26.29 should be satisfied to get good low-frequency performance. The lowest frequency component of the input signal, f_MIN, is determined by completing a Fourier series on the input signal. Then, setting f_MIN = 100f in Equation 26.29 ensures that the 3-dB breakpoint introduced by R_G and C is two decades lower than f_MAX.

(26.28)

(26.29)

26.3.19 Noninverting AC Amplifier

V_CC and the resistors (R) set a DC level of V_CC/2 at the inverting input. R_G is connected to ground through a capacitor, thus the circuit functions as a buffer for DC. This causes the DC output voltage to be V_CC/2, so the quiescent output voltage is the middle of the supply voltage, and it is ready to swing to either rail as the input signal commands.

The AC gain is given in Equation 26.30 R_G and C create a coupling network for the AC signal. Good coupling networks should be a constant low impedance at the signal frequencies, so Equation 26.31 should be satisfied to get good low frequency performance. The lowest frequency component of the input signal, f_MIN, is determined by completing a Fourier series on the input signal. Then, setting f_MIN = 100f in Equation 26.31 ensures that the 3-dB breakpoint introduced by R_G and C is two decades lower than f_MAX. The breakpoint for R_G and C₁ is set in a similar manner.

(26.30)

(26.31)

26.4.1 Inverting Summer

The three input voltages are inverted and added as Equation 26.32 shows. R_B should be made equal in value to the parallel combination of R_F, R_G1, R_G2, and R_G3 to convert the input bias current to a common-mode voltage so the op-amp can reject it. V_REF sets the output voltage somewhere between the supply limits, and this allows negative addition (subtraction) to take place.

(26.32)

26.4.2 Noninverting Summer

This circuit adds the input voltages and multiplies them by the stage gain. R_G1, R_G2, and R_G3 in parallel should be equal to R_F in parallel with R_G to cancel the input bias current using the common-mode input voltage rejection technique. VREF is added to the circuit to enable the addition of negative values.

(26.33)

26.4.3 Noninverting Summer with Buffers

V_REF1 and V_REF2 are added to enable the buffers to handle positive input voltages. Their output contribution to the last stage is cancelled out by V_REF3. This configuration uses fewer resistors at the expense of two op-amps. R_G1, R_G2, and RF in parallel should be made equal to R_B to cancel the input bias current.

(26.34)

26.4.4 Inverting Integrator

The Laplace operator, s = jω, is used in Equation 26.35, and the mathematical operation 1/s constitutes an integration. Differentiation circuits are shown later, and the mathematical operation, s, constitutes a differentiation. The integration time constant is RC, thus the magnitude crosses 0 dB on a log plot when RC = 1. Also the phase is −45° when RC = 1.

(26.35)

This integrator is not very practical because there is no method of discharging the capacitor; hence, any leakage current will eventually charge the capacitor until the circuit becomes saturated. The positive input of the integrator is biased at V_CC/2 to center the output voltage at V_CC/2; thus allowing for positive and negative voltage swings. The bias resistors are selected as 2R so that the parallel combination equals R. This offsets the input current drawn through R.

26.4.5 Inverting Integrator with Input Current Compensation

Functionally, this circuit is the same as that shown in Figure 26.27, but a current compensation network has been added to offset the input current. V_CC, R₁, and R₂ bias the positive input at V_CC/2 to center the output voltage at V_CC/2; thus allowing for positive and negative voltage swings.

R₁ and R₂ are selected as relatively small values because the current flowing through R_A also flows through the parallel combination of R₁ and R₂. R_A forward biases the diode with a constant current, thus the diode acts like a small voltage regulator. The diode voltage drop is temperature sensitive, and this factor works in our favor because the input transistors are temperature sensitive. The two temperature sensitivities cancel out if the diode current is selected correctly. R_B is a large-value resistor that acts like a current source, so it is selected such that it supplies the input bias current. Selecting R_B correctly ensures that no input current flows through the integration resistor, R.

This integrator is not very practical because there is no method of discharging the capacitor. Hence, any input current will eventually charge the capacitor until the circuit becomes saturated. The bias circuit drastically reduces the input current flowing through R, thus it extends the integration time. A reset circuit is needed to make the integrator more practical.

This bias compensation scheme is set up for an op-amp that has NPN input transistors. The diode must be reversed and connected to ground for op-amps with PNP input circuits.

(26.36)

26.4.6 Inverting Integrator with Drift Compensation

Functionally, this circuit is the same as that shown in Figure 26.27, but it uses an RC circuit in the positive lead to obtain drift compensation. The voltage divider is made from a series string of resistors (R_A), and VCC biases the input in the center of the power supply.

Positive input current flows through R and C in parallel, so the positive input current drops the same voltage across the parallel RC combination as the negative input current drops across its series RC combination. The common-mode rejection capability of the op-amp rejects the voltages caused by the input currents. Much longer integration times can be achieved with this circuit, but when the input signal does not center around V_CC/2, the compensation is poor.

(26.37)

26.4.7 Inverting Integrator with Mechanical Reset

Functionally, this circuit is the same as that shown in Figure 26.27, but a method has been provided to discharge (reset) the capacitor. S₁ is a mechanical switch or relay and when the contacts close, they short the integrating capacitor forcing it to discharge. Some capacitors are sensitive to fast discharge cycles, so R_S is put in the discharge path to limit the initial discharge current. When R_S is absent from the circuit, the impulse of current that occurs at the first instant of discharge causes considerable noise, so the selection of R_S is also based on noise considerations. For all practical purposes, the time constant formed by R_S and C determines the discharge rate.

One advantage of mechanical discharge methods is that they are isolated from the remainder of the circuit. Their size, weight, time delay, and uncertain actuating time offset this advantage. When the disadvantages of mechanical reset outweigh the advantages, circuit designers go to electronic reset circuits.

(26.38)

26.4.8 Inverting Integrator with Electronic Reset

Functionally, this circuit is the same as that shown in Figure 26.27, but an electronic method has been provided to discharge (reset) the capacitor. Q₁ is controlled by a gate drive signal that changes its state from on to off. When Q₁ is on, the gate-source resistance is low, less than 100Ω. And when Q₁ is off, the gate-source resistance is high—about several hundred MΩ.

The source of the FET is at the inverting lead that is at ground, so the Q₁ gate-source bias is not affected by the input signal. Sometimes, the output signal can get large enough to cause leakage currents in Q₁, so the designer must take care to bias Q₁ correctly. Consult a transistor book for more detailed information on transistor reset circuits. A major problem with electronic reset is the charge injected through the transistor’s stray capacitance. This charge can be large enough to cause integration errors.

(26.39)

26.4.9 Inverting Integrator with Resistive Reset

This circuit differs from that shown in Figure 26.27 because it yields a breakpoint rather than a pure integration. On a log plot, the integrator slope is −6 dB per octave at the 0 frequency intercept, and the 0 dB intercept occurs when f = 1/2πRC. A breakpoint plots flat on a log plot until the breakpoint where it breaks down at −6 dB per octave. It is −3 dB when f = 1/2πRC.

R_F is in parallel with the integrating capacitor, C, so it is continually discharging C. The low frequency attenuation that is the best attribute of the pure integrator is sacrificed for the reset circuit complexity:

(26.40)

26.4.10 Noninverting Integrator with Inverting Buffer

This circuit is an inverting integrator preceded by an inverting buffer. Eliminating the signal inversion costs an op-amp and four resistors, but this is the easiest way to get true noninverting integrator performance.

(26.41)

26.4.11 Noninverting Integrator Approximation

This circuit has fewer parts than the Noninverting Integrator with Inverting Buffer (Figure 26.33), but it is not a true integrator because there is a zero in the transfer equation. The log plot starts rolling off at a −6 dB per octave rate at low frequencies, but when f = 1/2πRC, the zero cuts in. The zero causes the log plot to flatten out because the slope decreases to 0 db per decade.

This circuit functions as an integrator at very low frequencies, but at frequencies higher than f = 1/2πRC, it functions as a buffer.

(26.42)

26.4.12 Inverting Differentiator

The log plot of the differentiator is a positive slope of 6-dB per octave passing through 0 dB at f = 1/2πRC. At extremely high frequencies, the capacitive reactance goes to very low values, thus the circuit gain approaches the op-amp open-loop gain. This performance emphasizes any system noise or noise generated by the op-amp. The poor noise performance of this circuit limits its application to a very few specialized situations.

This configuration has a pole in the feedback loop. If the op-amp has more than one pole, and most op-amps have several poles, this configuration can become oscillatory. The V_CC and R_A circuit bias the output in the center of the power supplies. R_A/2 should be selected equal to RG||RF so that input currents are canceled out.

(26.43)

26.4.13 Inverting Differentiator with Noise Filter

This circuit has a pure differentiator that rises at a 6-dB per octave slope from zero frequency. At f = 1/2πR_FC_F, the pole kicks in and the slope is reduced to zero. The pole has two effects. First, it stabilizes the circuit by canceling zero’s phase shift. Second, it limits the circuit gain to 1 at high frequencies, so it acts like a noise filter.

R/2 should equal R_F for good input current cancellation, and V_CC coupled with R centers the output voltage.

(26.44)

26.5.1 Basic Wien Bridge Oscillator

When ω = 2πf = 1/RC, the feedback is in phase (this is positive feedback), and the gain is 1/3, so oscillation requires an amplifier with a gain of 3. When R_F = 2R_G the amplifier gain is 3 and oscillation occurs at f = 1/2πRC. Normally, the gain is larger than 3 to ensure oscillation under worst case conditions.

V_REF sets the output DC voltage in the center of the span.

The output sine wave is highly distorted because limiting by saturation and cut-off is controlling the output voltage excursion. The distortion decreases when the gain is decreased, but the circuit may not oscillate under worst-case low gain conditions.

(26.45)

26.5.2 Wien Bridge Oscillator with Nonlinear Feedback

When the circuit gain is 3, R_L = R_F/2.

Substituting a lamp (R_L) for the gain setting resistor reduces distortion because the nonlinear lamp resistance adjusts the gain to keep the output voltage smaller than the power supply voltage. The output voltage never approaches the power supply rail, so distortion doesn’t occur. R_F and R_L determine the lamp current (see Equations 26.46 and 26.47).

(26.46)

(26.47)

The lamp is selected by examining lamp resistance curves until a lamp with a resistance approximately equal to R_F/2 at I_OUT(RMS) is found. The output voltage swing should be less than 75% of the maximum guaranteed voltage swing, and 3 R_L must be greater than the load resistance specified for the voltage swing specification. V_REF should be V_CC/5.

26.5.3 Wien Bridge Oscillator with AGC

The op-amp is configured as an AC amplifier to ease biasing problems. The gain equation for the op-amp is given below. R_G1 or R_G2, but not both resistors, is required depending on the selection of the Q₁.

The diode, D₁, half-wave rectifies the output voltage and applies it to the voltage divider formed by R₁ and R₂. The voltage divider biases Q₁ in its linear region, and they eventually set the output voltage. C₁ filters the rectified sine wave with a long time constant so that the output voltage stays constant. C₂ must be selected large enough to act as a short at the oscillation frequency.

As the output voltage increases, the negative voltage across the gate of Q₁ increases. The increased negative gate voltage causes Q₁ to increase its drain-to-source resistance. This results in increased op-amp gain and an output voltage decrease. When the voltage divider and FET are selected properly, the output voltage swing is less than the guaranteed maximum swing, so distortion doesn’t occur.

(26.48)

26.5.4 Quadrature Oscillator

Quadrature oscillators produce sine waves 90° out of phase, so they output sine/cosine, or quadrature waves.

When R₁C₁ = R₂C₂ = R₃C₃, the circuit oscillates at ω = 2πf = 1/RC. Both op-amps act as integrators causing two poles at 1/RC, thus the circuit oscillates when the loop gain crosses the 0-dB axis. The integrators ensure that gain is always sufficient for oscillation. There is a slight bit of distortion at the sine output, and it is very hard to eliminate this distortion.

26.5.5 Classical Phase Shift Oscillator

Theoretically, the three RC sections do not load each other, thus the loop gain has three identical poles multiplied by the op-amp gain.

The loop phase shift is −180° when the phase shift of each section is −60°, and this occurs when ω = 2πf = 1.732/RC because the tangent of 60° = 1.73. The magnitude of β at this point is (1/2)³, so the gain, A = R_F/R_G, must be greater or equal to 8 for the system gain to be equal to 1.

The assumption that the RC sections do not load each other is not entirely valid, thus the circuit does not oscillate at the specified frequency, and the gain required for oscillation is more than 8. This circuit configuration was very popular when an active component was large and expensive, but now that op-amps are inexpensive, small, and come quad packages, the classical phase shift oscillator is losing popularity

The classical phase shift oscillator has an undistorted sine wave available at the output of the third RC section. This is not a low-impedance output, and the signal amplitude is smallest here, but these sacrifices have to be made to get away from distortion. An undistorted output can be obtained from the op-amp if an AGC circuit similar to the one shown in Figure 26.39 is employed. The reference voltage is set according to the equation V_REF = V_CC/ 2(1 + R_F/R_G) to center the output voltage at V_CC/2.

(26.49)

26.5.6 Buffered Phase Shift Oscillator

A noninverting op-amp buffers each RC section in this oscillator. Equation 26.49, repeated below, truly represents the transfer function of this circuit if RG >> R.

(26.50)

The loop phase shift is −180° when the phase shift of each section is −60°, and this occurs when ω = 2πf = 1.732/RC because the tangent 60° = 1.73. The magnitude of β at this point is (1/2)³, so the gain, A = R_F/R_G, must be greater or equal to 8 for the system gain to be equal to one.

The buffered phase shift oscillator has an undistorted sine wave available at the output of the third RC section. This is not a low-impedance output, and the signal amplitude is smallest here, but these sacrifices have to be made to get away from distortion. An undistorted output can be obtained from the op-amp if an AGC circuit similar to the one shown in Figure 26.39 is employed.

There are three op-amps, so the gain can be distributed among the op-amps at the expense of a few resistors, and the distortion is reduced. Another method of reducing distortion is to limit the output voltage swing softly with external components. The limiting technique does not yield as good results as the AGC technique does, but it is less expensive. The reference voltage is set according to the equation V_REF = V_CC/ 2(1 + R_F/R_G) to center the output voltage at V_CC/2.

26.5.7 Bubba Oscillator

The Bubba oscillator is another phase shift oscillator, but it takes advantage of the quad op-amp package to yield some unique advantages. Each RC section is buffered by an op-amp to prevent loading. When R_G >> R there is no loading in the circuit, and the circuit yields theoretical performance.

Four RC sections require −45° phase shift per section to accumulate −180° phase shift. Each RC section contributes −45° phase shift when ω = 1/RC. The gain required for oscillation is G ≥ (1/0.707)⁴= 4. Taking outputs from alternate sections yields low-impedance quadrature outputs. When an output is taken from each op-amp, the circuit delivers four 45° phase-shifted sine waves.

The gain, A, must equal 4 for oscillation to occur. Very low distortion sine waves can be obtained from the junction of R and R_G. When low-distortion sine waves are required at all outputs, the gain should be distributed among the op-amps. Gain distribution requires biasing of the other op-amps, but it has no effect on the oscillator frequency. This oscillator has the best dφ/df of the phase shift oscillators, so it has minimum frequency drift. The reference voltage is set according to the equation V_REF = V_CC/2(1 + R_F/R_G) to center the output voltage at V_CC/2.

(26.51)

26.5.8 Triangle Oscillator

The triangle oscillator produces triangle waves and square waves. The op-amp functions as an integrator. When the output voltage of the comparator is low, the output of the op-amp charges C until the output voltage exceeds the hysteresis voltage set by R₁ and R_F and the reference voltage (V_CC/2). At this point, the comparator output switches to a high state and the op-amp integrates the voltage in a negative direction. The triangle wave (op-amp output voltage swing) is given in Equation 26.52. The frequency of oscillation is given in Equation 26.53.

(26.52)

(26.53)

The op-amp reference voltage can be adjusted to equalize the triangle rise and fall times.

26.6.1 Hybrid Darlington Pair

Cool application note, using two transistors to switch a signal level Vcc PNP switched by NPN (see Figure 26.45).

This is a handy circuit that switches a higher level voltage with a lower level one. Say, for example, you have a micro with a 5V output and you need to drive a 12V load. For a reason you can’t change, you have to switch the Vcc leg. In this circuit you turn on one transistor with a 5V signal, which in turn activates the other transistor switching the higher voltage to the load. This works because the transistors are current driven; when you shut off the current flow to the PNP transistor, it shuts off regardless of the voltage. Another plus is that this circuit has Darlington-like properties without one of the downsides. You won’t need a lot of current to the input to switch the output and, unlike a traditional Darlington pair, the voltage drop across the output is much smaller. You don’t have two series base junctions to contend with at the output.

26.6.2 DC Level Shifter

This is really the high-pass filter that we have already studied but with a slight twist. Instead of ground, we hook the resistor to a reference voltage. Since DC has a frequency of zero, only the AC component will pass and in the process a DC bias will be applied to the signal. Make sure you don’t size the cap and resistor so that the signal you want is attenuated.

26.6.3 Virtual Ground

Using the voltage divider as a reference, the op-amp becomes a voltage source with the output matching the voltage at the divider. This can be very useful when you are trying to handle AC signals with only a single-ended supply circuit.

26.6.4 Voltage Follower

This one is mighty useful when trying to measure a signal that is easily affected by load. V_i = V_o, but, best of all, V_i isn’t loaded at all, thanks to the buffering effect of the op-amp.

This is another great circuit that works nicely amplifying AC signals with a single-ended supply. It also has the benefit of not amplifying any DC signal components, keeping things like DC offsets from making your signal rail. This happens because of the cap in the feedback circuit. Since the cap only passes AC current, DC signals see that point as disconnected. When the resistor to ground is disconnected, the op-amp acts like the voltage follower in the previous circuit.

26.6.5 Inverter Oscillator

I saw this in the back of a data book years ago; I think it was a Motorola logic data book. This was way back before the internet—you used to have to turn pages to find this stuff! The way it works is based on the fact that the Schmidt trigger inverter has hysteresis built into the input. This makes the output stick at a high or low level till the cap on the input charges to the threshold voltage that trips the inverter. Output flips and everything goes the other direction, repeating indefinitely. Adding some diodes to the charge and discharge path can affect the duty cycle of the output.

26.6.6 Constant Current Source

Using negative feedback, the op-amp tries to maintain the voltage drop across R input. Even if the resistance of the load changes, the drop across the R input stays the same. According to Ohm’s Law, keeping R and V the same will keep current the same too. Remember, though, this current control has operational limits; it can only swing the output voltage so far to compensate for load variance. Once these limits are reached, the current regulation can no longer exist.

26.6.7 Get Your Own

These are just a few of my favorites. Get your own and know them well. You will be better served knowing a few circuit concepts inside and out than knowing thousands superficially.