This vector instruction is a parallel operation that uses an adder on each of the source floating-point blocks aSrc (xmmSrc) and bSrc (xmmDst) and stores the result in the destination Dst (xmmDst).

The instructions may be labeled as packed, parallel, or vector, but each block of floating-point bits is in reality isolated from one another.

The following are 64/128-bit single- and double-precision summation samples.

64-bit single-precision floating-point

128-bit single-precision floating-point

128-bit double-precision floating-point

This vector instruction is a scalar operation that uses an adder with the source scalar xmmSrc and the source floating-point value in the least significant block within xmmDst and stores the result in the destination xmmDst. The upper float elements are unaffected.

This vector instruction is a parallel operation that subtracts each of the source floating-point blocks aSrc (xmmSrc) from bSrc (xmmDst) with the result stored in the destination Dst (xmmDst).

The register and operator ordering is as follows:

The instructions may be labeled as packed, parallel, or vector, but each block of floating-point bits is in reality isolated from one another.

64-bit single-precision floating-point

128-bit single-precision floating-point

128-bit double-precision floating-point

This vector instruction is a scalar operation that subtracts the least significant source floating-point block of xmmSrc from the same block in xmmDst and stores the result in the destination xmmDst. The upper float elements are unaffected.

This vector instruction is a parallel operation that subtracts each of the source floating-point blocks bSrc (mmxDst) from aSrc (mmxSrc) with the result stored in the destination Dst (mmxDst).

The register and operator ordering is as follows:

The instructions may be labeled as packed, parallel, or vector, but each block of floating-point bits is in reality isolated from one another.

A typical subtraction uses an equation similar to {a=a–b}, but what happens if the equation {a=b–a} is needed instead? This instruction solves that situation by limiting any special handling needed to exchange values between registers such as the following:

or

By now you should be very aware that you should be using assertions in your code such as the ASSERT_PTR4 for normal pointers and ASSERT_PTR16 for pointers to vectors to ensure they are properly aligned in memory, so I will try not to bore you with it much anymore in print. You should also by now be aware of the penalties for dealing with out of alignment memory. Keep these in mind when writing your own code. There is also a limitation on the use of the term const to help make the printed code less wordy and more clear.

You will find that for purposes of cross-platform compatibility, these functions return no arguments. They are instead written as procedures where the first argument points to a buffer that the result is stored in. This is not written to make your life confusing. It is written this way because of one particular processor: the 80×86. Due to its MMX versus FPU usage an EMMS instruction must be called to reset that functionality as a clean slate, so only one of them can be used at a time. By not returning a value such as a float or array of floats, it minimizes the risk that the programmer might accidentally try to use the returned value while in the wrong mode. In this way the vmp_SIMDEntry() and vmp_SIMDExit() procedure calls are made to assist in switching between FPU and MMX mode of operation. Since most of you will be focused upon float and not integer or fixed-point vector math, that will be the focus, but the principles are the same!

The simple addition and subtraction of a single (scalar) float has been included here as a reference.

void vmp_FAdd(float *pfD, float fA, float fB)
{
  *pfD = fA + fB;
}

void vmp_FSub(float *pfD, float fA, float fB)
{
  *pfD = fA - fB;
}

void vmp_VecAdd(vmp3DVector * const pvD,
          const vmp3DVector * const pvA,
          const vmp3DVector * const pvB)
{
  pvD->x = pvA->x + pvB->x;
  pvD->y = pvA->y + pvB->y;
  pvD->z = pvA->z + pvB->z;
}

void vmp_VecSub(vmp3DVector * const pvD,
          const vmp3DVector * const pvA,
          const vmp3DVector * const pvB)
{
  pvD->x = pvA->x - pvB->x;
  pvD->y = pvA->y - pvB->y;
  pvD->z = pvA->z - pvB->z;
}

void vmp_QVecAdd(vmp3DQVector * const pvD,
           const vmp3DQVector * const pvA,
           const vmp3DQVector * const pvB)
{
  pvD->x = pvA->x + pvB->x;
  pvD->y = pvA->y + pvB->y;
  pvD->z = pvA->z + pvB->z;
  pvD->w = pvA->w + pvB->w;
}

void vmp_QVecSub(vmp3DQVector * const pvD,
           const vmp3DQVector * const pvA,
           const vmp3DQVector * const pvB)
{
  pvD->x = pvA->x - pvB->x;
  pvD->y = pvA->y - pvB->y;
  pvD->z = pvA->z - pvB->z;
  pvD->w = pvA->w - pvB->w;
}

Now examine these functions closer using x86 assembly. As MMX does not support floating-point, only 3DNow!, SSE, and above can be utilized. 3DNow! supports 64-bit so two loads must be handled simultaneously and two stores, but it is a simple matter of adding the two pairs of floats to each other. This example shows that three floats {XYZ} are being used and the fourth element {W} is being ignored.

mov   eax,vA    ; Vector A
mov   ebx,vB    ; Vector B
mov   edx,vD    ; Vector destination

movq  mm0,[eax]                      ; vA.xy {Ay Ax}
movq  mm2,[ebx]                      ; vB.xy {By Bx}
movd  mm1,(vmp3DVector PTR [eax]).z  ; {0 Az}
movd  mm3,(vmp3DVector PTR [ebx]).z  ; {0 Bz}
pfadd mm0,mm2                        ; {Ay+By Ax+Bx}
pfadd mm1,mm3                        ; {0+0 Az+Bz}
movq  [edx],mm0                      ; {Ay+By Ax+Bx}
movd  (vmp3DVector PTR [edx]).z,mm1  ; {0 Az+Bz}

movq  mm0,[eax]                            ; vA.xy {Ay Ax}
movq  mm2,[ebx]                            ; vB.xy {By Bx}
movd  mm1,(vmp3DVector PTR [eax]).z        ; {0 Az}
movd  mm3,(vmp3DVector PTR [ebx]).z        ; {0 Bz}
pfsub mm0,mm2                              ; {Ay-By Ax-Bx}

pfsub  mm1,mm3                             ; {0-0   Az-Bz}
movq   [edx],mm0                           ; {Ay-By Ax-Bx}
movd   (vmp3DVector PTR [edx]).z,mm1       ; {0 Az-Bz}

movq  mm0,[eax+0]                  ; vA.xy {Ay Ax}
movq  mm2,[ebx+0]                  ; vB.xy {By Bx}
movq  mm1,[eax+8]                  ; vA.zw {Aw Az}
movq  mm3,[ebx+8]                  ; vB.zw {Bw Bz}
pfadd  mm0,mm2                     ; {Ay+By Ax+Bx}
pfadd  mm1,mm3                     ; {Aw+Bw Az+Bz}
movq  [edx+0],mm0                  ; {Ay+By Ax+Bx}
movq  [edx+8],mm1                  ; {Aw+Bw Az+Bz}

himsk32 DWORD 000000000h, 000000000h, 000000000h,
              0FFFFFFFFh     ; Save upper 32 bits
lomsk96 DWORD 0FFFFFFFFh, 0FFFFFFFFh, 0FFFFFFFFh,
              000000000h     ; Save lower 96 bits

movups xmm2,[edx]               ; vD.xyzw {Dw Dz Dy Dx}
movups xmm0,[ebx]               ; vB.xyzw {Bw Bz By Bx}
movups xmm1,[eax]               ; vA.xyzw {Aw Az Ay Ax}
andps  xmm2,OWORD PTR himsk32   ; {Dw   0   0   0}
addps  xmm0,xmm1                ; {Aw+Bw Az+Bz Ay+By Ax+Bx}
andps  xmm0,OWORD PTR lomsk96   ; {0 Az+Bz Ay+By Ax+Bx}
orps   xmm0,xmm2                ; {Dw Az+Bz Ay+By Ax+Bx}
movups [edx],xmm0               ; {Dw Dz   Dy   Dx}

movaps  xmm2,[edx]                  ; vD.xyzw {Dw Dz Dy Dx}
movaps  xmm0,[ebx]                  ; vB.xyzw {Bw Bz By Bx}
movaps  xmm1,[eax]                  ; vA.xyzw {Aw Az Ay Ax}
andps   xmm2,OWORD PTR himsk32      ; {Dw 0 0 0}
addps   xmm0,xmm1                   ; {Aw+Bw Az+Bz Ay+By Ax+Bx}
andps   xmm0,OWORD PTR lomsk96      ; {0 Az+Bz Ay+By Ax+Bx}
orps    xmm0,xmm2                   ; {Dw Az+Bz Ay+By Ax+Bx}
movaps  [edx],xmm0                  ; {Dw Dz Dy Dx}

movaps  xmm1,[ebx] ; {Bw Bz By Bx}
movaps  xmm0,[eax] ; {Aw Az Ay Ax}
addps   xmm0,xmm1  ; {Aw+Bw Az+Bz Ay+By Ax+Bx}
movaps  [edx],xmm0 ; {Dw Dz Dy Dx}

void vmp_VecSubScalar(vmp3DVector * const pvD,
   const vmp3DVector * const pvA, float fScalar)
{
  pvD->x = pvA->x - fScalar;
  pvD->y = pvA->y - fScalar;
  pvD->z = pvA->z – fScalar;
}

Did that look strangely familiar? The big question now is, "How do we replicate a scalar to look like a vector since there tends not to be mirrored scalar math on processors?" Typically a processor will interpret a scalar calculation as the lowest (first) float being evaluated with a single scalar float. This is fine and dandy, but there are frequent times when a scalar needs to be replicated and summed to each element of a vector. So the next question is how do we do that?

With the 3DNow! instruction set it is easy. Since the processor is really a 64-bit half vector, the data is merely unpacked into the upper and lower 32 bits.

movd      mm2,fScalar    ; fScalar {0 s}
punpckldq mm2,mm2        ; fScalar {s s}

Then it is just used twice, once with the upper 64 bits and then once with the lower 64 bits.

pfadd     mm0,mm2        ; {Ay+s Ax+s}
pfadd     mm1,mm2        ; {Aw+s Az+s}

With the SSE instruction set it is almost as easy. The data is shuffled into all 32-bit floats.

movss      xmm1,fScalar         ; {0 0 0 s}
shufps     xmm1,xmm1,00000000b  ; {s s s s}

Now the scalar is the same as the vector.

addps     xmm0,xmm1       ; {Aw+s Az+s Ay+s Ax+s}

Any questions?

This vector instruction is a parallel operation that has an even subtraction and an odd addition of the source floating-point blocks. For the even elements, subtract aSrc (xmmSrc) from bSrc (xmmDst) with the result stored in the destination Dst (xmmDst). For the odd elements, sum aSrc (xmmSrc) and bSrc (xmmDst) with the result stored in the destination Dst (xmmDst).

This vector instruction is a parallel operation that separately sums the odd/even pairs of the source and destination and stores the result of the bSrc (xmmDst) in the lower destination elements of Dst (xmmDst) and the result of the aSrc (xmmSrc) in the upper elements of Dst (xmmDst).

This vector instruction is a parallel operation that separately subtracts the (odd) element from the (even) element and stores the result of the bSrc (xmmDst) in the lower destination elements of Dst (xmmDst) and the result of the aSrc (xmmSrc) in the upper addresses of Dst (xmmDst).

This half-vector instruction is a parallel operation that separately subtracts the upper element from the lower element of bSrc (mmxDst) and stores the result in the lower element of Dst (mmxDst). The sum of the upper and lower elements of aSrc (mmxSrc) is stored in the upper element of Dst (mmxDst).