ADD destination, source

The ADD general-purpose instruction logically sums the 8-, 16-, 32-, or 64-bit source to the destination, saves the result in destination, and sets the flags accordingly. An 8-bit source immediate value can be sign extended to 16-, 32-, or 64-bit value. A 32-bit source immediate value can be sign extended to a 64-bit destination.

The ADC general-purpose instruction does exactly the same operation but with one difference. The carry value of 0 or 1 is added to the ending result: d = a + b + (carry)

When adding a series of numbers one typically uses the non-carry ADD first, followed by ADC for each additional calculation, taking into account the resulting Carry flag.

a   =  a  +  b  +  c  +  d  +  e
a   =  a ADD b ADC c ADC d ADC e

          mov   eax,0000a5a5h
          add   eax,00000ff0h
          adc   eax,0000ff00h
          adc   eax,000ff000h
          adc   eax,00ff0000h

; Add   two 64 #'s     ecx:ebx + edx:eax
          add     ebx,eax       ; Carry results from lower 32 bits.
          adc     ecx,edx       ; Add upper 32 bits + carry

; or when using a 64-bit processor
        add     rbx,rax       ; 64 bits
; and then add with carry for a 128-bit summation.
        adc     rcx,rdx

Sums for really big numbers can be calculated in this way. Need a number 8000 bits long? You can do it in assembly by continuously adding the carry of previous arithmetic operations onto a current operation.

The INC general-purpose instruction is very similar to the ADD instruction, adding a value of 1 to the 8-, 16-, 32-, or 64-bit destination. The result is saved in the destination: d = a + 1.

It is recommended that an ADD instruction be used instead of an INC since flag dependencies can cause stalling due to previous writes to the EFLAG registers.

inc     eax

Use this instead:

add     eax,1

Various forms of indirect memory reference, such as the following, are still allowed:

inc     [eax]
inc     [eax+ebx*4]

This applies to all the general-purpose registers.

 #ifdef _M_IX86
 #define  QUICK_INCREMENT(v) __asm inc v;
 #else
 #define  QUICK_INCREMENT(v) 
     EnterMutex() 
     v++;    
     ExitMutex()
 #endif

XADD destination, source

The XADD general-purpose instruction first exchanges the values in the source general-purpose register and destination just like the XCHG instruction and then logically sums the 8-, 16-, 32-, or 64-bit source to the destination, saves the result in destination, and sets the flags accordingly.

This instruction is rarely used except in the case where a register exchange needs to take place so as to preserve the old value. This is equivalent to four separate instructions:

...or two instructions by using the XCHG instruction.

As you can see, the old value is preserved in the source register, and the destination memory gets the sum of the new and old values.

SUB destination, source

The SUB general-purpose instruction logically subtracts the 8-, 16-, 32-, or 64-bit source from the destination, saves the result in destination, and sets the flags accordingly. An 8-bit immediate source value can be sign extended to 16-, 32-, or 64-bit value. A 32-bit immediate source value can be sign extended to a 64-bit destination: d = b – a.

The SBB general-purpose instruction does exactly the same thing but with one difference: The Carry flag is referred to as the borrow flag with a value of 0 or 1, which is subtracted from the ending result.

6d = b – a – (Carry)

When subtracting a series of numbers one typically uses SUB for the first subtraction, followed by SBB for each additional subtraction, taking into account the Carry flag, which indicates a borrow is required from the next calculation.

a = a – b – c – d – e

a = a SUB b SBB c SBB d SBB e

        mov     eax,0000a5a5h
        sub     eax,00000ff0h
        sbb     eax,0000ff00h
        sbb     eax,000ff000h
        sbb     eax,00ff0000h

The DEC general-purpose instruction is very similar to the SUB instruction, subtracting a value of 1 from the 8-, 16-, 32-, or 64-bit destination. The result is saved in the destination: d = a – 1.

It is recommended that a SUB instruction be used instead of a DEC since flag dependencies can cause stalling due to previous writes to the EFLAG registers.

dec     eax

Use this instead:

sub     eax,1

The various forms of indirect memory reference, such as the following, are still allowed:

dec     [eax]
dec     tbl[ebx+ecx*2]

This applies to all the general-purpose registers.

#ifdef _M_IX86
#define  QUICK_DECREMENT(v) __asm dec v;
#else
#define  QUICK_DECREMENT(v) 
    EnterMutex()   
    v--;            
    ExitMutex()
#endif

     inc al
     jnz $L1        ; Jump if not saturated!
     dec al
$L1:

add al,1
sbb al,0

sub al,1
adc al,0

PADDx destination, source

The PADDx instruction is a parallel operation that uses an adder on each of the source bit blocks aSrc (xmmSrc) and bSrc (xmmDst) and stores the result in the destination Dst (xmmDst).

The instructions may be labeled as packed, parallel, or vector, but each block of bits is in reality isolated from each other. The following is a 32-bit example consisting of four unsigned 8-bit values:

...and four signed 8-bit values:

Regardless of the decimal representation of unsigned or signed, the hex values of the two examples remains the same, which is the reason for these being [Un]signed, thus sign neutral.

Notice in the following additions of 7-bit signed values that with the limit range of –64...63 the worst case of negative and positive limit values results with no overflow.

Of course, positive and negative signed values could also be intermixed without an overflow. For a 7-bit unsigned value, 0...127, there would be no overflow.

The eighth unused bit is in reality used as a buffer to prevent any overflow to a ninth bit.

The PADDSx (signed) and PADDUSx (unsigned) instructions are a parallel operation that uses an adder on each of the source bit block registers aSrc (xmmSrc) and bSrc (xmmDst) and stores the result in the destination Dst (xmmDst) using saturation logic to prevent any possible wraparound.

Each calculation limits the value to the extents of the related data type so that if the limit is exceeded, it is clipped inclusively to that limit. This is handled differently whether it is signed or unsigned, as they both use different limit values. Effectively, the result of the summation is compared to the upper limit with a Min expression and compared to the lower limit with a Max expression. Notice in the previous section that when two signed 8-bit values of 0x7F (127) are summed, a value of 0xFE (254) results but is clipped to the maximum value of 0x7f (127). The same applies if, for example, two values of 0x80 (–128) are summed, resulting in –256 but clipped to the minimum value of 0x80 (–128).

The instructions may be labeled as packed, parallel, or vector but each block of bits is in reality isolated from each other.

A sample use of this instruction would be for sound mixing where two sound waves are mixed into a single wave for output. The saturation point keeps the amplitude of the wave from wrapping from a positive or high level into a negative or low one, thus creating a pulse encoded harmonic, or distortion.

For saturation, the limits are different for the data size as well as for signed and unsigned.

PSUBx destination, source D –= A

This vector instruction is a parallel operation that subtracts each of the source bit blocks aSrc (xmmSrc) from bSrc (xmmDst) and stores the result in the destination Dst (xmmDst).

PSUBSx destination, source D –= A

This vector instruction is a parallel operation that subtracts each of the source bit blocks aSrc (xmmSrc) from bSrc (xmmDst) and stores the result in the destination Dst (xmmDst).

These can get pretty verbose, as for fixed-point (integer) addition there would be support for 8-, 16-, and 32-bit data elements within a 128-bit vector and these would be signed and unsigned, with and without saturation. The interesting thing about adding signed and unsigned numbers, other than the carry or borrow, is that the resulting value will be exactly the same and thus the same equation can be used. This can be viewed in the following 8-bit example:

Notice that the resulting bits from the 8-bit calculation are all the same. Only the carry is different and the resulting bits are only interpreted as being signed or unsigned.

Now let's examine these functions closer. MMX and SSE2 have the biggest payoff, as 3DNow! and SSE are primarily for floating-point support.

  mov     ebx,pbB         ; Vector B
  mov     eax,pbA         ; Vector A
  mov     edx,pbD         ; Vector Destination

The following is a 16×8-bit addition but substituting a PSUBB for the PADDB will transform it into a subtraction.

movq    mm0,[ebx+0]   ; Read B Data {B7...B0}
movq    mm1,[ebx+8]   ;              {BF...B8}
movq    mm2,[eax+0]   ; Read A Data {A7...A0}
movq    mm3,[eax+8]   ;              {AF...A8}
paddb   mm0,mm2       ; lower 64 bits {A7+B7 ... A0+B0}
paddb   mm1,mm3       ; upper 64 bits {AF+BF ... A8+B8}
movq    [edx+0],mm0
movq    [edx+8],mm1

movdqa xmm0,[ebx]     ; Read B Data {BF...B0 }
movdqa xmm1,[eax]     ; Read A Data {AF...A0 }
paddb  xmm0,xmm1      ; {vA+vB} 128 bits {AF+BF   ... A0+B0}
movdqa [edx],xmm0     ; Write D Data

This SIMD instruction is a 64 (128)-bit parallel operation that sums the eight (16) individual 8-bit source integer bit blocks aSrc (xmmSrc) and bSrc (xmmDst), adds one, then divides by two and returns the lower 8 bits with the result being stored in the destination Dst (xmmDst).

This SIMD instruction is a 64 (128)-bit parallel operation that sums the four (eight) individual 16-bit source integer bit blocks aSrc (xmmSrc) and bSrc (xmmDst), adds one, then divides by two and returns the lower 16 bits with the result being stored in the destination Dst (xmmDst).

8×8-Bit Sum of Absolute Differences

Dst(15...0) = abs(Src(7...0) - Dst(7...0)) + abs(Src(15...8) -
          Dst(15...8))
     + abs(Src(23...16) - Dst(23...16)) + abs(Src(31...24) - Dst(31...24))
     + abs(Src(39...32) - Dst(39...32)) + abs(Src(47...40) - Dst(47...40))
     + abs(Src(55...48) - Dst(55...48)) + abs(Src(63...56) - Dst(63...56))
Dst(63...16) =  0;

16×8-Bit Sum of Absolute Differences

Dst(31...16) = abs(Src(71...64) - Dst(71...64)) + abs(Src(79...72) -
          Dst(79...72))
     + abs(Src(87...80) - Dst(87...80)) + abs(Src(95...88) - Dst(95...88))
     + abs(Src(103...96) - Dst(103...96)) + abs(Src(111...104) -
          Dst(111...104))
     + abs(Src(119...112) - Dst(119...112)) + abs(Src(127...120) -
          Dst(127...120))
Dst(127...32) = 0

MUL operand

The MUL general-purpose instruction multiplies the unsigned 8-, 16-, 32-, or 64-bit operand by the unsigned AL/AX/EAX/RAX register, saves the result based upon the bit size of the operand as indicated in the table below, and sets the flags accordingly.

A square operation (x²) is actually pretty simple!

        mov     rax,7
        mul     rax             ; rdx:rax = rax x rax

The IMUL general-purpose instruction has three forms based upon the number of operands.

PMULLW destination, source

These vector instructions use a 64 (128)-bit data path and so four (eight) operations occur in parallel. The product is calculated using each of the 16-bit half-words of the multiplicand mmxSrc (xmmSrc) and the 16-bit half-words of the multiplier mmxDst (xmmDst) for each 16-bit block, and stores the lower 16 bits of each of the results in the original 16-bit half-words of the destination mmxDst (xmmDst).

PMULHW destination, source

These vector instructions use a 64 (128)-bit data path and so four (eight) operations occur in parallel. The product is calculated using each of the 16-bit half-word of the multiplicand mmxSrc (xmmSrc) and the 16-bit half-word of the multiplier mmxDst (xmmDst) for each 16-bit block, and stores the upper 16 bits of each of the results in the original 16-bit half-words of the destination mmxDst (xmmDst).

PMULHRW destination, source

This vector instruction uses a 64-bit data path and so four operations occur in parallel. The product is calculated using each of the unsigned 16-bit half-words of the multiplicand mmxDst and the 16-bit half-word of the multiplier mmxSrc for each 16-bit block, sums 00008000 hex to the 32-bit product, and stores the resulting upper 16 bits in the destination mmxDst (xmmDst).

Dst(15...0) = UPPER16((Dst(15...0)   x Src(15...0)) + 0x8000)
Dst(31...16) = UPPER16((Dst(31...16) x Src(31...16)) + 0x8000)
Dst(47...32) = UPPER16((Dst(47...32) x Src(47...32)) + 0x8000)
Dst(63...48) = UPPER16((Dst(63...48) x Src(63...48)) + 0x8000)

An interesting thing about the SSE instruction set is that it is primarily designed for floating-point operations. The MMX instruction set handles most of the packed integer processing except the case of unsigned 16-bit multiplication. This was not resolved until a later release of extensions for the MMX by AMD and the SSE by Intel, but this is only 64 bits. Intel came back with the SSE2 instruction set with a complete set of packed instructions for supporting 128 bits.

mov     ebx,phB         ; Vector B
mov     eax,phA         ; Vector A
mov     edx,phD         ; Vector Destination

movq     mm0,[ebx+0] ; Read B Data {3...0}
movq     mm1,[ebx+8] ;             {7...4}
movq     mm2,[eax+0] ; Read A Data {3...0}
movq     mm3,[eax+8] ;             {7...4}

pmullw   mm0,mm2
pmullw   mm1,mm3

movq     [edx+0],mm0 ; Write D ??? 16 bits  {3...0}
movq     [edx+8],mm1 ;   (upper or lower)   {7...4}

pmulhw   mm0,mm2 ; SIGNED HIGH   {3...0}
pmulhw   mm1,mm3 ;               {7...4}

pmulhuw  mm0,mm2 ; UNSIGNED HIGH {3...0}
pmulhuw  mm1,mm3 ;               {7...4}

movdqa  xmm0,[ebx]      ; Read B Data   {7...0}
movdqa  xmm1,[eax]      ; Read A Data   {7...0}
pmullw  xmm0,xmm1
movdqa  [edx],xmm0      ; Write D lower 16 bits {7...0}

PMULUDQ destination, source

This vector instruction calculates the product of the (even) lower 32 bits of each set of 64 (128) bits of the multiplicand aSrc (xmmSrc) and the lower 32 bits of the multiplier bSrc (xmmDst) for each 64 (128)-bit block, and stores each full 64 (128)-bit integer result in the destination Dst (xmmDst).

In the following 64-bit table, the upper 32 bits {63...32}of mmxSrc and mmxDst are ignored. Note that this is not a SIMD reference but included for reference.

In the following 128-bit table, the upper odd pairs of 32 bits {127...96, 63...32} of xmmDst and xmmSrc are ignored.

PMADDWD destination, source

This vector instruction calculates the 32-bit signed products of two pairs of two 16-bit multiplicands aSrc(xmmSrc) and the multiplier bSrc(xmmDst) for each bit block. The first and second 32-bit products are summed and stored in the lower 32 bits of the Dst(xmmDst). The third and fourth 32-bit products are summed and stored in the next 32 bits of the destination Dst(xmmDst). The same is repeated for the upper 64 bits for the 128-bit data model.

DIV operand

The DIV general-purpose instruction divides the unsigned 16-, 32-, 64-, or 128-bit AX, DX:AX, EDX:EAX, RDX:RAX pair into the 8-, 16-, 32-, or 64-bit operand and saves the result based upon the bit size of the operand as indicated in the table below and sets the flags accordingly.

div ebx

IDIV operand

The IDIV general-purpose instruction divides the signed 16-, 32-, 64-, or 128-bit AX, DX:AX, EDX:EAX, RDX:RAX pair into the 8-, 16-, 32-, or 64-bit operand and saves the result based upon the bit size of the operand as indicated in the table below and sets the flags accordingly.

The sign of the remainder always matches the sign of the divisor. An overflow is indicated by a Divide Error Exception instead of the Overflow flag.