- Copyright
- Preface
- 1. Introduction
- 2. Coding Standards
- 3. Processor Differential Insight
- Processor Overview
- History
- The 64-Bit Processor
- 80x86 Registers
- CPU Status Registers (EFLAGS/64-Bit RFLAGS)
- NOP — No Operation
- Floating-Point 101
- Processor Data Type Encoding
- EMMS — Enter/Leave MMX State
- FEMMS — Enter/Leave MMX State
- Destination/Source Orientations
- Big/Little-Endian
- Alignment Quickie
- (Un)aligned Memory Access
- System Level Functionality
- Indirect Memory Addressing
- Translation Table
- String Instructions
- Special (Non-Temporal) Memory Instructions
- Exercises
- 4. Bit Mangling
- 5. Bit Wrangling
- 6. Data Conversion
- Data Interlacing, Exchanging, Unpacking, and Merging
- Byte Swapping
- Data Interlacing
- PUNPCKLBW — Parallel Extend Lower from Byte
- PUNPCKHBW — Parallel Extend Upper from Byte
- PUNPCKLWD — Parallel Extend Lower from 16-Bit
- PUNPCKHWD — Parallel Extend Upper from 16-Bit
- PUNPCKLDQ — Parallel Extend Lower from 32-Bit
- PUNPCKHDQ — Parallel Extend Upper from 32-Bit
- MOVSS — Move Scalar (SPFP)
- MOVQ2DQ — Move Scalar (1×32-Bit) MMX to XMM
- MOVDQ2Q — Move Scalar (1×32-bit) XMM to MMX
- MOVLPS — Move Low Packed (2×SPFP)
- MOVHPS — Move High Packed (2×SPFP)
- MOVLHPS — Move Low to High Packed (2×SPFP)
- MOVHLPS — Move High to Low Packed (2×SPFP)
- MOVSD — Move Scalar (1×DPFP)
- MOVLPD — Move Low Packed (1×DPFP)
- MOVHPD — Move High Packed (1×DPFP)
- PUNPCKLQDQ — Parallel Copy Lower (2×64-Bit)
- PUNPCKHQDQ — Parallel Copy Upper (2×64-Bit)
- Swizzle, Shuffle, and Splat
- PINSRW — Shuffle (1×16-Bit) to (4×16-Bit)
- PSHUFW — Shuffle Packed Words (4×16-Bit)
- PSHUFLW — Shuffle Packed Low Words (4×16-Bit)
- PSHUFHW — Shuffle Packed High Words (4×16-Bit)
- PSHUFD — Shuffle Packed Double Words (4×32-Bit)
- SHUFPS — Shuffle Packed SPFP Values (4×SPFP)
- MOVSLDUP — Splat Packed Even SPFP to (4×SPFP)
- MOVSHDUP — Splat Packed Odd SPFP to (4×SPFP)
- MOVDDUP — Splat Lower DPFP to Packed (2×DPFP)
- SHUFPD — Shuffle Packed DPFP (2×64-Bit)
- Data Bit Expansion
- CBW Convert Signed AL (Byte) to AX (Word)
- CWDE Convert Signed AX (Word) to EAX (DWord)
- CDQE Convert Signed EAX (DWord) to RAX (QWord)
- MOVSX/MOVSXD — Move with Sign Extension
- MOVZX — Move with Zero Extension
- CWD — Convert Signed AX (Word) to DX:AX
- CDQ — Convert Signed EAX (DWord) to EDX:EAX
- CQO — Convert Signed RAX (QWord) to RDX:RAX
- PEXTRW — Extract (4×16-bit) into Integer to (1×16)
- Data Bit Reduction (with Saturation)
- Data Conversion (Integer : Float, Float : Integer, Float : Float)
- PI2FW — Convert Packed Even int16 to SPFP
- CVTDQ2PS — Convert Packed int32 to SPFP
- CVTPS2DQ — Convert Packed SPFP to int32
- CVTPI2PS — Convert Lo Packed int32 to SPFP
- CVTPS2PI — Convert Lo Packed SPFP to int32
- CVTSI2SS — Convert Scalar int32 to SPFP
- CVTDQ2PD — Convert Even Packed int32 to DPFP
- CVTPD2DQ — Convert Packed DPFP to Even int32
- CVTPD2PS — Convert Packed DPFP to Lo SPFP
- CVTPS2PD — Convert Lo Packed SPFP to DPFP
- CVTPD2PI — Convert Packed DPFP to int32
- CVTPI2PD — Convert Packed int32 to DPFP
- CVTSS2SI — Convert Scalar SPFP to int32/64
- CVTSD2SI — Convert Scalar DPFP to Int
- CVTSI2SD — Convert Scalar Int to DPFP
- CVTSD2SS — Convert Scalar DPFP to SPFP
- CVTSS2SD — Convert Scalar SPFP to DPFP
- Exercises
- 7. Interger Math
- General Integer Math
- Packed Addition and Subtraction
- Vector Addition and Subtraction (Fixed Point)
- Averages
- Sum of Absolute Differences
- Integer Multiplication
- Packed Integer Multiplication
- Integer Division
- Exercises
- 8. Floating-Point Anyone?
- The Floating-Point Number
- Loading/Storing Numbers and the FPU Stack
- General Math Instructions
- FCHS — FPU Two's Complement ST(0) = – ST(0)
- FABS — FPU Absolute Value ST(0) = |ST(0)|
- FADD/FADDP/FIADD — FPU Addition D = ST(0) + A
- FSUB/FSUBP/FISUB — FPU Subtraction D = ST(0) – A
- FSUBR/FSUBRP/FISUBR — FPU Reverse Subtraction D = A – ST(0)
- FMUL/FMULP/FIMUL — FPU Multiplication D = ST(0) × A
- FDIV/FDIVP/FIDIV — FPU Division D = Dst ÷ Src
- FDIVR/FDIVRP/FIDIVR — FPU Reverse Division D = Src ÷ Dst
- FPREM — FPU Partial Remainder
- FPREM1 — FPU Partial Remainder
- FRNDINT — FPU Round to Integer
- Advanced Math Instructions
- Floating-Point Comparison
- FPU BCD (Binary-Coded Decimal)
- FPU Trigonometry
- FPU System Instructions
- FINIT/FNINIT — FPU Init
- FCLEX/FNCLEX — FPU Clear Exceptions
- FFREE — FPU Free FP Register
- FSAVE/FNSAVE — FPU Save X87 FPU, MMX, SSE, SSE2
- FRSTOR — FPU Restore x87 State
- FXSAVE — FPU Save x87 FPU, MMX, SSE, SSE2, SSE3
- FXRSTOR — FPU Restore x87 FPU, MMX, SSE, SSE2, SSE3
- FSTENV/FNSTENV — FPU Store x87 Environment
- FLDENV — FPU Load x87 Environment
- FSTCW/FNSTCW — FPU Store x87 Control Word
- FLDCW — FPU Load x87 Control Word
- FSTSW/FNSTSW — FPU Store x87 Status Word
- Validating (Invalid) Floating-Point
- Exercises
- 9. Comparison
- TEST — Logical Compare A B
- Indexed Bit Testing
- SETcc — Set Byte on Condition
- Comparing Operands and Setting EFLAGS
- CMP — Packed Comparison
- Extract Packed Sign Masks
- SCAS/SCASB/SCASW/SCASD/SCASQ —Scan String
- CMOVcc — Conditional Move
- CMPXCHG — Compare and Exchange
- Boolean Operations upon Floating-Point Numbers
- ANDPS — Logical AND of Packed SPFP D = A B
- ANDPD — Logical AND of Packed DPFP
- Pseudo Vec — (XMM) FABS — FP Absolute A = | A |
- Pseudo Vec — (3DNow!) FABS — FP Absolute A = | A |
- ORPS — Logical OR of Packed SPFP D = A B
- ORPD — Logical OR of Packed DPFP
- XORPS — Logical XOR of Packed SPFP D = A B
- XORPD — Logical XOR of Packed DPFP
- Pseudo Vec — FCHS — FP Change Sign A = – A
- ANDNPS — Logical ANDC of Packed SPFP D = A (¬B)
- ANDNPD — Logical ANDC of Packed DPFP
- Min — Minimum
- Max — Maximum
- 10. Branching
- Jump Unconditionally
- Jump Conditionally
- Branch Prediction
- PAUSE — (Spin Loop Hint)
- Pancake Memory LIFO Queue
- Stack
- CALL Procedure (Function)
- Calling Conventions (Stack Argument Methods)
- Interrupt Handling
- 11. Branchless
- 12. Floating-Point Vector Addition and Subtraction
- Floating-Point Vector Addition and Subtraction
- Vector Scalar Addition and Subtraction
- Special — FP Vector Addition and Subtraction
- Exercises
- 13. FP Vector Multiplication and Division
- Floating-Point Multiplication
- Vector Scalar Multiplication
- Vector Floating-Point Division
- Exercises
- 14. Floating-Point Deux
- SQRT — Square Root
- 1×SPFP Scalar Square Root
- 4×SPFP Square Root
- 1×DPFP Scalar Square Root
- 2×DPFP Square Root
- 1×SPFP Scalar Reciprocal Square Root (15-Bit)
- Pseudo Vec
- Pseudo Vec (x86)
- SPFP Square Root (2 Stage) (24-Bit)
- vmp_FSqrt (3DNow!) Standard Float 24-Bit Precision
- Pseudo Vec
- Pseudo Vec (x86)
- Graphics 101 — Vector Magnitude (aka 3D Pythagorean Theorem)
- Pseudo Vec
- Pseudo Vec (x86)
- Vector Normalize
- SQRT — Square Root
- 15. Binary-Coded Decimal (BCD)
- 16. What CPUID?
- 17. PC I/O
- 18. System
- System "Lite"
- System Timing Instructions
- Cache Manipulation
- System Instructions
- ARPL — Adjust Requested Privilege Level
- BOUND — Check Array Index For Bounding Error
- CLTS — Clear Task Switch Flag
- HLT — Halt Processor
- UD2 — Undefined Instruction
- INVLPG — Invalidate TLB
- LAR — Load Access Rights
- LOCK — Assert Lock # Signal Prefix
- LSL — Load Segment Limit
- MOV — Move To/From Control Registers
- MOV — Move To/From Debug Registers
- STMXCSR — Save MXCSR Register State
- LDMXCSR — Load MXCSR Register State
- SGDT/SIDT — Save Global/Interrupt Descriptor Table
- LGDT/LIDT — Load Global/Interrupt Descriptor Table
- SLDT — Save Local Descriptor Table
- LLDT — Load Local Descriptor Table
- SMSW — Save Machine Status Word
- LMSW — Load Machine Status Word
- STR — Save Task Register
- LTR — Load Task Register
- RDMSR — Read from Model Specific Register
- WRMSR — Write to Model Specific Register
- SWAPGS — Swap GS Base Register
- SYSCALL — 64-Bit Fast System Call
- SYSRET — Fast Return from 64-Bit Fast System Call
- SYSENTER — Fast System Call
- SYSEXIT — Fast Return from Fast System Call
- RSM — Resume from System Management Mode
- VERR/VERW — Verify Segment for Reading
- LDS/LES/LFS/LGS/LSS — Load Far Pointer
- Hyperthreading Instructions
- 19. Gfx 'R' Asm
- 20. MASM vs. NASM vs. TASM vs. WASM
- 21. Debugging Functions
- 22. Epilogue
- A. Data Structure Definitions
- B. Mnemonics
- C. Reg/Mem Mapping
- Glossary
- References
This appendix maps the addressing methods for memory load/save, jump table lookup, and call table lookup.
The same kind of memory reference that is used to access a memory table or array can also be used to access a jump vector. Almost any register can be used alone, in a pair addition, and with an optional base address and/or scale factor of {2, 4, or 8}, but you will note that there are some limitations in regard to the ESP register.
(Real Mode — Near or far is same opcodes)(Protected Mode — Near or far is same opcodes)
jmp . . . jmp NearAdrPtr[. . .]
eax | ebx | ecx | edx | esp | ebp | esi | edi |
ax | bx | cx | dx | sp | bp | si | di |
(Real Mode — Near or far is same opcodes)(Protected Mode — Near or far is same opcodes)
jmp word ptr [. . .] jmp dword ptr [. . .] jmp fword ptr [. . .] jmp NearAdrPtr[. . .]
eax | ebx | ecx | edx | esp | ebp | esi | edi |
eax+eax | eax+ebx | eax+ecx | eax+edx | eax+esp | eax+ebp | eax+esi | eax+edi |
ebx+eax | ebx+ebx | ebx+ecx | ebx+edx | ebx+esp | ebx+ebp | ebx+esi | ebx+edi |
ecx+eax | ecx+ebx | ecx+ecx | ecx+edx | ecx+esp | ecx+ebp | ecx+esi | ecx+edi |
edx+eax | edx+ebx | edx+ecx | edx+edx | edx+esp | edx+ebp | edx+esi | edx+edi |
esp+eax | esp+ebx | esp+ecx | esp+edx | - | esp+ebp | esp+esi | esp+edi |
ebp+eax | ebp+ebx | ebp+ecx | ebp+edx | ebp+esp | ebp+ebp | ebp+esi | ebp+edi |
esi+eax | esi+ebx | esi+ecx | esi+edx | esi+esp | esi+ebp | esi+esi | esi+edi |
edi+eax | edi+ebx | edi+ecx | edi+edx | edi+esp | edi+ebp | edi+esi | edi+edi |
eax*2 | ebx*2 | ecx*2 | edx*2 | - | ebp*2 | esi*2 | edi*2 |
eax+eax*2 | eax+ebx*2 | eax+ecx*2 | eax+edx*2 | - | eax+ebp*2 | eax+esi*2 | eax+edi*2 |
ebx+eax*2 | ebx+ebx*2 | ebx+ecx*2 | ebx+edx*2 | - | ebx+ebp*2 | ebx+esi*2 | ebx+edi*2 |
ecx+eax*2 | ecx+ebx*2 | ecx+ecx*2 | ecx+edx*2 | - | ecx+ebp*2 | ecx+esi*2 | ecx+edi*2 |
edx+eax*2 | edx+ebx*2 | edx+ecx*2 | edx+edx*2 | - | edx+ebp*2 | edx+esi*2 | edx+edi*2 |
esp+eax*2 | esp+ebx*2 | esp+ecx*2 | esp+edx*2 | - | esp+ebp*2 | esp+esi*2 | esp+edi*2 |
ebp+eax*2 | ebp+ebx*2 | ebp+ecx*2 | ebp+edx*2 | - | ebp+ebp*2 | ebp+esi*2 | ebp+edi*2 |
esi+eax*2 | esi+ebx*2 | esi+ecx*2 | esi+edx*2 | - | esi+ebp*2 | esi+esi*2 | esi+edi*2 |
edi+eax*2 | edi+ebx*2 | edi+ecx*2 | edi+edx*2 | - | edi+ebp*2 | edi+esi*2 | edi+edi*2 |
eax*4 | ebx*4 | ecx*4 | edx*4 | - | ebp*4 | esi*4 | edi*4 |
eax+eax*4 | eax+ebx*4 | eax+ecx*4 | eax+edx*4 | - | eax+ebp*4 | eax+esi*4 | eax+edi*4 |
ebx+eax*4 | ebx+ebx*4 | ebx+ecx*4 | ebx+edx*4 | - | ebx+ebp*4 | ebx+esi*4 | ebx+edi*4 |
ecx+eax*4 | ecx+ebx*4 | ecx+ecx*4 | ecx+edx*4 | - | ecx+ebp*4 | ecx+esi*4 | ecx+edi*4 |
edx+eax*4 | edx+ebx*4 | edx+ecx*4 | edx+edx*4 | - | edx+ebp*4 | edx+esi*4 | edx+edi*4 |
esp+eax*4 | esp+ebx*4 | esp+ecx*4 | esp+edx*4 | - | esp+ebp*4 | esp+esi*4 | esp+edi*4 |
ebp+eax*4 | ebp+ebx*4 | ebp+ecx*4 | ebp+edx*4 | - | ebp+ebp*4 | ebp+esi*4 | ebp+edi*4 |
esi+eax*4 | esi+ebx*4 | esi+ecx*4 | esi+edx*4 | - | esi+ebp*4 | esi+esi*4 | esi+edi*4 |
edi+eax*4 | edi+ebx*4 | edi+ecx*4 | edi+edx*4 | - | edi+ebp*4 | edi+esi*4 | edi+edi*4 |
eax*8 | ebx*8 | ecx*8 | edx*8 | - | ebp*8 | esi*8 | edi*8 |
eax+eax*8 | eax+ebx*8 | eax+ecx*8 | eax+edx*8 | - | eax+ebp*8 | eax+esi*8 | eax+edi*8 |
ebx+eax*8 | ebx+ebx*8 | ebx+ecx*8 | ebx+edx*8 | - | ebx+ebp*8 | ebx+esi*8 | ebx+edi*8 |
ecx+eax*8 | ecx+ebx*8 | ecx+ecx*8 | ecx+edx*8 | - | ecx+ebp*8 | ecx+esi*8 | ecx+edi*8 |
edx+eax*8 | edx+ebx*8 | edx+ecx*8 | edx+edx*8 | - | edx+ebp*8 | edx+esi*8 | edx+edi*8 |
esp+eax*8 | esp+ebx*8 | esp+ecx*8 | esp+edx*8 | - | esp+ebp*8 | esp+esi*8 | esp+edi*8 |
ebp+eax*8 | ebp+ebx*8 | ebp+ecx*8 | ebp+edx*8 | - | ebp+ebp*8 | ebp+esi*8 | ebp+edi*8 |
esi+eax*8 | esi+ebx*8 | esi+ecx*8 | esi+edx*8 | - | esi+ebp*8 | esi+esi*8 | esi+edi*8 |
edi+eax*8 | edi+ebx*8 | edi+ecx*8 | edi+edx*8 | - | edi+ebp*8 | edi+esi*8 | edi+edi*8 |
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