B
Backside bus, centralized shared-memory multiprocessors, 351
Bandwidth See also Throughput
and cache miss, B-2 to B-3
centralized shared-memory multiprocessors, 351–352
DDR DRAMS and DIMMS, 101
DSM architecture, 379
GDRAM, 322–323
GPU computation, 327–328
GPU Memory, 327
ILP instruction fetch
basic considerations, 202–203
branch-target buffers, 203–206
integrated units, 207–208
return address predictors, 206–207
memory, and vector performance, 332
memory hierarchy, 126
performance milestones, 20
SMP limitations, 363
vector load/store units, 276–277
Banks, Fermi GPUs, 297
BARRNet See Bay Area Research Network (BARRNet)
Base field, IA-32 descriptor table, B-52 to B-53
Basic block, ILP, 149
Benchmarking
see also specific benchmark suites
desktop, 38–40
fallacies, 56
instruction set operations, A-15
as performance measurement, 37–41
real-world server considerations, 52–55
server performance, 40–41
BER See Bit error rate (BER)
Between instruction exceptions, definition, C-45
Binary-coded decimal, definition, A-14
Bing search
delays and user behavior, 451
latency effects, 450–452
WSC processor cost-performance, 473
Bisection bandwidth, WSC array switch, 443
Bit selection, block placement, B-7
Block addressing
block identification, B-7 to B-8
interleaved cache banks, 86
memory hierarchy basics, 74
Blocking calls, shared-memory multiprocessor workload, 369
Blocking factor, definition, 90
Block offset
block identification, B-7 to B-8
cache optimization, B-38
definition, B-7 to B-8
direct-mapped cache, B-9
example, B-9
main memory, B-44
Blocks See also Cache block See also Thread Block
ARM Cortex-A8, 115
vs. bytes per reference, 378
compiler optimizations, 89–90
definition, B-2
L3 cache size, misses per instruction, 371
memory hierarchy basics, 74
memory in cache, B-61
placement in main memory, B-44
uncached state, 384
BLT See Block transfer engine (BLT)
Body of Vectorized Loop
GPU Memory structure, 304
NVIDIA GPU, 296
SIMD Lane Registers, 314
Thread Block Scheduler, 314
Bose-Einstein formula, definition, 30
Bounds checking, segmented virtual memory, B-52
Branch delay slot
characteristics, C-23 to C-25
control hazards, C-41
MIPS R4000, C-64
scheduling, C-24
Branches
canceling, C-24 to C-25
delayed, C-23
delay slot, C-65
MIPS control flow instructions, A-38
MIPS operations, A-35
nullifying, C-24 to C-25
RISC instruction set, C-5
Branch folding, definition, 206
Branch hazards
basic considerations, C-21
penalty reduction, C-22 to C-25
pipeline issues, C-39 to C-42
scheme performance, C-25 to C-26
stall reduction, C-42
Branch history table, basic scheme, C-27 to C-30
Branch offsets, control flow instructions, A-18
Branch penalty
examples, 205
instruction fetch bandwidth, 203–206
reduction, C-22 to C-25
simple scheme examples, C-25
Branch prediction
accuracy, C-30
branch cost reduction, 162–167
correlation, 162–164
cost reduction, C-26
dynamic, C-27 to C-30
ideal processor, 214
ILP exploitation, 201
instruction fetch bandwidth, 205
integrated instruction fetch units, 207
misprediction rates on SPEC89, 166
static, C-26 to C-27
two-bit predictor comparison, 165
Branch stalls, MIPS R4000 pipeline, C-67
Branch-target address
branch hazards, C-42
MIPS control flow instructions, A-38
MIPS R4000, C-25
pipeline branches, C-39
RISC instruction set, C-5
Branch-target buffers
ARM Cortex-A8, 233
branch hazard stalls, C-42
example, 203
instruction fetch bandwidth, 203–206
instruction handling, 204
MIPS control flow instructions, A-38
Branch-target cache See Branch-target buffers
Buses
cache coherence, 391
centralized shared-memory multiprocessors, 351
definition, 351
Google WSC servers, 469
Bypassing See also Forwarding
data hazards requiring stalls, C-19 to C-20
dynamically scheduled pipelines, C-70 to C-71
MIPS R4000, C-65
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