H

Hadoop, WSC batch processing, 437
Half adders, J-2
Half words
aligned/misaligned addresses, A-8
memory address interpretation, A-7 to A-8
MIPS data types, A-34
operand sizes/types, 12
as operand type, A-13 to A-14
Handshaking, interconnection networks, F-10
Hard drive, power consumption, 63
Hard real-time systems, definition, E-3 to E-4
Hardware
as architecture component, 15
cache optimization, 96
compiler scheduling support, L-30 to L-31
compiler speculation support
memory references, H-32
overview, H-27
preserving exception behavior, H-28 to H-32
description notation, K-25
energy/performance fallacies, 56
for exposing parallelism, H-23 to H-27
ILP approaches, 148, 214–215
interconnection networks, F-9
pipeline hazard detection, C-38
Virtual Machines protection, 108
WSC cost-performance, 474
WSC running service, 434–435
Hardware-based speculation
basic algorithm, 191
data flow execution, 184
FP unit using Tomasulo’s algorithm, 185
ILP
data flow execution, 184
with dynamic scheduling and multiple issue, 197–202
FP unit using Tomasulo’s algorithm, 185
key ideas, 183–184
multiple-issue processors, 198
reorder buffer, 184–192
vs. software speculation, 221–222
key ideas, 183–184
Hardware faults, storage systems, D-11
Hardware prefetching
cache optimization, 131–133
miss penalty/rate reduction, 91–92
NVIDIA GPU Memory structures, 305
SPEC benchmarks, 92
Hardware primitives
basic types, 387–389
large-scale multiprocessor synchronization, I-18 to I-21
synchronization mechanisms, 387–389
Harvard architecture, L-4
Hazards See also Data hazards
branch hazards, C-21 to C-26, C-39 to C-42, C-42
control hazards, 235, C-11
detection, hardware, C-38
dynamically scheduled pipelines, C-70 to C-71
execution sequences, C-80
functional hazards, 233, 247–254
instruction set complications, C-50
longer latency pipelines, C-54 to C-58
structural hazards, 268–269, C-11, C-13 to C-16, C-71, C-78 to C-79
HCAs See Host channel adapters (HCAs)
Header
messages, F-6
packet format, F-7
switch microarchitecture pipelining, F-60
TCP/IP, F-84
Head-of-line (HOL) blocking
congestion management, F-64
switch microarchitecture, F-58 to F-59, F-59, F-60, F-62
system area network history, F-101
virtual channels and throughput, F-93
Heap, and compiler technology, A-27 to A-28
HEP processor, L-34
Heterogeneous architecture, definition, 262
Hewlett-Packard AlphaServer, F-100
Hewlett-Packard PA-RISC
addressing modes, K-5
arithmetic/logical instructions, K-11
characteristics, K-4
conditional branches, K-12, K-17, K-34
constant extension, K-9
conventions, K-13
data transfer instructions, K-10
EPIC, L-32
features, K-44
floating-point precisions, J-33
FP instructions, K-23
MIPS core extensions, K-23
multimedia support, K-18, K-18, K-19
unique instructions, K-33 to K-36
Hewlett-Packard PA-RISC MAX2, multimedia support, E-11
Hewlett-Packard Precision Architecture, integer arithmetic, J-12
Hewlett-Packard ProLiant BL10e G2 Blade server, F-85
Hewlett-Packard ProLiant SL2x170z G6, SPECPower benchmarks, 463
Hewlett-Packard RISC microprocessors, vector processor history, G-26
Higher-radix division, J-54 to J-55
Higher-radix multiplication, integer, J-48
High-level language computer architecture (HLLCA), L-18 to L-19
High-level optimizations, compilers, A-26
Highly parallel memory systems, case studies, 133–136
High-order functions, control flow instruction addressing modes, A-18
High-performance computing (HPC)
InfiniBand, F-74
interconnection network characteristics, F-20
interconnection network topology, F-44
storage area network history, F-102
switch microarchitecture, F-56
vector processor history, G-27
write strategy, B-10
vs. WSCs, 432, 435–436
Hillis, Danny, L-58, L-74
Histogram, D-26 to D-27
History file, precise exceptions, C-59
Hitachi S810, L-45, L-47
Hitachi SuperH
addressing modes, K-5, K-6
arithmetic/logical instructions, K-24
branches, K-21
characteristics, K-4
condition codes, K-14
data transfer instructions, K-23
embedded instruction format, K-8
multiply-accumulate, K-20
unique instructions, K-38 to K-39
Hit time
average memory access time, B-16 to B-17
first-level caches, 79–80
memory hierarchy basics, 77–78
reduction, 78, B-36 to B-40
way prediction, 81–82
HLLCA See High-level language computer architecture (HLLCA)
HOL See Head-of-line blocking (HOL)
Home node, directory-based cache coherence protocol basics, 382
Hop count, definition, F-30
Hops
direct network topologies, F-38
routing, F-44
switched network topologies, F-40
switching, F-50
Host channel adapters (HCAs)
historical background, L-81
switch vs. NIC, F-86
Host definition, 108, 305
Hot swapping, fault tolerance, F-67
HPC See High-performance computing (HPC)
HPC Challenge, vector processor history, G-28
HP-Compaq servers
price-performance differences, 441
SMT, 230
HPSm, L-29
Hypercube networks
characteristics, F-36
deadlock, F-47
direct networks, F-37
vs. direct networks, F-92
NEWS communication, F-43
HyperTransport, F-63
NetApp FAS6000 filer, D-42
Hypertransport, AMD Opteron cache coherence, 361
Hypervisor, characteristics, 108
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