D
Database program speculation, via multiple branches, 211
Data cache
ARM Cortex-A8, 236
cache performance, B-16
GPU Memory, 306
ISA, 241
locality principle, B-60
MIPS R4000 pipeline, C-62 to C-63
multiprogramming, 374
page level write-through, B-56
RISC processor, C-7
structural hazards, C-15
TLB, B-46
Data cache miss
applications vs. OS, B-59
cache optimization, B-25
Intel Core i7, 240
Opteron, B-12 to B-15
sizes and associativities, B-10
writes, B-10
Data cache size, multiprogramming, 376–377
Datacenters
CDF, 487
cooling systems, 449
layer 3 network example, 445
PUE statistics, 451
tier classifications, 491
vs. WSC costs, 455–456
WSC efficiency measurement, 450–452
vs. WSCs, 436
Data dependences
data hazards, 167–168
dynamically scheduling with scoreboard, C-71
hazards, 153–154
ILP, 150–152
ILP hardware model, 214–215
ILP limitation studies, 220
vector execution time, 269
Data fetching
ARM Cortex-A8, 234
directory-based cache coherence protocol example, 382–383
dynamically scheduled pipelines, C-70 to C-71
ILP, instruction bandwidth
basic considerations, 202–203
branch-target buffers, 203–206
return address predictors, 206–207
MIPS R4000, C-63
snooping coherence protocols, 355–356
Data flow execution, hardware-based speculation, 184
Datagrams See Packets
Data hazards
ARM Cortex-A8, 235
basic considerations, C-16
definition, C-11
dependences, 152–154
dynamic scheduling, 167–176
basic concept, 168–170
examples, 176–178
Tomasulo’s algorithm loop-based example, 179–181
ILP limitation studies, 220
instruction set complications, C-50 to C-51
microarchitectural techniques case study, 247–254
MIPS pipeline, C-71
RAW, C-57 to C-58
Data-level parallelism (DLP)
definition, 9
GPUs
basic considerations, 288
basic PTX thread instructions, 299
conditional branching, 300–303
coprocessor relationship, 330–331
Fermi GPU architecture innovations, 305–308
Fermi GTX 480 floorplan, 295
mapping examples, 293
Multimedia SIMD comparison, 312
multithreaded SIMD Processor block diagram, 294
NVIDIA computational structures, 291–297
NVIDIA/CUDA and AMD terminology, 313–315
NVIDIA GPU ISA, 298–300
programming, 288–291
SIMD thread scheduling, 297
terminology, 292
from ILP, 4–5
and power, 322
vector architecture
basic considerations, 264
gather/scatter operations, 279–280
multidimensional arrays, 278–279
multiple lanes, 271–273
peak performance vs. start-up overhead, 331
programming, 280–282
vector execution time, 268–271
vector-length registers, 274–275
vector load-store unit bandwidth, 276–277
vector-mask registers, 275–276
vector processor example, 267–268
VMIPS, 264–267
vector kernel implementation, 334–336
vector performance and memory bandwidth, 332
vector vs. scalar performance, 331–332
WSCs vs. servers, 433–434
Data-race-free, synchronized programs, 394
Data races, synchronized programs, 394
Data transfers
cache miss rate calculations, B-16
computer architecture, 15
instruction operators, A-15
ISA, 12–13
MIPS, addressing modes, A-34
MIPS64 instruction subset, A-40
MIPS64 ISA formats, 14
MIPS operations, A-36 to A-37
MMX, 283
multimedia instruction compiler support, A-31
operands, A-12
PTX, 305
SIMD extensions, 284
“typical” programs, A-43
VAX, B-73
vector vs. GPU, 300
Data trunks, MIPS scoreboarding, C-75
Data types
architect-compiler writer relationship, A-30
desktop computing, A-2
MIPS64 architecture, A-34
multimedia compiler support, A-31
operand types/sizes, A-14 to A-15
SIMD Multimedia Extensions, 282–283
DAXPY loop
memory bandwidth, 332
MIPS/VMIPS calculations, 267–268
peak performance vs. start-up overhead, 331
VLRs, 274–275
DDR See Double data rate (DDR)
Decimal operands, formats, A-14
DEC PDP-11, address space, B-57 to B-58
DEC VAX
address space, B-58
architect-compiler writer relationship, A-30
branch conditions, A-19
compiler writing-architecture relationship, A-30
control flow instruction branches, A-18
exceptions, C-44
extensive pipelining, C-81
flawless architecture design, A-45, K-81
high-level instruction set, A-41 to A-43
history, 2–3
immediate value distribution, A-13
instruction classes, B-73
instruction operator categories, A-15
instruction set complications, C-49 to C-50
miss rate vs. virtual addressing, B-37
operand types/sizes, A-14
operators, A-15
precise exceptions, C-59
replacement by RISC, 2
swap code, B-74, K-72, K-74
swap and register preservation, B-74 to B-75
Defect tolerance, chip fabrication cost case study, 61–62
Dell Poweredge servers, prices, 53
Dependability
integrated circuits, 33–36
memory systems, 104–105
WSC goals/requirements, 433
WSC memory, 473–474
WSC storage, 442–443
Dependences
CUDA, 290
as data dependence, 150
data hazards, 167–168
dynamically scheduled pipelines, C-70 to C-71
dynamically scheduling with scoreboard, C-71
dynamic scheduling with Tomasulo’s algorithm, 172
hardware-based speculation, 183
hazards, 153–154
ILP, 150–156
ILP hardware model, 214–215
ILP limitation studies, 220
MIPS scoreboarding, C-79
as program properties, 152
and Tomasulo’s algorithm, 170
types, 150
vector execution time, 269
vector mask registers, 275–276
VMIPS, 268
Descriptor privilege level (DPL), segmented virtual memory, B-53
Descriptor table, IA-32, B-52
Desktop computers
characteristics, 6
compiler structure, A-24
as computer class, 5
memory hierarchy basics, 78
multiprocessor importance, 344
performance benchmarks, 38–40
processor comparison, 242
Destination offset, IA-32 segment, B-53
Dies
Nehalem floorplan, 30
Die yield, basic equation, 30–31
Digital Alpha
branches, A-18
Digital Alpha processors
control flow instruction branches, A-18
displacement addressing mode, A-12
exception stopping/restarting, C-47
immediate value distribution, A-13
MIPS precise exceptions, C-59
shared-memory workload, 367–369
DIMMs See Dual inline memory modules (DIMMs)
Direct-mapped cache
address parts, B-9
address translation, B-38
block placement, B-7
memory hierarchy basics, 74
memory hierarchy, B-48
optimization, 79–80
Directory-based cache coherence
advanced directory protocol case study, 420–426
basic considerations, 378–380
case study, 418–420
definition, 354
distributed-memory multiprocessor, 380
latencies, 425
protocol basics, 380–382
protocol example, 382–386
state transition diagram, 383
Displacement addressing mode
basic considerations, A-10
MIPS, 12
MIPS data transfers, A-34
MIPS instruction format, A-35
value distributions, A-12
Distributed shared memory (DSM)
basic considerations, 378–380
multichip multicore multiprocessor, 419
snooping coherence protocols, 355
DLP See Data-level parallelism (DLP)
DMA See Direct memory access (DMA)
DOR See Dimension-order routing (DOR)
Double data rate (DDR)
ARM Cortex-A8, 117
DRAM performance, 100
DRAMs and DIMMS, 101
Google WSC servers, 468–469
Intel Core i7, 121
SDRAMs, 101
Double data rate 2 (DDR2), SDRAM timing diagram, 139
Double data rate 4 (DDR4), DRAM, 99
Double data rate 5 (DDR5), GDRAM, 102
Double-precision floating point
add-divide, C-68
AVX for x86, 284
data access benchmarks, A-15
Fermi GPU architecture, 306
floating-point pipeline, C-65
IBM 360, 171
MIPS data transfers, A-34
Multimedia SIMD vs. GPUs, 312
operand sizes/types, 12
as operand type, A-13 to A-14
operand usage, 297
pipeline timing, C-54
SIMD Extensions, 283
Double words
aligned/misaligned addresses, A-8
data access benchmarks, A-15
memory address interpretation, A-7 to A-8
MIPS data types, A-34
stride, 278
DPL See Descriptor privilege level (DPL)
DRAM See Dynamic random-access memory (DRAM)
Driver domains, Xen VM, 111
DSM See Distributed shared memory (DSM)
DSP See Digital signal processor (DSP)
DSS See Decision support system (DSS)
Dual inline memory modules (DIMMs)
clock rates, bandwidth, names, 101
DRAM basics, 99
Google WSC server, 467
Google WSC servers, 468–469
graphics memory, 322–323
SDRAMs, 101
WSC memory, 473–474
Dual SIMD Thread Scheduler, example, 305–306
Dynamically shared libraries, control flow instruction addressing modes, A-18
Dynamic energy, definition, 23
Dynamic random-access memory (DRAM)
bandwidth issues, 322–323
characteristics, 98–100
clock rates, bandwidth, names, 101
cost trends, 27
CUDA, 290
dependability, 104
Flash memory, 103–104
Google WSC servers, 468–469
GPU SIMD instructions, 296
improvement over time, 17
integrated circuit costs, 28
Intel Core i7, 121
internal organization, 98
memory performance, 100–102
multibanked caches, 86
NVIDIA GPU Memory structures, 305
performance milestones, 20
power consumption, 63
real-world server considerations, 52–55
Roofline model, 286
server energy savings, 25
speed trends, 99
technology trends, 17
WSC efficiency measurement, 450
WSC memory costs, 473–474
WSC memory hierarchy, 444–445
WSC power modes, 472
yield, 32
Dynamic scheduling
ILP
basic concept, 168–169
definition, 168
example and algorithms, 176–178
with multiple issue and speculation, 197–202
overcoming data hazards, 167–176
MIPS scoreboarding, C-79
SMT on superscalar processors, 230
and unoptimized code, C-81
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