C
Cache bandwidth
caches, 78
multibanked caches, 85–86
nonblocking caches, 83–85
pipelined cache access, 82
Cache block
cache coherence protocol, 357–358
compiler optimizations, 89–90
critical word first, 86–87
definition, B-2
false sharing, 366
GPU comparisons, 329
inclusion, 397–398
memory block, B-61
miss categories, B-26
miss rate reduction, B-26 to B-28
way prediction, 81
write invalidate protocol implementation, 356–357
write strategy, B-10
Cache coherence
advanced directory protocol case study, 420–426
basic considerations, 112–113
directory-based See Directory-based cache coherence
enforcement, 354–355
extensions, 362–363
hardware primitives, 388
latency hiding with speculation, 396
lock implementation, 389–391
mechanism, 358
memory hierarchy basics, 75
multiprocessor-optimized software, 409
multiprocessors, 352–353
protocol definitions, 354–355
single-chip multicore processor case study, 412–418
single memory location example, 352
snooping See Snooping cache coherence
state diagram, 361
steps and bus traffic examples, 391
write-back cache, 360
Cache definition, B-2
Cache latency, nonblocking cache, 83–84
Cache miss
and average memory access time, B-17 to B-20
block replacement, B-10
definition, B-2
example calculations, 83–84
Intel Core i7, 122
nonblocking cache, 84
single vs. multiple thread executions, 228
Cache optimizations
basic categories, B-22
basic optimizations, B-40
case studies, 131–133
compiler-controlled prefetching, 92–95
compiler optimizations, 87–90
critical word first, 86–87
energy consumption, 81
hit time reduction, B-36 to B-40
miss categories, B-23 to B-26
miss rate reduction
via associativity, B-28 to B-30
via block size, B-26 to B-28
via cache size, B-28
overview, 78–79
pipelined cache access, 82
simple first-level caches, 79–80
techniques overview, 96
way prediction, 81–82
Cache performance
average memory access time, B-16 to B-20
basic equations, B-22
basic optimizations, B-40
cache optimization, 96
case study, 131–133
example calculation, B-16 to B-17
out-of-order processors, B-20 to B-22
prediction, 125–126
Cache prefetch, cache optimization, 92
Caches See also Memory hierarchy
access time vs. block size, B-28
basic considerations, B-48 to B-49
definition, B-2
Fermi GPU architecture, 306
ideal processor, 214
ILP for realizable processors, 216–218
multichip multicore multiprocessor, 419
parameter ranges, B-42
vs. virtual memory, B-42 to B-43
Cache size
and access time, 77
AMD Opteron example, B-13 to B-14
energy consumption, 81
highly parallel memory systems, 133
memory hierarchy basics, 76
miss rate, B-24 to B-25
vs. miss rate, B-27
miss rate reduction, B-28
multilevel caches, B-33
and relative execution time, B-34
shared-memory multiprogramming workload, 376
virtually addressed, B-37
Caller saving, control flow instructions, A-19 to A-20
Calls
compiler structure, A-25 to A-26
CUDA Thread, 297
dependence analysis, 321
high-level instruction set, A-42 to A-43
invocation options, A-19
ISAs, 14
MIPS control flow instructions, A-38
MIPS registers, 12
multiprogrammed workload, 378
NVIDIA GPU Memory structures, 304–305
return address predictors, 206
shared-memory multiprocessor workload, 369
user-to-OS gates, B-54
Canceling branch, branch delay slots, C-24 to C-25
Canonical form, AMD64 paged virtual memory, B-55
Capacity misses
blocking, 89–90
and cache size, B-24
definition, B-23
memory hierarchy basics, 75
shared-memory workload, 373
CAPEX See Capital expenditures (CAPEX)
CAS See Column access strobe (CAS)
Case studies
advanced directory protocol, 420–426
cache optimization, 131–133
chip fabrication cost, 61–62
computer system power consumption, 63–64
directory-based coherence, 418–420
highly parallel memory systems, 133–136
instruction set principles, A-47 to A-54
memory hierarchy, B-60 to B-67
microarchitectural techniques, 247–254
pipelining example, C-82 to C-88
single-chip multicore processor, 412–418
vector kernel on vector processor and GPU, 334–336
WSC resource allocation, 478–479
WSC TCO, 476–478
CCD See Charge-coupled device (CCD)
C/C++ language
hardware impact on software development, 4
NVIDIA GPU programming, 289
return address predictors, 206
CDB See Common data bus (CDB)
CDC See Control Data Corporation (CDC)
CDF, datacenter, 487
CDMA See Code division multiple access (CDMA)
Centralized shared-memory multiprocessors
basic considerations, 351–352
cache coherence, 352–353
cache coherence enforcement, 354–355
cache coherence example, 357–362
cache coherence extensions, 362–363
invalidate protocol implementation, 356–357
SMP and snooping limitations, 363–364
snooping coherence implementation, 365–366
snooping coherence protocols, 355–356
Central processing unit (CPU)
Amdahl’s law, 48
average memory access time, B-17
cache performance, B-4
coarse-grained multithreading, 224
exception stopping/restarting, C-47
extensive pipelining, C-81
Google server usage, 440
vs. GPUs, 288
instruction set complications, C-50
MIPS implementation, C-33 to C-34
MIPS precise exceptions, C-59 to C-60
MIPS scoreboarding, C-77
pipeline branch issues, C-41
pipelining exceptions, C-43 to C-46
pipelining performance, C-10
SPEC server benchmarks, 40
Central processing unit (CPU) time
execution time, 36
modeling, B-18
processor performance calculations, B-19 to B-21
processor performance equation, 49–51
processor performance time, 49
CFM See Current frame pointer (CFM)
Channel adapter See Network interface
Chime
definition, 309
GPUs vs. vector architectures, 308
multiple lanes, 272
NVIDIA GPU computational structures, 296
vector execution time, 269, G-4
vector sequence calculations, 270
CIFS See Common Internet File System (CIFS)
CLA See Carry-lookahead adder (CLA)
Clean block, definition, B-11
Climate Savers Computing Initiative, power supply efficiencies, 462
Clock cycles
basic MIPS pipeline, C-34 to C-35
and branch penalties, 205
cache performance, B-4
FP pipeline, C-66
and full associativity, B-23
GPU conditional branching, 303
ILP exposure, 157
instruction fetch bandwidth, 202–203
instruction steps, 173–175
Intel Core i7 branch predictor, 166
MIPS exceptions, C-48
MIPS pipeline, C-52
MIPS pipeline FP operations, C-52 to C-53
MIPS scoreboarding, C-77
miss rate calculations, B-31 to B-32
multithreading approaches, 225–226
pipelining performance, C-10
processor performance equation, 49
RISC classic pipeline, C-7
Sun T1 multithreading, 226–227
vector execution time, 269
vector multiple lanes, 271–273
VLIW processors, 195
Clock cycles per instruction (CPI)
addressing modes, A-10
ARM Cortex-A8, 235
cache behavior impact, B-18 to B-19
cache hit calculation, B-5
data hazards requiring stalls, C-20
extensive pipelining, C-81
floating-point calculations, 50–52
ILP exploitation, 192
MIPS R4000 performance, C-69
miss penalty reduction, B-32
multiprocessing/multithreading-based performance, 398–400
multiprocessor communication calculations, 350
pipeline branch issues, C-41
pipeline with stalls, C-12 to C-13
pipeline structural hazards, C-15 to C-16
pipelining concept, C-3
processor performance calculations, 218–219
processor performance time, 49–51
and processor speed, 244
shared-memory workloads, 369–370
simple MIPS implementation, C-33 to C-34
structural hazards, C-13
Sun T1 multithreading unicore performance, 229
Sun T1 processor, 399
Tomasulo’s algorithm, 181
Clock cycle time
and associativity, B-29
average memory access time, B-21 to B-22
cache performance, B-4
MIPS implementation, C-34
miss penalties, 219
pipelining, C-3
Clock periods, processor performance equation, 48–49
Clock rate
DDR DRAMS and DIMMS, 101
ILP for realizable processors, 218
Intel Core i7, 236–237
microprocessors, 24
MIPS pipeline FP operations, C-53
multicore processor performance, 400
and processor speed, 244
Clocks, processor performance equation, 48–49
Clock skew, pipelining performance, C-10
Clusters
characteristics, 8, I-45
cloud computing, 345
as computer class, 5
Google WSC servers, 469
Internet Archive Cluster See Internet Archive Cluster
outage/anomaly statistics, 435
as WSC forerunners, 435–436, L-72 to L-73
WSC storage, 442–443
CMOS
DRAM, 99
Coarse-grained multithreading, definition, 224–226
Code generation
dependences, 220
general-purpose register computers, A-6
ILP limitation studies, 220
loop unrolling/scheduling, 162
Code size
architect-compiler considerations, A-30
benchmark information, A-2
comparisons, A-44
flawless architecture design, A-45
instruction set encoding, A-22 to A-23
ISA and compiler technology, A-43 to A-44
loop unrolling, 160–161
multiprogramming, 375–376
PMDs, 6
RISCs, A-23 to A-24
VAX design, A-45
VLIW model, 195–196
Coherence See Cache coherence
Cold-start misses, definition, B-23
Collision misses, definition, B-23
Column access strobe (CAS), DRAM, 98–99
Commercial workloads
execution time distribution, 369
symmetric shared-memory multiprocessors, 367–374
Commodities
Amazon Web Services, 456–457
array switch, 443
cloud computing, 455
cost vs. price, 32–33
Ethernet rack switch, 442
HPC hardware, 436
shared-memory multiprocessor, 441
WSCs, 441
Common data bus (CDB)
FP unit with Tomasulo’s algorithm, 185
reservation stations/register tags, 177
Communication subnets See Interconnection networks
Communication subsystems See Interconnection networks
Compiler-controlled prefetching, miss penalty/rate reduction, 92–95
Compiler optimizations
blocking, 89–90
cache optimization, 131–133
compiler assumptions, A-25 to A-26
and consistency model, 396
loop interchange, 88–89
miss rate reduction, 87–90
passes, A-25
performance impact, A-27
types and classes, A-28
Compiler techniques
ILP exposure, 156–162
Compiler technology
and architecture decisions, A-27 to A-29
ISA and code size, A-43 to A-44
multimedia instruction support, A-31 to A-32
register allocation, A-26 to A-27
Compiler writer-architect relationship, A-29 to A-30
Compulsory misses
and cache size, B-24
definition, B-23
memory hierarchy basics, 75
shared-memory workload, 373
Computer aided design (CAD) tools, cache optimization, 79–80
Computer architecture See also Architecture
computer design innovations, 4
defining, 11
exceptions, C-44
factors in improvement, 2
ISA, 11–15
multiprocessor software development, 407–409
parallel, 9–10
Computer arithmetic
Computer classes
desktops, 6
embedded computers, 8–9
example, 5
overview, 5
parallelism and parallel architectures, 9–10
PMDs, 6
servers, 7
warehouse-scale computers, 8
Computer design principles
Amdahl’s law, 46–48
common case, 45–46
parallelism, 44–45
principle of locality, 45
processor performance equation, 48–52
Computer history, technology and architecture, 2–5
Computer room air-conditioning (CRAC), WSC infrastructure, 448–449
Compute Unified Device Architecture See CUDA (Compute Unified Device Architecture)
Conditional branches
branch folding, 206
compare frequencies, A-20
compiler performance, C-24 to C-25
evaluation, A-19
GPUs, 300–303
ideal processor, 214
ISAs, A-46
predictor misprediction rates, 166
PTX instruction set, 298–299
static branch prediction, C-26
types, A-20
vector-GPU comparison, 311
Condition codes
branch conditions, A-19
control flow instructions, 14
definition, C-5
high-level instruction set, A-43
instruction set complications, C-50
pipeline branch penalties, C-23
Conflict misses
and block size, B-28
cache coherence mechanism, 358
definition, B-23
as kernel miss, 376
L3 caches, 371
memory hierarchy basics, 75
OLTP workload, 370
PIDs, B-37
shared-memory workload, 373
Consistency See Memory consistency
Control Data Corporation (CDC) 6600
dynamically scheduling with scoreboard, C-71 to C-72
Control Data Corporation (CDC) STAR-100
peak performance vs. start-up overhead, 331
Control dependences
as data dependence, 150
hardware-based speculation, 183
ILP, 154–156
ILP hardware model, 214
and Tomasulo’s algorithm, 170
vector mask registers, 275–276
Control flow instructions
addressing modes, A-17 to A-18
classes, A-17
conditional branch options, A-19
hardware vs. software speculation, 221
ISAs, 14
procedure invocation options, A-19 to A-20
Control instructions
VAX, B-73
Control Processor
definition, 309
GPUs, 333
SIMD, 10
Thread Block Scheduler, 294
vector unit structure, 273
Conventional datacenters, vs. WSCs, 436
Convoy
vector execution time, 269–270
Core definition, 15
Correlating branch predictors, branch costs, 162–163
Cost
Amazon EC2, 458
Amazon Web Services, 457
chip fabrication case study, 61–62
cloud computing providers, 471–472
memory hierarchy design, 72
multiprocessor cost relationship, 409
multiprocessor linear speedup, 407
PMDs, 6
server usage, 7
speculation, 210
tournament predictors, 164–166
WSC array switch, 443
WSC vs. datacenters, 455–456
WSC efficiency, 450–452
WSC facilities, 472
WSC network bottleneck, 461
WSCs vs. servers, 434
WSC TCO case study, 476–478
Cost associativity, cloud computing, 460–461
Cost-performance
computer trends, 3
extensive pipelining, C-80 to C-81
IBM eServer p5 processor, 409
WSC Flash memory, 474–475
WSC goals/requirements, 433
WSC hardware inactivity, 474
WSC processors, 472–473
Cost trends
integrated circuits, 28–32
manufacturing vs. operation, 33
overview, 27
vs. price, 32–33
time, volume, commoditization, 27–28
CPA See Carry-propagate adder (CPA)
CPU See Central processing unit (CPU)
Cray T90, memory bank calculations, 276
Cray X1
peak performance, 58
CRC See Cyclic redundancy check (CRC)
Critical word first, cache optimization, 86–87
Crossbars
VMIPS, 265
C# language, hardware impact on software development, 4
CSSU See Compare-select-store unit (CSSU)
CUDA (Compute Unified Device Architecture)
GPU conditional branching, 303
GPUs vs. vector architectures, 310
NVIDIA GPU programming, 289
sample program, 289–290
SIMD instructions, 297
terminology, 313–315
CUDA Thread
definitions and terms, 314
GPU data addresses, 310
GPU Memory structures, 304
NVIDIA parallelism, 289–290
vs. POSIX Threads, 297
PTX Instructions, 298
SIMD Instructions, 303
Thread Block, 313
CWS See Circulating water system (CWS)
CYBER 180/990, precise exceptions, C-59
Cycles, processor performance equation, 49
Cycle time See also Clock cycle time
CPI calculations, 350
pipelining, C-81
scoreboarding, C-79
vector processors, 277
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