M
MAC See Multiply-accumulate (MAC)
Machine memory, Virtual Machines, 110
Macro-op fusion, Intel Core i7, 237–238
Main Memory
addressing modes, A-10
address translation, B-46
block placement, B-44
cache function, B-2
coherence protocol, 362
DRAM, 17
gather-scatter, 329
GPU vs. MIMD, 327
GPUs and coprocessors, 330
GPU threads, 332
ILP considerations, 245
interlane wiring, 273
linear speedups, 407
memory hierarchy basics, 76
memory hierarchy design, 72
memory mapping, B-42
MIPS operations, A-36
Multimedia SIMD vs. GPUs, 312
multiprocessor cache coherence, 352
paging vs. segmentation, B-43
partitioning, B-50
processor performance calculations, 218–219
RISC code size, A-23
server energy efficiency, 462
symmetric shared-memory multiprocessors, 363
virtual memory block identification, B-44 to B-45
virtual memory writes, B-45 to B-46
VLIW, 196
write-back, B-11
write process, B-45
Manufacturing cost
chip fabrication case study, 61–62
cost trends, 27
modern processors, 62
vs. operation cost, 33
MapReduce
cloud computing, 455
Google usage, 437
reductions, 321
WSC batch processing, 437–438
WSC cost-performance, 474
Mask Registers
basic operation, 275–276
definition, 309
Multimedia SIMD, 283
NVIDIA GPU computational structures, 291
vector compilers, 303
vector vs. GPU, 311
VMIPS, 267
M-bus See Memory bus (M-bus)
Mean time to failure (MTTF)
computer system power consumption case study, 63–64
example calculations, 34–35
SLA states, 34
WSCs vs. servers, 434
Memory access
ARM Cortex-A8 example, 117
basic MIPS pipeline, C-36
vs. block size, B-28
cache hit calculation, B-5 to B-6
data hazards requiring stalls, C-19 to C-21
exception stopping/restarting, C-46
hazards and forwarding, C-56 to C-57
instruction set complications, C-49
integrated instruction fetch units, 208
MIPS data transfers, A-34
MIPS exceptions, C-48 to C-49
MIPS pipeline control, C-37 to C-39
MIPS R4000, C-65
multimedia instruction compiler support, A-31
shared-memory workloads, 372
simple MIPS implementation, C-32 to C-33
simple RISC implementation, C-6
structural hazards, C-13 to C-14
Memory addressing
ALU immediate operands, A-12
basic considerations, A-11 to A-13
displacement values, A-12
immediate value distribution, A-13
interpretation, A-7 to A-8
ISA, 11
Memory banks See also Banked memory
gather-scatter, 280
multiprocessor architecture, 347
parallelism, 45
shared-memory multiprocessors, 363
strides, 279
vector load/store unit bandwidth, 276–277
Memory consistency
basic considerations, 392–393
cache coherence, 352
compiler optimization, 396
directory-based cache coherence protocol basics, 382
multiprocessor cache coherency, 353
relaxed consistency models, 394–395
single-chip multicore processor case study, 412–418
speculation to hide latency, 396–397
Memory hierarchy
address space, B-57 to B-58
basic questions, B-6 to B-12
block identification, B-7 to B-9
block placement issues, B-7
block replacement, B-9 to B-10
cache optimization
basic categories, B-22
basic optimizations, B-40
hit time reduction, B-36 to B-40
miss categories, B-23 to B-26
miss rate reduction
via associativity, B-28 to B-30
via block size, B-26 to B-28
via cache size, B-28
pipelined cache access, 82
cache performance, B-3 to B-6
average memory access time, B-17 to B-20
basic considerations, B-16
basic equations, B-22
example calculation, B-16
out-of-order processors, B-20 to B-22
case studies, B-60 to B-67
inclusion, 397–398
levels in slow down, B-3
Opteron L1/L2, B-57
OS and page size, B-58
overview, B-39
Pentium vs. Opteron protection, B-57
processor examples, B-3
process protection, B-50
terminology, B-2 to B-3
virtual memory
basic questions, B-44 to B-46
fast address translation, B-46
overview, B-48
paged example, B-54 to B-57
page size selection, B-46 to B-47
segmented example, B-51 to B-54
write strategy, B-10 to B-12
Memory hierarchy design
access times, 77
Alpha 21264 floorplan, 143
cache coherency, 112–113
cache optimization
case study, 131–133
compiler-controlled prefetching, 92–95
compiler optimizations, 87–90
critical word first, 86–87
energy consumption, 81
overview, 78–79
pipelined cache access, 82
techniques overview, 96
way prediction, 81–82
cache performance prediction, 125–126
cache size and misses per instruction, 126
DDR2 SDRAM timing diagram, 139
highly parallel memory systems, 133–136
high memory bandwidth, 126
instruction miss benchmarks, 127
instruction simulation, 126
Intel Core i7 three-level cache hierarchy, 118
Intel Core i7 TLB structure, 118
Intel 80x86 virtualization issues, 128
memory basics, 74–78
overview, 72–74
protection and ISA, 112
server vs. PMD, 72
system call virtualization/paravirtualization performance, 141
virtual machine monitor, 108–109
Virtual Machines ISA support, 109–110
Virtual Machines protection, 107–108
Virtual Machines and virtual memory and I/O, 110–111
virtual memory protection, 105–107
VMM on nonvirtualizable ISA, 128–129
Xen VM example, 111
Memory mapping
memory hierarchy, B-48 to B-49
segmented virtual memory, B-52
TLBs, 323
virtual memory definition, B-42
Memory protection
control dependence, 155
Pentium vs. Opteron, B-57
processes, B-50
safe calls, B-54
segmented virtual memory example, B-51 to B-54
virtual memory, B-41
Memory stall cycles
average memory access time, B-17
definition, B-4 to B-5
miss rate calculation, B-6
out-of-order processors, B-20 to B-21
performance equations, B-22
Memory system
cache optimization, B-36
coherency, 352–353
computer architecture, 15
C program evaluation, 134–135
dependability enhancement, 104–105
gather-scatter, 280
GDRAMs, 323
GPUs, 332
latency, B-21
MIPS, C-33
multiprocessor architecture, 347
multiprocessor cache coherence, 352
multiprogramming workload, 377–378
page size changes, B-58
price/performance/power considerations, 53
RISC, C-7
Roofline model, 286
shared-memory multiprocessors, 363
SMT, 399–400
stride handling, 279
T1 multithreading unicore performance, 227
Memory technology basics
DRAM and DIMM characteristics, 101
DRAM performance, 100–102
Flash memory, 102–104
overview, 96–97
performance trends, 20
SRAM, 97–98
Messages
coherence maintenance, 381
Microarchitecture
as architecture component, 15–16
ARM Cortex-A8, 241
data hazards, 168
ILP exploitation, 197
Intel Core i7, 236–237
Nehalem, 411
out-of-order example, 253
PTX vs. x86, 298
switches See Switch microarchitecture
techniques case study, 247–254
Microfusion, Intel Core i7 micro-op buffer, 238
Microprocessor overview
clock rate trends, 24
cost trends, 27–28
desktop computers, 6
embedded computers, 8–9
energy and power, 23–26
integrated circuit improvements, 2
and Moore’s law, 3–4
power and energy system trends, 21–23
technology trends, 18
Microprocessor without Interlocked Pipeline Stages See MIPS (Microprocessor without Interlocked Pipeline Stages)
Microsoft Azure, 456, L-74
Microsoft Windows
benchmarks, 38
multithreading, 223
time/volume/commoditization impact, 28
WSC workloads, 441
Migration, cache coherent multiprocessors, 354
MIMD (Multiple Instruction Streams, Multiple Data Streams)
and Amdahl’s law, 406–407
definition, 10
GPU programming, 289
GPUs vs. vector architectures, 310
with Multimedia SIMD, vs. GPU, 324–330
multiprocessor architecture, 346–348
speedup via parallelism, 263
TLP, basic considerations, 344–345
Minicomputers, replacement by microprocessors, 3–4
MIPS (Microprocessor without Interlocked Pipeline Stages)
addressing modes, 11–12
basic pipeline, C-34 to C-36
branch predictor correlation, 163
cache performance, B-6
control flow instructions, 14
data dependences, 151
data hazards, 169
encoding, 14
exception stopping/restarting, C-46 to C-47
FP unit with Tomasulo’s algorithm, 173
hazard checks, C-71
ILP, 149
ILP exposure, 157–158
ILP hardware model, 215
instruction set complications, C-49 to C-51
ISA class, 11
ISA example
addressing modes for data transfer, A-34
arithmetic/logical instructions, A-37
basic considerations, A-32 to A-33
data types, A-34
FP operations, A-38 to A-39
instruction format, A-35
load-store instructions, A-36
MIPS operations, A-35 to A-37
registers, A-34
usage, A-39
Livermore Fortran kernel performance, 331
memory addressing, 11
multicycle operations
basic considerations, C-51 to C-54
hazards and forwarding, C-54 to C-58
precise exceptions, C-58 to C-60
operands, 12
pipeline branch issues, C-39 to C-42
pipeline control, C-36 to C-39
pipe stage, C-37
processor performance calculations, 218–219
registers and usage conventions, 12
RISC code size, A-23
scoreboard components, C-76
scoreboarding, C-72
unpipelined functional units, C-52
write strategy, B-10
MIPS16
RISC code size, A-23
MIPS R4000
integer pipeline, C-63
pipeline overview, C-61 to C-65
pipeline performance, C-67 to C-70
pipeline structure, C-62 to C-63
MIPS R8000, precise exceptions, C-59
Misprediction rate
branch-prediction buffers, C-29
predictors on SPEC89, 166
profile-based predictor, C-27
SPECCPU2006 benchmarks, 167
Mispredictions
branch-target buffers, 205
hardware-based speculation, 190
hardware vs. software speculation, 221
integer vs. FP programs, 212
Intel Core i7, 237
prediction buffers, C-29
static branch prediction, C-26 to C-27
Misses per instruction
application/OS statistics, B-59
cache performance, B-5 to B-6
cache protocols, 359
cache size effect, 126
L3 cache block size, 371
memory hierarchy basics, 75
performance impact calculations, B-18
shared-memory workloads, 372
SPEC benchmarks, 127
strided access-TLB interactions, 323
Miss penalty
average memory access time, B-16 to B-17
compiler-controlled prefetching, 92–95
critical word first, 86–87
hardware prefetching, 91–92
ILP speculative execution, 223
memory hierarchy basics, 75–76
nonblocking cache, 83
out-of-order processors, B-20 to B-22
processor performance calculations, 218–219
reduction via multilevel caches, B-30 to B-35
write buffer merging, 87
Miss rate
AMD Opteron data cache, B-15
ARM Cortex-A8, 116
basic categories, B-23
vs. block size, B-27
cache optimization, 79
and associativity, B-28 to B-30
and block size, B-26 to B-28
and cache size, B-28
cache performance, B-4
and cache size, B-24 to B-25
compiler-controlled prefetching, 92–95
compiler optimizations, 87–90
hardware prefetching, 91–92
memory hierarchy basics, 75–76
multilevel caches, B-33
processor performance calculations, 218–219
shared-memory workload, 370–373
single vs. multiple thread executions, 228
Sun T1 multithreading unicore performance, 228
vs. virtual addressed cache size, B-37
MIU See Mesh interface unit (MIU)
MMX See Multimedia Extensions (MMX)
Modified-Exclusive-Shared-Invalid (MESI) protocol, characteristics, 362
Modified-Owned-Exclusive-Shared-Invalid (MOESI) protocol, characteristics, 362
Modified state
coherence protocol, 362
directory-based cache coherence protocol basics, 380
snooping coherence protocol, 358–359
Module availability, definition, 34
Module reliability, definition, 34
Moore’s law
DRAM, 100
flawed architectures, A-45
and microprocessor dominance, 3–4
RISC, A-3
software importance, 55
technology trends, 17
Mortar shot graphs, multiprocessor performance measurement, 405–406
MPI See Message Passing Interface (MPI)
MPPs See Massively parallel processors (MPPs)
MSP See Multi-Streaming Processor (MSP)
MTBF See Mean time between failures (MTBF)
MTDL See Mean time until data loss (MTDL)
MTTF See Mean time to failure (MTTF)
MTTR See Mean time to repair (MTTR)
Multicore processors
architecture goals/requirements, 15
cache coherence, 361–362
centralized shared-memory multiprocessor structure, 347
directory-based cache coherence, 380
multiprocessors, 345
performance gains, 398–400
performance milestones, 20
single-chip case study, 412–418
and SMT, 404–405
snooping cache coherence implementation, 365
SPEC benchmarks, 402
uniform memory access, 364
write invalidate protocol implementation, 356–357
Multicycle operations, MIPS pipeline
basic considerations, C-51 to C-54
hazards and forwarding, C-54 to C-58
precise exceptions, C-58 to C-60
Multilevel caches
cache optimizations, B-22
centralized shared-memory architectures, 351
memory hierarchy basics, 76
miss penalty reduction, B-30 to B-35
miss rate vs. cache size, B-33
Multimedia SIMD vs. GPU, 312
performance equations, B-22
purpose, 397
write process, B-11
Multilevel exclusion, definition, B-35
Multimedia applications
GPUs, 288
ISA support, A-46
MIPS FP operations, A-39
vector architectures, 267
Multimedia Extensions (MMX)
compiler support, A-31
SIMD history, 262, L-50
vs. vector architectures, 282–283
Multimedia SIMD Extensions
compiler support, A-31
DLP, 322
vs. GPUs, 312
MIMD, vs. GPU, 324–330
parallelism classes, 10
programming, 285
256-bit-wide operations, 282
vs. vector, 263–264
Multimedia user interfaces, PMDs, 6
Multiple Instruction Streams, Multiple Data Streams See MIMD (Multiple Instruction Streams, Multiple Data Streams)
Multiple Instruction Streams, Single Data Stream (MISD), definition, 10
Multiple-issue processors
basic VLIW approach, 193–196
with dynamic scheduling and speculation, 197–202
instruction fetch bandwidth, 202–203
integrated instruction fetch units, 207
loop unrolling, 162
microarchitectural techniques case study, 247–254
primary approaches, 194
with speculation, 198
Tomasulo’s algorithm, 183
Multiple lanes technique
vector instruction set, 271–273
Multiple paths, ILP limitation studies, 220
Multiprocessor basics
architectural issues and approaches, 346–348
architecture goals/requirements, 15
architecture and software development, 407–409
basic hardware primitives, 387–389
cache coherence, 352–353
communication calculations, 350
computer categories, 10
consistency models, 395
definition, 345
fallacies, 55
locks via coherence, 389–391
low-to-high-end roles, 344–345
parallel processing challenges, 349–351
for performance gains, 398–400
performance trends, 21
point-to-point example, 413
shared-memory See Shared-memory multiprocessors
Multiprogramming
definition, 345
multithreading, 224
performance, 36
shared-memory workloads, 374–375
software optimization, 408
workload execution time, 375
Multithreaded SIMD Processor
block diagram, 294
Fermi GPU architectural innovations, 305–308
Fermi GPU block diagram, 307
GPU programming, 289–290
Grid mapping, 293
NVIDIA GPU computational structures, 291
Roofline model, 326
Multithreading
coarse-grained, 224–226
definition and types, 223–225
fine-grained, 224–226
GPU programming, 289
ILP, 223–232
memory hierarchy basics, 75–76
for performance gains, 398–400
Sun T1 effectiveness, 226–229
MVL See Maximum vector length (MVL)
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