E
Early restart, miss penalty reduction, 86
EBS See Elastic Block Storage (EBS)
ECC See Error-Correcting Code (ECC)
EEPROM (Electronically Erasable Programmable Read-Only Memory)
compiler-code size considerations, A-44
Flash Memory, 102–104
memory hierarchy design, 72
Effective address
data dependences, 152
definition, A-9
load interlocks, C-39
RISC instruction set, C-4 to C-5
simple MIPS implementation, C-31 to C-32
TLB, B-49
Eight-way set associativity
ARM Cortex-A8, 114
cache optimization, B-29
conflict misses, B-23
data cache misses, B-10
Elapsed time, execution time, 36
Electronically Erasable Programmable Read-Only Memory See EEPROM (Electronically Erasable Programmable Read-Only Memory)
Electronic Design News Embedded Microprocessor Benchmark Consortium (EEMBC)
ISA code size, A-44
performance benchmarks, 38
Element group, definition, 272
Embedded systems
characteristics, 8–9, E-4
as computer class, 5
Encoding
control flow instructions, A-18
erasure encoding, 439
MIPS ISA, A-33
MIPS pipeline, C-36
opcode, A-13
VLIW model, 195–196
Energy efficiency See also Power consumption
Climate Savers Computing Initiative, 462
hardward fallacies, 56
ILP exploitation, 201
Intel Core i7, 401–405
ISA, 241–243
microprocessor, 23–26
PMDs, 6
processor performance equation, 52
servers, 25
and speculation, 211–212
system trends, 21–23
WSC, measurement, 450–452
WSC goals/requirements, 433
WSC infrastructure, 447–449
WSC servers, 462–464
Energy proportionality, WSC servers, 462
Erasure encoding, WSCs, 439
Error-Correcting Code (ECC)
fault detection pitfalls, 58
Fermi GPU architecture, 307
memory dependability, 104
and WSCs, 473–474
Ethernet switches
architecture considerations, 16
Dell servers, 53
historical performance milestones, 20
WSCs, 441–444
EX See Execution address cycle (EX)
Example calculations
average memory access time, B-16 to B-17
block size and average memory access time, B-26 to B-28
branch predictors, 164
branch schemes, C-25 to C-26
branch-target buffer branch penalty, 205–206
cache hits, B-5
cache organization impact, B-19 to B-20
CPI and FP, 50–51
dies, 29
die yield, 31
disk subsystem failure rates, 48
floating-point square root, 47–48
GCD test, 319, H-7
geometric means, 43–44
hardware-based speculation, 200–201
inclusion, 397
information tables, 176–177
L1 cache speed, 80
loop-carried dependences, 316, H-4 to H-5
loop-level parallelism, 317
loop-level parallelism dependences, 320
loop unrolling, 158–160
MapReduce cost on EC2, 458–460
memory banks, 276
microprocessor dynamic energy/power, 23
MIPS/VMIPS for DAXPY loop, 267–268
miss penalty, B-33 to B-34
miss rates and cache sizes, B-29 to B-30
miss support, 85
MTTF, 34–35
multimedia instruction compiler support, A-31 to A-32
parallel processing, 349–350, I-33 to I-34
pipeline execution rate, C-10 to C-11
pipeline structural hazards, C-14 to C-15
power-performance benchmarks, 439–440
processor performance comparison, 218–219
redundant power supply reliability, 35
ROB commit, 187
ROB instructions, 189
scoreboarding, C-77
sequential consistency, 393
server costs, 454–455
server power, 463
SIMD multimedia instructions, 284–285
speedup, 47
status tables, 178
strides, 279
true sharing misses and false sharing, 366–367
vector sequence chimes, 270
VLIW processors, 195
way selection, 82
write buffer and read misses, B-35 to B-36
write vs. no-write allocate, B-12
WSC memory latency, 445
WSC running service availability, 434–435
WSC server data transfer, 446
Exceptions
ALU instructions, C-4
architecture-specific examples, C-44
categories, C-46
control dependence, 154–155
hardware-based speculation, 190
long latency pipelines, C-55
out-of-order completion, 169–170
return address buffer, 207
ROB instructions, 190
speculative execution, 222
stopping/restarting, C-46 to C-47
types and requirements, C-43 to C-46
Execution address cycle (EX)
basic MIPS pipeline, C-36
data hazards requiring stalls, C-21
data hazard stall minimization, C-17
exception stopping/restarting, C-46 to C-47
hazards and forwarding, C-56 to C-57
MIPS FP operations, basic considerations, C-51 to C-53
MIPS pipeline, C-52
MIPS pipeline control, C-36 to C-39
out-of-order execution, C-71
RISC classic pipeline, C-10
simple MIPS implementation, C-31 to C-32
simple RISC implementation, C-6
Execution time
application/OS misses, B-59
calculation, 36
energy efficiency, 211
integrated circuits, 22
loop unrolling, 160
multilevel caches, B-32 to B-34
multiprocessor performance, 405–406
multiprogrammed parallel “make” workload, 375
multithreading, 232
performance equations, B-22
PMDs, 6
principle of locality, 45
processor comparisons, 243
reduction, B-19
second-level cache size, B-34
and stall time, B-21
vector mask registers, 276
vector operations, 268–271
Expand-down field, B-53
Explicit operands, ISA classifications, A-3 to A-4
Explicit unit stride, GPUs vs. vector architectures, 310
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