Input Scheduling 257
Enabling QoS on the Switch
QoS first needs to be enabled globally on the switch, before this discussion turns to an
explanation of the different QoS features. Example 8-1 shows how to initialize QoS on the
Catalyst 6500 and shows the commands to verify the configuration.
After QoS has been enabled on the switch, the features can be configured. This chapter now
focuses on the individual QoS mechanisms available on the Catalyst 6500. The first topic
is input scheduling.
Input Scheduling
As shown in Table 8-1, the Catalyst 6500, through the use of individual port ASICs, can
support input queue scheduling. This feature is beneficial if contention for the bus or
switching fabric exists. At the time of writing, for instance, fabric-enabled cards have an 8-
Gbps full-duplex connection to the switching fabric. Voice and real-time application perfor-
mance may be severely impacted if the receiving module is a WS-X6516, with all 16 ports
receiving traffic at close to line rate. To ensure that voice traffic and other real-time appli-
cations maintain required service levels, you can use input scheduling to assign traffic to
the appropriate queues and thresholds. The recommendation is to assign voice traffic to the
priority queue to minimize the end-to-end delay and jitter. To take advantage of this feature,
however, the inbound port must be configured to trust the arriving CoS. To view the sched-
uling capabilities of a particular port, use one of the following commands:
Example 8-1 Enabling QoS on the Switch
(Hybrid)
hybrid(enable)> set qos enable
Command Verification:
hybrid(enable)> show qos status
QoS is enabled on this switch.
(Native)
native(config)# mls qos
Command Verification:
native# show mls qos
QoS is enabled globally
!
(text omitted)
Example 8-2 Viewing Input Scheduling Capabilities
(Hybrid)
Show port capabilities [
mod
[/
port
]]
hybrid (enable) show port capabilities 4/1
Model WS-X6408A-GBIC
(text omitted)
QOS scheduling rx-(1p1q4t),tx-(1p2q2t)
(text omitted)
or
258 Chapter 8: QoS Support on the Catalyst 6500
NOTE The following section on classification covers the concept of trust and how it operates on
the Catalyst 6500.
All other settings result in the arriving frames being placed in a default queue and
forwarded directly to the switching engine based on FIFO. Figure 8-3 represents the
decision path for an arriving frame.
Figure 8-3 Decision Path for an Ingress Frame
(Native)
show interface {
type
num
} capabilities
native# show interface gigabitEthernet 2/1 capabilities
Model: WS-X6516-GBIC
(text omitted)
QOS scheduling: rx-(1p1q4t), tx-(1p2q2t)
(text omitted)
or
show queueing interface {
type
num
} [| include Receive]
native# show queueing interface fastEthernet 6/1 | include Receive
Receive queues [type = 1q4t]:
Example 8-2 Viewing Input Scheduling Capabilities (Continued)
Port
Untrusted
Trust-COS
** Priority queue only available on ports
with 1p1qXt architecture.
Arriving
Frame
Ingress Port
(Port ASIC)
802.1q or
ISL frame
Trust
IPPREC
Use Default
Port CoS
Trust-
DSCP
** Priority queue (CoS 5)
Normal queue
Tail-drop Thresholds
Use Default
Port CoS
Switching
Engine
Ye s
Ye s
Ye s
Ye s
No No
No
No
Ye s
Input Scheduling 259
Because input scheduling is only applicable when the port is set to trust an ingress frame’s
CoS value, assume the appropriate configuration has been made. If the arriving frame has
an 802.1q or Inter-Switch Link (ISL) header, the port logic maintains the CoS value
specified in the user priority field or the user field for the respective frames. For all other
frames, the port ASIC uses the default CoS setting specified by the administrator for the
given port.
NOTE 802.1q headers have a user priority field, and ISL headers contain a user field; these fields
enable the network administrator to specify that a certain stream of traffic should be
handled more expeditiously. However, frames not tagged with a trunk header lack any
additional fields that accommodate a CoS setting. As a result, all untagged frames utilize
the default CoS value specified on the ingress port. By acquiring the default port CoS value,
the derived value determines how the frame is processed through the switch. This setting
may also impact how the frame is handled on an end-to-end basis across the network.
After the CoS value of an inbound frame has been determined, the frame is placed into the
appropriate queue. For most 10/100 ports, there is one queue with four configurable tail-
drop thresholds, designated as 1q4t. For additional information on queue nomenclature,
refer to the section “Catalyst Feature Overview” in Chapter 3, “Overview of QoS Support
on Catalyst Platforms and Exploring QoS on the Catalyst 2900XL, 3500XL, and Catalyst
4000 CatOS Family of Switches.” Each CoS is mapped to one of these four thresholds.
Table 8-4 shows the exact CoS-to-threshold assignment for 1q4t port types. The exception
to this is the fabric-enabled 10/100 modules, whose ports offer an additional strict-priority
queue for frames marked with CoS 5. These port types are designated as 1p1q0t. This
module is covered later in the section “Input Scheduling and Congestion Avoidance for
1p1q0t and 1p1q8t.”
Similar to the non-fabric-enabled 10/100 ports, earlier Gigabit Ethernet ports could only
provide a single queue with congestion avoidance handled by the four configurable tail-
drop thresholds. (Refer back to Table 8-2 to view the queue architecture for the various
modules.) However, recent Gigabit linecards offer the additional use of a strict-priority
queue, noted as 1p1q4t. The priority queue is responsible for transmitting delay-sensitive
and critical network traffic, namely voice. Because the priority queue can starve remaining
traffic, it is recommended that only low-bandwidth traffic be placed in the strict-priority
queue. By default, frames marked with CoS 5 are mapped to the strict-priority queue. This
ensures the expeditious handling of voice traffic, because Cisco IP Phones mark voice
frames with CoS 5. To minimize the delay and jitter, which impact voice quality, the strict-
priority queue is provided immediate access to the switch backplane. If traffic exists in the
strict-priority queue, it is serviced prior to any other queues. Contrary to the normal queue,
however, the priority queue does not possess a configurable threshold. When the strict-
priority queue reaches 100-percent capacity, frames are discarded due to buffer exhaustion.
260 Chapter 8: QoS Support on the Catalyst 6500
Figure 8-4 shows input scheduling on 10/100 ports from an architectural perspective.
Figure 8-4 Ingress QoS on the Coil ASIC
NOTE Figure 8-4 does not reflect the architecture of the fabric- enabled 10/100 modules. They use
different ASICs and utilize a centralized buffer accessible to each port on the linecard.
Although the architecture is centralized, the net result is a finite buffer being statically
allocated to each port.
As depicted in Figure 8-4, input queue scheduling and congestion management on the 10/
100 modules are accomplished by using the Coil ASIC.
The Pinnacle serves as the connection to the switching bus, and branches out to four Coil
ASICs. Each Coil ASIC is responsible for servicing twelve 10/100 ports on a single
linecard. The Coil is also responsible for allocating a finite amount of buffer space to each
port. As shown in the figure, each individual port receives 128 KB of buffer space. The
figure depicts the architecture for both the WS-X6348 and WS-X6148. Each block of
memory is further subdivided, leaving 112 KB for the transmit buffer and 16 KB for the
receive buffer. Within the 16 KB of space allocated for the receive queue, four tail-drop
thresholds are specified. The different CoS values are mapped to these threshold levels.
(Default Threshold Values for
Normal Queue)
100% Capacity
80% Capacity
60% Capacity
50% Capacity
CoS 6, 7
CoS 4, 5
CoS 2, 3
CoS 0, 1
16 kbps-Rx Buffer Capacity
128 kbps Total Buffer Space
Allocated per 10/100 Port
Incoming
Frames
Coil
Input Scheduling (1q4t)
1 Queue
4 Tail-Drop Thresholds
Coil
10/100
Ports
112 kbps (Tx)
16 kbps (Rx)
Pinnacle
Input Scheduling 261
Figure 8-5 Ingress QoS on the Pinnacle ASIC
Figure 8-5 shows the ASIC responsible for Gigabit Ethernet ports. In this case, the Pinnacle
ASIC controls four Gigabit ports. Each port receives 512 KB of buffer space, which is
subdivided into 439 KB for the transmit side and 73 KB for the receive side. For earlier
Gigabit linecards that do not have a strict-priority queue, the buffer architecture differs
slightly and the default threshold settings and CoS mappings match the default settings for
the 10/100 ports, shown in Table 8-4. For ports with a strict-priority queue, the default
differs slightly. Instead of being mapped to the third tail-drop threshold setting of 80
percent, all frames arriving with CoS 5 are mapped to the priority queue by default. It is up
to the network administrator to ensure that CoS 5 is, in fact, the critical traffic. The strict-
priority queue then ensures that all arriving critical traffic is forwarded prior to traffic in the
normal queue. When the priority queue is depleted, the normal queue is serviced. Again,
the priority queue is only intended to accommodate low-bandwidth, low-latency traffic,
such as voice. Continuous traffic present in the priority queue can potentially starve out
lower queues. The priority queue does not have a configurable threshold. Therefore as soon
as the queue is full, it tail drops any excess frames. Figure 8-5 depicts the priority queue,
the default thresholds, and the CoS mappings. Now that input queue scheduling has been
introduced, the focus turns to assigning receive queue drop thresholds and how to map CoS
values to the thresholds and queues.
Pinnacle
100% Capacity
80% Capacity
60% Capacity
50% Capacity
73 kbps--Rx Buffer Capacity
512 kbps Total Buffer Space
Allocated per Port
Incoming
Frames
Input Scheduling (1p1q4t)
1 Strict Priority Queue
and
1 Queue with
4 Tail-Drop Thresholds
439 kbps (Tx)
73 kbps (Rx)
100% Capacity
CoS 7
CoS 4, 6
CoS 2, 3
CoS 0, 1
CoS 5
Normal Queue
Switching Bus
Strict Priority Queue
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