200 Chapter 7: QoS Features Available on the Catalyst 4000 IOS Family of Switches and the Catalyst
*GBIC = Gigabit interface converter
This chapter provides information about architecture, supported QoS features, configu-
ration examples, and case studies for both the Catalyst 4000 IOS Family of switches and
the Catalyst G-L3 Family of switches.
QoS Support on the Catalyst 4000 IOS Family of Switches
QoS feature support on the Catalyst 4000 IOS Family of switches surpasses those features
supported in the Catalyst 4000 CatOS Family of switches. Tables 3-1 through 3-5 in
Chapter 3 summarize the general QoS feature support on the Catalyst 4000 IOS Family of
switches.
Specifically, the first section of this chapter covers the following topics and QoS features
supported on the Catalyst 4000 IOS Family of switches:
• Architecture Overview
• Software Requirements
• Global Configuration
• Input Scheduling
• Internal DSCP
• Classification and Marking
Catalyst 4000 Model Reference Family Description
Catalyst 4503 + WS-X4013
Supervisor III Engine
Catalyst 4000 CatOS 3-slot modular chassis + 2 1000BASE-X GBIC
ports on Layer 2 supervisor
Catalyst 4503 + WS-X4014
Supervisor III Engine
Catalyst 4000 IOS 3-slot modular chassis + 2 1000BASE-X GBIC
ports on Layer 2/3 supervisor
Catalyst 4503 + WS-X4515
Supervisor IV Engine
Catalyst 4000 IOS 3-slot modular chassis + 2 1000BASE-X GBIC
ports on Layer 2/3 supervisor
Catalyst 4506 + WS-X4014
Supervisor III Engine
Catalyst 4000 IOS 6-slot modular chassis + 2 1000BASE-X GBIC
ports on Layer 2/3 supervisor
Catalyst 4506 + WS-X4515
Supervisor IV Engine
Catalyst 4000 IOS 6-slot modular chassis + 2 1000BASE-X GBIC
ports on Layer 2/3 supervisor
Catalyst 4507R + WS-X4515
Supervisor IV Engine
Catalyst 4000 IOS 7-slot modular chassis + 2 1000BASE-X GBIC
ports on Layer 2/3 supervisor
Catalyst 4840G Catalyst Layer 3
server load-balancing
switch
40-port 10/100BASE-TX + 1000BASE-X
GBIC Layer 3 server load-balancing switch
Catalyst 4908G-L3 Catalyst G-L3 Switch 12-port 1000BASE-X GBIC Layer 3 switch
Catalyst 4912G Catalyst 4000 CatOS 12-port 1000BASE-X GBIC Layer 3 switch
Table 7-1 Catalyst 4000 CatOS Versus Cisco IOS Software Platform Matrix (Continued)
QoS Support on the Catalyst 4000 IOS Family of Switches 201
• ACL-based Classification
• Policing
• Congestion Management
• Auto-QoS
• Case Study
Catalyst 4000 IOS Family of Switches QoS Architectural Overview
The Catalyst 4000 IOS Family of switches bases packet-processing performance solely on
the use of ternary content addressable memory (TCAM). Packet processing includes appli-
cation of QoS rules utilizing TCAM. These switches also use TCAM for Layer 2 lookups,
Layer 3 lookups, Layer 3 rewrite information, and access-control list (ACL) processing.
The use of TCAM in this manner allows the Catalyst 4000 IOS Family of switches to
achieve line-rate performance at 64 Gbps.
The use of TCAM and the unique architecture of the Catalyst 4000 IOS Family of switches
allows for application of QoS rules while maintaining line-rate performance for
nonblocking ports. Table 3-9 in Chapter 3 discusses which front-panel ports are
nonblocking per line card. The switches’ architecture processes every packet against all
QoS rules regardless of whether any configured QoS rules exist. A default QoS rule of null
exists for application to every packet processed. As a result, when the switch subjects
packets to QoS rules and processing, no change occurs in system performance. This
behavior holds for ACL processing as well.
The industry term hardware switching refers to the discussed use of the TCAM component
for packet processing. If the switch is unable to hardware switch a packet, the CPU must
process the packet instead. The term software switched describes the packet processing
orchestrated by an onboard CPU. An onboard CPU employs Cisco IOS Software for
instruction on how to process and forward packets. Packets handled by the CPU experience
lower packet-processing performance compared to hardware-switched packets because of
the limited speed of the onboard CPU. In relation to QoS on the Catalyst 4000 IOS Family
of switches, packet processing needs to occur in hardware, because of the limited software-
switching performance of the CPU. A trade-off of utilizing TCAM for the line-rate perfor-
mance is that hardware switching does not support all the Cisco IOS QoS features available
in the latest Cisco IOS Software versions. Hardware switching only supports a subset of
Cisco IOS QoS features for packet processing. The content of this chapter focuses only on
QoS features that support hardware switching. In addition, TCAM is a limited resource
varying per platform. The resource limitations affect the size and number of ACLs entries
and policy maps allowed. ACLs that do not fit into TCAM are not executed on the Catalyst
4000 IOS Family of switches. Chapter 6, “QoS Features Available on the Catalyst 2950 and
3550 Family of Switches,” presents the first platform to utilize TCAM for QoS features.
This chapter includes more detailed information on the TCAM architecture. Figure 7-1
202 Chapter 7: QoS Features Available on the Catalyst 4000 IOS Family of Switches and the Catalyst
depicts the logical model of QoS packet flow in a Catalyst 4000 IOS switch. Later sections
refer to this figure.
Figure 7-1 Logical QoS Architecture for the Catalyst 4000 IOS Family of Switches
Because of the QoS features supported on the Catalyst 4000 IOS Family of switches, these
switches fit well into an end-to-end QoS design as core, distribution, or access layer
switches. Networks that require more than 64 Gbps or 48 Mpps in the core need to use the
Catalyst 6500 platform instead. Figure 7-2 illustrates a sample network design using a
Catalyst 4000 IOS switch in the distribution layer.
Software Requirements
All versions of the Catalyst 4000 IOS Software support QoS features. Several QoS
attributes differ between the existing software versions. The initial releases of the Cisco
IOS Catalyst 4000 software are Cisco IOS versions 12.1(8a)EW and 12.1(8a)EW1. A
notable software change applicable to QoS occurs in Cisco IOS Software version
12.1(11b)EW1. In the original software versions, the switch counts packet drops that result
from transmit queue overflow as output errors. In 12.1(11b)EW1 and later software
versions, the switch counts output queue buffer drops as output drops rather than output
errors. Example 7-1 compares how the switch counts output queue drops in 12.1(8a)EW
and 12.1(8a)EW1 versus 12.1(11b)EW1 and later software versions.
QoS Packet Processing
Determine
Transmit
Queue
MarkPolicing
Internal DSCP
determines output
queue.
Only Packet Header is
processed. Packet is
stored in Global Buffer
during Header
Processing.
Egress
Packet
Packet with
Internal DCSP
Scheduling and the Shaping
andSharing configuration
determinesqueue service.
1p3q1t Transmit
Queue
Queue 4
Queue 3
Queue 2
Queue 1
Classification
Internal DSCP is
derived from Ingress
Packet DSCP, CoS,
port configuration or
ACL configuration and
DSCP mapping tables.
Ingress
Packet
QoS Support on the Catalyst 4000 IOS Family of Switches 203
Figure 7-2 Sample Network Topology Using Catalyst 4000 IOS Switches
L3 L3
L2
L3
L2
L3
L3
L2
Catalyst 6500
with MSFC II
Catalyst 4507R
with Supervisor
IV
Catalyst 4506
Catalyst 6500
with MSFC II
Catalyst 4507R
with Supervisor
IV
Catalyst 4506
Workstations Workstations
Cisco IP
Phones
Cisco IP
Phones
204 Chapter 7: QoS Features Available on the Catalyst 4000 IOS Family of Switches and the Catalyst
Example 7-1 Transmit Buffer Overflow Counter Differences Between Software Versions 12.1(8a)EW and
12.1(8a)EW1 and Later Versions
! 12.1(8a)EW:
Switch#show interface FastEthernet 6/1
FastEthernet6/1 is up, line protocol is up
Hardware is Fast Ethernet Port, address is 0007.508b.84e0 (bia 0007.508b.84e0)
MTU 1500 bytes, BW 100000 Kbit, DLY 100 usec,
reliability 255/255, txload 1/255, rxload 1/255
Encapsulation ARPA, loopback not set
Keepalive set (10 sec)
Full-duplex, 100Mb/s
input flow-control is off, output flow-control is off
ARP type: ARPA, ARP Timeout 04:00:00
Last input never, output never, output hang never
Last clearing of “show interface” counters never
Input queue: 0/2000/0/0 (size/max/drops/flushes); Total output drops: 0
Queueing strategy: fifo
Output queue: 0/40 (size/max)
5 minute input rate 0 bits/sec, 0 packets/sec
5 minute output rate 0 bits/sec, 0 packets/sec
373781138 packets input, 2447156352 bytes, 0 no buffer
Received 11 broadcasts, 0 runts, 0 giants, 0 throttles
4 input errors, 1 CRC, 0 frame, 0 overrun, 0 ignored
0 input packets with dribble condition detected
926574 packets output, 76097292 bytes, 0 underruns
3120970731 output errors, 0 collisions, 0 interface resets
0 babbles, 0 late collision, 0 deferred
1 lost carrier, 0 no carrier
0 output buffer failures, 0 output buffers swapped out
! 12.1(11b)EW1 and Later:
Switch#show interface FastEthernet 6/1
FastEthernet6/1 is up, line protocol is up
Hardware is Fast Ethernet Port, address is 0007.508b.84e0 (bia 0007.508b.84e0)
MTU 1500 bytes, BW 100000 Kbit, DLY 100 usec,
reliability 255/255, txload 1/255, rxload 1/255
Encapsulation ARPA, loopback not set
Keepalive set (10 sec)
Full-duplex, 100Mb/s
input flow-control is off, output flow-control is off
ARP type: ARPA, ARP Timeout 04:00:00
Last input never, output never, output hang never
Last clearing of “show interface” counters never
Input queue: 0/2000/0/0 (size/max/drops/flushes); Total output drops: 250355824
Queueing strategy: fifo
Output queue: 0/40 (size/max)
5 minute input rate 0 bits/sec, 0 packets/sec
5 minute output rate 0 bits/sec, 0 packets/sec
373781138 packets input, 2447156352 bytes, 0 no buffer
Received 11 broadcasts, 0 runts, 0 giants, 0 throttles
0 input errors, 0 CRC, 0 frame, 0 overrun, 0 ignored
0 input packets with dribble condition detected
926574 packets output, 76097292 bytes, 0 underruns
0 output errors, 0 collisions, 0 interface resets
0 babbles, 0 late collision, 0 deferred
1 lost carrier, 0 no carrier
0 output buffer failures, 0 output buffers swapped out
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