2.1.1 Supplied Voltage

Firstly, the supplied battery voltage must meet the operation requirements of the electronic circuitry used in the wearable device. Importantly, the supplied voltage is not the same as the battery nominal voltage as there will be an internal voltage drop in the battery due to the internal resistance, and this drop will vary depending on the current draw. Most off-the-shelf low-power microcontrollers and transceivers today require somewhere between 1.8 V and 3.6 V, and batteries that supply a voltage outside this range must be used with a DC-to-DC voltage converter or stacked in series to increase the delivered voltage. However, these techniques reduce the battery lifetime due to either the extra power consumption from the additional circuitry or due to the increased internal impedance.

2.1.2 Maximum Continuous Current

Secondly, the maximum continuous current (also referred to as the maximum average current supply), I_avg(max), limits the average current draw from the battery. In theory, a 200 mAh battery can provide 1 mA for 200 hours, or 200 mA for 1 hour. In practice, each battery actually has a maximum supported current draw and if more current than this is drawn the effective capacity will not be the full 200 mAh reported value. The average current required by the system must be smaller than the corresponding I_avg(max) for the specific battery. Otherwise, more than one battery will have to be used in parallel, possibly together with diodes to prevent any non-rechargeable batteries from inadvertently charging. Again, the battery must be able to provide this current without a significant drop in its voltage supply because of the internal impedance.

2.1.3 Maximum Pulse Current Capability

Thirdly, for short periods a battery can provide more than I_avg(max), up to a maximum pulse value I_pulse(max). I_pulse(max) must be large enough to guarantee that variations in the supply voltage, which will drop if the current consumption increases, will not exceed the operating range of any circuit in the wearable sensor. The value of I_pulse(max) is a function of how long the pulse must be provided (the hold time); Figure 2 shows typical maximum values of pulse current with various pulse widths for the batteries listed in Table 2. There is a clear decrease in the maximum pulse current that can be provided as the duration of the required pulse increases. This is of particular importance when selecting the radio transceiver block and protocol as this generally determines both the peak current draw and how long it is required for.

2.1.4 Effective Capacity and Lifetime

Combining the above effects allows the effective battery capacity (C_eff) to be found. This is a critical parameter for long-term monitoring applications and it will generally be smaller than the nominal battery capacity, unless the system average current consumption (I_sys) matches the manufacturer’s recommended value (also referred to as the nominal current or the standard discharge current). The value of C_eff is hence a function of I_sys and it will be lower than its nominal value when I_sys is larger than the nominal current.

Based on this, in order for a certain battery to be a viable option for a specific system it must meet the system requirements not only in terms of size and supply voltage, but also in terms of the average and maximum dynamic currents that the system needs to operate. Once the necessary conditions are met the lifetime of the battery, LT(I_sys), can be determined as

$LT(I_{sys})=\frac{C_{eff}(I_{sys})}{I_{sys}}$ (1)

(1)

Figure 2 also shows a plot of the measured battery lifetime LT(I_sys) versus the average current consumption I_sys for our battery examples. From this it is clear how, although the CYC battery used requires more volume, it also provides much better performance in all other aspects. Comparatively the zinc-air BC batteries have similar performance only if the effective average current drain is higher than 1 mA. This is due to their high self-discharge characteristic when exposed to air, and for applications with ultra-low effective power consumption (i.e., I_sys<1mA) zinc-air batteries should be used with air management so that only a limited (but necessary) amount of air goes into the batteries. Alternatively, in cases when the continuous current is not a limiting factor, the CC battery may be preferable since it has a superior combined performance in terms of self-discharge rate and pulse current capability.

2.2.1 Data Acquisition

As shown in Figure 1, a general wearable sensor may contain signal conditioning circuitry (typically an amplifier and an analog-to-digital converter (ADC)), and some optional signal-processing blocks to reduce the amount of data for wireless transmission. In the signal-conditioning block there is at least one anti-aliasing filter that restricts the bandwidth of the input signal before passing it to the ADC. For wearable applications seeking to minimize size, the anti-aliasing filter may be realized as a first-order RC low-pass filter. This is a physically very small circuit, but its use will come at the cost of requiring a higher ADC sampling frequency to ensure that the analog input signal is correctly represented in the digital domain. In turn, this implies that the amount of data passed through the system is increased, leading to an increase in power consumption due to the data multiplication. If desired, and as considered in section 2.4, downsampling of the data can be performed in the digital domain to obtain data compression. It is to avoid similar data multiplication that successive approximation register (SAR) ADCs tend to be preferred in wearable applications, rather than Σ-Δ ones, which are intrinsically based upon oversampling. In addition, SAR converters can operate with a lower peak dynamic current.

2.2.2 Wireless Transmission Controller

After acquisition, the physiological data is temporarily stored in a buffer and packetized to be sent to the wireless transmitter. During this process the controller decides on the structure of the transmission protocol, including the total size of a packet frame (L_frame) and the size of the packet header. Both limit the amount of physiological data (L_data) that can be carried in each over-the-air data packet and mean that the full over-the-air rate available to the wireless transmitter cannot be used to transmit useful physiological data. The utilization of the protocol (η_protocol) for the data can be expressed as

${\eta }_{protocol}=\frac{L_{data}}{L_{frame}+T_{latency}·R_{air}}$ (2)

(2)

where R_air is the over-the-air data rate and T_latency is the total latency introduced by the data acquisition, packet packaging, and transceiver interfacing.

Note that although longer packet sizes increase the data throughput and relieve the communication overhead, they also increase the transmission time, exponentially increasing the risk of interruption from undesired radio frequency (RF) interferences. This error rate will be explored in more detail below. Further, to avoid extra transceiver control complexity and overhead, the length of each data packet should be designed to match the size of the buffer present in the transceiver being used. This prevents the buffer from overflowing, and here we consider using this optimal packet size only.

2.3.1 Quality of the Packet Transmission

Unstable transmission quality can cause unnecessary retransmission overhead or even packet loss. The successful transmission rate (η_tx) for one packet can be calculated as

${\eta }_{tx}=(1-PER)·{\phi }_{QOL}={\left(1-BER\right)}^N·{\phi }_{QOL}$ (3)

(3)

where PER is the packet error rate, BER is the bit error rate, N is the bit length of a packet, and φ_QOL, the quality of link (QOL) factor, which estimates the probability of the RF channel being clear throughout the transmission process. It decays with longer transmission times.

From (3) it can be seen how a long packet size is not advisable. Also, the QOL of radio transceivers is affected by the transmission range and the transmission power. Long transmission ranges decrease the strength of the RF signal and hence lower the QOL. Generally, the transmission RF power can be tuned to trade-off QOL and power consumption.

In addition to this, to compensate for the BER and improve the link quality, chip manufacturers have introduced different features into transceivers so as to strengthen their error tolerance capability. Forward error correction (FEC) and automatic acknowledgement (auto-ack) are two examples that will be used in the test cases considered below. However, the use of these can come with extra cost, the largest one being FEC, which sacrifices half of the available bandwidth to create redundancy.

2.3.2 Hardware Overhead

In order to allow the wireless transmitter and receiver to recognize each other, and to synchronize, the transceiver appends a preamble signal (with size L_preample) and its own transmission identification data (with size L_txid) to the front of every packet automatically. Once the packet reaches the receiver these extra bits are examined and removed by the packet-handling hardware. Again, this results in not all of the over-the-air data rate being available for useful data transmission. The hardware efficiency η_hw is a key factor in this and can be calculated as

${\eta }_{hw}=\frac{L_{data}}{L_{frame}+L_{preamble}+L_{txid}+(T_{cal}+T_{switch})·R_{air}}$ (4)

(4)

where the last term in the denominator accounts for a certain overhead generated by the time required to calibrate the PLL module of the RF synthesizer before transmission: T_cal is necessary in battery powered systems in order to avoid the frequency drift caused by variations in the supply voltage, and T_switch is the time taken by the transitions between different low-power states.

2.3.3 Air Data Rate vs. Effective Data Rate

Given all of these factors the effective data transmission rate can be calculated, and this must be sufficient for the wanted application. Moreover, for the same amount of data, the faster the data rate the lower the effective power consumption as the transmitter can be turned off for more of the time. However, the overheads discussed in previous sections decrease the effective data rate and must not be ignored in power management. The effective bandwidth (R_eff) of the transmission process can be estimated as

$R_{eff}={\eta }_{protocol}·{\eta }_{tx}·{\eta }_{hw}·R_{air}$ (5)

(5)

2.4.1 Node Design

Our system has a single channel that starts at the high-pass filter, normally used to eliminate out-of-band low frequency components such as electrode drift. This is followed by an amplifier that conditions the normally very weak signals for the subsequent blocks, a low-pass anti-aliasing filter (first-order RC filter made using discrete surface mount components) and a 10-bit SAR ADC, which is part of the MSP430 chip (MSP430F2274).

Here, we investigate two variants on this basic system: one using a Texas Instruments CC2500 transceiver as the transmitter stage and one using a Nordic RF24L01+ transceiver. Both of these operate in the 2.4 GHz band and are connected to the MSP430 by the serial peripheral interface (SPI) with maximum 10 MHz and 8 MHz clocks, respectively. The CC2500 has an option to enable FEC, while the RF24L01+ provides hardware support for auto-ack.

We use Texas Instrument’s SimpliciTI protocol stack with both transceivers, although it was originally designed for the CC2500 only. SimpliciTI is a low-power, lightweight wireless network protocol dedicated for battery-operated devices that require long battery life. From [19] the header of a non-encrypted SimpliciTI packet frame contains 96 bits. Because the RF24L01+ has half the buffer size of the CC2500 (256 bits), one field in the header is used to store the byte length of the user data, and this has been modified for the RF24L01+. In the user data field we add a time stamp for the recording, 20 bits in length, to each packet as an additional header. Given the memory constraints of the used MSP430 the rest of the space in a packet allows the CC2500 to transmit 34 samples (340 bits), whereas the RF24L01+ can transmit 18 samples (180 bits). In total, the packet size is 456 bits for the CC2500 and 294 bits for the RF24L01+.

To maximize the data throughput, minimize latency, and allow the transmitters to be duty cycled to reduce the average power, the air data rates of the transceivers are set to their maximum values: 500 kbits/s for the CC2500 and 2 Mbits/s for the RF24L01+. As recommended in [20], the preamble signal of the CC2500 is set to 96 bits. The RF24L01+ has 8 bits fixed preamble length [21] and both the CC2500 and RF24L01+ have extra identification data appended by hardware with lengths of 16 and 19 bits. Overall, assuming 100% of QOL, the effective data rate can be calculated from Eqs. (2) to (5) as 106 kbits/s and 338 kbits/s, respectively.

2.4.2 Optional Data Compression

To cover the physiological range we assume a bandwidth of up to 1 kHz. However, due to the use of a first-order passive RC anti-aliasing filter we sample at 4 kHz. Given this oversampling we again investigate two variants on the system: one where we transmit all of the collected data and one where we first downsample the data by a factor of 2. This lets us explore the impact of even modest data compression on our node lifetime.

The downsampling is implemented using a tenth-order Kaiser window digital low-pass filter (FIR) running on the MSP430. Our MSP430 model contains no hardware multiplier to reduce the computational burden of this processing.

2.4.3 Power Performance Results

For the core system, excluding the wireless transmitter, Table 3 shows the current consumption of each block present. The typical current profiles of the two transceivers are illustrated in Figure 4, where label A marks the section corresponding to the transmission overhead, B marks the actual wireless transmission times, and C indicates the optional auto-ack reception.

Combined with the wireless transmitter, the two systems are compared in Table 4, which shows the current consumption of the systems when tested over 24 hours using the different batteries given in Table 2. It can be seen how some configurations only pass the 24-hour test with certain batteries. Not all miniature batteries are suitable for long-term monitoring! This has direct implications on the kind (and number) of batteries that may be required in a specific design, and consequently on the device size. For 24-hour monitoring applications with 22 kbits/s data rate, the smallest wireless configuration can be achieved by using one lithium manganese dioxide CR2430 3V battery.

Turning on the data compression leads to substantial reductions in the effective current drawn by the system. Reductions by 20 to 30% are achieved, and in the CC2500 case without FEC the reduction is 53%. In all of the cases this reduction allows more of the battery technologies from Table 2 to be used, giving greater freedom in the system design and in the optimization of the device size. In the best case the effective current consumption of the entire system goes down to 3.5 mA, equivalent to a net power consumption of 480 nJ/bit. It is important to highlight, however, that only reductions in the effective current are achieved by the data compression. There are no substantial differences in the peak currents, and in some cases these may now become the limiting factors in the system design.

4.1.1 Procedure

Online signal processing for wearable sensors can take two forms:

As we will see in section 4.3 most current wearable algorithms focus on this second option; the core stages required are shown in Figure 8. The raw input signal (y) is first passed to a feature extraction stage which emphasizes the points in the signal of interest: signal processing is applied such that interesting sections of the input signal are amplified relative to the non-interesting sections. For example, in ECG heart beat detection the aim would be to highlight the time at which the QRS complex occurs.

These features are then normalized to correct for the fact that physiological signals vary widely between different people and in the same person over time. This may be due to different underlying disorders present, changes in the signal due to age (as happens with the EEG [30]), or due to changes in the interface/electrodes(s) contact over time. Normalization aims to correct for these changes (to some extent) to allow reliable and robust operation of the algorithm, even if a subject-dependent classifier is used.

The final step is generating an output and using the input physiological signal to actually make a decision. Generally this takes the form of a classification engine that might provide a binary answer: Is a heartbeat present in this section of data? Is the subject awake or asleep? The output could also be multi-class: in this section of data is the subject awake, in light sleep (stages 1 and 2), deep sleep (stages 3 and 4), or in REM sleep? This output can then be used to control the operation of the wearable sensor node to maximize its operational lifetime. For example, in sleep monitoring applications the node might go into low-power mode whenever it detects that the human subject is awake. Alternatively, the sampling frequency of an ECG may be varied between a high rate during the heartbeat (QRS complex) and a low rate in between beats [31].

4.1.2 Feature Extraction

There are many possible features that could be chosen for use as the signal processing basis, and this forms one of the main design decisions impacting algorithm performance. Many of the algorithms considered in section 4.3 are based upon frequency domain information. For example, sleep onset in the EEG is known to be characterized by a reduction in the presence of 8 to 13 Hz (alpha) activity with this being replaced by 4 to 8 Hz (theta) activity [32]. The feature extraction in this case may therefore be a Fourier transform to follow the changes in these frequency bands. Alternatively, time-frequency transforms such as the continuous wavelet transform or discrete wavelet transform could be used [33,34].

For use in wearable sensor nodes the number of different features used is ideally minimized to reduce the power consumption and the number of circuit stages required. Hence it is important to make an optimal feature choice. A recent study that investigated 63 different features for highlighting seizure activity in the EEG [35] found that discrete wavelet transform-based features obtained the best performance (with an area under the performance curve of 83%), while fractal dimension and bounded variation features offered little over chance performance (53%). However, this doesn’t rule out the possibility that these other features if used with a different classification approach would get better performance, or that combinations of more than one feature could again lead to better performances.

Further, all features are also not equal in terms of the power required to calculate them, and this must weigh the choices made. Indeed when corrected for run time, [35] prefers a time-domain feature known as the line-length as the single best feature for highlighting seizure activity in scalp EEG.

4.1.3 Classification Engines

The simplest decision-making scheme is a threshold where the normalized input feature is simply compared to a fixed detection threshold:

$\begin{array}{l}\mathrm{If\; feature}>\mathrm{threshold}\\ \mathrm{Make\; detection}\\ \mathrm{Else}\\ \mathrm{No\; detection}.\end{array}$ (16)

(16)

This threshold can easily be varied to produce performance trade-off curves as shown in Figure 6 and has a very low computational complexity. Such an approach has been used in systems such as [35,36] to obtain low complexity performance.

More recently, machine-learning approaches have been used to automatically determine the best detection parameters, and this is particularly useful when dealing with multiple features and the need to select optimal separating planes between classes. Support vector machines (SVM) [37] are quickly becoming the most popular choice of machine learning approach as they achieve high classification accuracies and have recently been implemented at the circuit level with low-power consumptions [38–40].

4.2.1 Analog Signal Processing

The physiological world that wearable sensors are attempting to monitor is intrinsically analog. Signals such as the EEG, ECG, or glucose concentration vary continuously and in continuous time. In contrast, the world of smartphones, PCs, and the Internet is digital with data represented by strings of binary data (either 0 or 1). These numbers can only represent finite, quantized input values and are taken at discrete time points at a particular sampling frequency. At some point a conversion between the two domains must take place, and this leads to a design choice over which domain to use when implementing wearable algorithms.

In 1990 Eric Vittoz published work on the fundamental power consumption limits of analog and digital processing, which has been since expanded on several times [41–43]. In the analog domain, the basic building block is taken as the integrator, modeled as an ideal transconductor charging and discharging a capacitor at frequency f. (A transconductor is an analog circuit block that outputs a current directly proportional to the input voltage.) The minimum power consumption required for this is found as [43]

$P_{min}=8kT·f·SNR$ (17)

(17)

where k is Boltzmann’s constant, T the temperature, and SNR the signal-to-noise ratio.

Similarly, in the digital domain the minimum required power consumption can be found by considering how many elementary operations are required, and the power consumption per elementary operation, E_tr. For a single pole digital filter this is estimated as [43]

$P_{min}=50B^2·f·E_{tr}$ (18)

(18)

where B is the digital word length in bits. In general, E_tr scales with the size of the CMOS technology used for the circuits, down to a fundamental noise governed limit.

These power equations are intended as fundamental limits and so based upon assumptions, in particular that the analog circuits are limited only by the noise floor. Several further bounds have also been derived since these, including ones that assume process variations and the matching of transistors further limits the analog circuits, and ones that offer more general modeling approaches [44,45]. Nevertheless, the underlying trends that (17) and (18) show are illustrative and widely accepted. They are visualized in Figure 9.

This shows that while the fundamental digital limit is well below the analog one, the practical limit can be a lot higher. Moreover, the analog limit is a strong function of the SNR ratio, and hence dynamic range, while for values over 6 bits the digital limit is a much weaker function. The result is that analog processing is generally accepted to be superior for low dynamic range applications. There are numerous sources that note the important role of analog processing systems in such applications, both presently and into the future (see, e.g., [24,45–47]). As a result, several of the signal-processing algorithms considered in section 4.3 incorporate some form of analog signal processing.

Beyond these general trends, however, determining the precise cross-over point for switching between analog and digital processing is very difficult for a particular circuit topology. In fact, even if this was known, the dynamic range of many physiological signals is highly debatable. The EEG systems considered in Table 1 used everywhere between 8 and 24 bits, while classical pen writer-based systems had a range of approximately 7 bits [48]. A key challenge is that once processing is started in the analog domain, additional ADCs to take the results into the digital domain want to be avoided, which means that all of the processing must be analog.

4.2.2 Fully Custom Hardware

The next choice is on the general design approach: to use generic off-the-shelf components that are easily available commercially or to fabricate custom-designed microchips that implement just the algorithm operations of interest and which can be highly optimized for the wanted application, or a mixture of the two. The general trade-off in performance is illustrated in Figure 10.

In general, the fully custom microchip is the preferred option as it allows complete customization, and so there are no possible excess blocks that are present but not 100% necessary. By implementing everything on the same silicon chip significant miniaturization can also be achieved compared to buying multiple chips and needing a larger PCB to connect everything together.

It is important to highlight that while this is the route to best performance it is inflexible, time consuming, and expensive. It is also not guaranteed to deliver the best performance, and careful design is required to minimize power consumption. For example, Figure 9 showed that the power consumption of digital processing is heavily dependent on the technology used to fabricate the microchip: the smaller the technology the lower the power consumption. However, for prototype runs and academic use the smallest processing nodes can be prohibitively expensive, potentially making off-the-shelf-devices that can use such nodes (due to having large fabrication runs) a better design choice.

This said, at present all of the algorithms investigated in section 4.3 use some form of custom microchip and there is little doubt that, while it presents significant design challenges, it is the best approach for realizing wearable algorithms today.

4.3.1 Generic Processors

Our sensor node in section 2 was based on the MSP430 as an easy-to-use, easily available low-power platform. However, in active mode the power consumption was 5.5 mW (at 10 MHz clock, 2.2 V supply). Thus, to realize microWatt levels of power consumption this MSP430 must be powered down for very large amounts of time, limiting the signal processing that can be provided.

There have been a number of recent publications that implement platforms compatible with the MSP430 instruction set allowing algorithm code to be directly re-used, but with a reduced power consumption. The platform described in [59] presented such an architecture consuming 175 μW in active mode (at 25 MHz clock, 0.4 V supply). Note that this was partly achieved by the use of an advanced 65 nm CMOS technology, and for very low-power use the off/leakage current is substantial: 1.7 μW. No specific algorithm was presented for use on this processor and so it is not included in Table 5.

In contrast [51] presented a high-performance general processor based on the CoolFlux platform rather than the MSP430 instruction set. This was used to implement an ECG heart beat detection algorithm that consumed only 13 μW (single-channel analysis only). In active mode the processor core power consumption is 1.45 mW, with a high 100 MHz clock.

Analog signal processing is also possible on generic platforms, with [60] presenting a programmable analog chip operating from 2.4 V. This demonstrated an analog FIR filter that could be used for feature extractions and consumed 7 μW at 1 MHz, although again no full algorithm was presented.

4.3.2 Generic Processors with Accelerators

As seen in Figure 8, the main stages in a wearable algorithm are the feature extraction and classification. To improve power performance these stages can therefore be implemented in dedicated hardware while the rest of the algorithm is still implemented in software on a processing core. An algorithm for seizure detection based upon frequency band changes calculated using the FFT was presented in [36]. By providing dedicated hardware for calculating the FFT, while running the rest of the algorithm on a customized ARM Cortex M3 processor, this achieved an 18 times reduction in the power consumption with the total power being less than 1 μW. No measure of the algorithm detection performance was given, however.

Alternatively, [38] used a customized MSP430 core for calculating the features and then an SVM accelerator for reducing the energy impact of the classification stage. The rationale being that the features are often specific to an application, while the classification engine (the SVM) could be re-used in many different situations. This acceleration reduced the classification energy costs by up to 144 times compared to a software-only implementation, although for EEG processing the energy per classification is 273 μJ. Thus, if a fast update rate is required, the total power consumption may still be quite high. Similarly, [39] built upon this to also accelerate some of the feature generations.

4.3.3 Fully Hardware Electronics and Design Trends

Most of the works considered in Table 5 do not use any specific software platform and instead achieve very low-power consumption by using only dedicated and highly customized hardware circuits. While there are many different approaches to realizing low-power fully custom electronics, nevertheless a number of common design trends are seen.

Firstly, very low supply voltages (typically in the 0.5–1 V range, and down to 0.32 V in [55]) are widespread. This directly reduces the power consumption (as P=VI), but has a big impact on the operation speed of a circuit [55]. Physiological signals are normally low frequency, typically below 1 kHz, and so this trade-off is often acceptable provided that a large number of operations are not required. In addition, often multiple power zones are used with different supply voltages and clock speeds provided to different parts of a single chip depending on the processing required at a particular time. For example, [36] had 18 different voltage domains, while [52] had 15. Dynamic voltage scaling (allowing speed scaling), clock gating (where the clock is disconnected to prevent unnecessary switching), and power gating (where entire sections are turned off to reduce leakage currents) form different aspects of these multiple power zones.

Secondly, very few of the considered circuits are based purely on conventional architectures and a recurring theme is the use of new and simplified topologies. For example, [54] introduces a small modification to the classification process with a small impact on classification performance, but which more than halves the number of circuit blocks required to implement it. A new digital filter topology was introduced in [40], while [55] only used integer coefficients in the filter stages to simplify the multiplications required. The objective with these approaches is to minimize the system complexity and to minimize the transistor count. Doing this gives fewer transistors to power, fewer sources of leakage current, and hence power savings.

The third trend is for the use of analog signal processing, which is used in four of the algorithms considered and is a very powerful method for minimizing the transistor count. A hybrid approach was used in [31] and [56], whereby analog signal processing was combined with an off-the-shelf MSP430 for motion artifact removal and heartbeat detection, respectively. Both [57] and [58] use fully analog approaches for calculating frequency information.

All but three of the entries in Table 5 make use of frequency information as part of the signal-processing algorithm. It is by far the most common basis for the feature extraction stage, and as a result highlights the potential for the use of analog signal processing in this role. In particular, a recent publication [58] presented a continuous wavelet transform (CWT) circuit for performing time-frequency analysis on scalp EEG signals while consuming a nominal power of only 60 pW. This CWT is only a feature extraction stage, but the picoWatt power level is far below any of the other circuit blocks considered in this chapter. It is achieved by the use of very low processing currents and a fully analog signal processing approach. It highlights the potential key role of analog signal processing will have in future systems, and that there is real opportunity to create truly wearable algorithms where the power source lasts longer than the useful life of the product.