Testing has become the number one challenge to nanometer system-on-chip (SOC) designs as a result of the unprecedented levels of design complexity and operating frequency made possible by advances in semiconductor manufacturing technologies. The vast demands and sophisticated applications in areas like consumer electronics have been the primary driving force for both the advances and the challenges in testing. The issues we face today range from digital to memory to analog and mixed-signal (AMS) testing and how these circuits interact with one another in the nanometer SOC design.

In digital testing, the requirement to operate circuits composed of tens to hundreds of millions of gates in the GHz range imposes severe challenges during manufacturing test. Because of the need for longer battery life or simply consuming less power, recent advances in low-power design methodologies require testing for these features without generating excessive heat. Multiple voltages and multiple frequencies have also stressed traditional test methodology. Challenges involve testing of these domains as well as synchronizers and level shifters. Test methodologies and solutions must be updated to reflect the constraints imposed by these new design methods and technologies. Furthermore, they must continue to provide quality and reliability measures that will improve manufacturing yield and defect level.

In memory testing, many novel built-in self-test (BIST) techniques have been developed in academia and practiced in industry to test large embedded memories, such as static random-access memory (SRAM) and dynamic random-access memory (DRAM) cores. Facing the trend that 80% of an SOC design could contain embedded memories in the nanometer design era, the need for advanced memory test techniques such as built-in self-diagnosis (BISD) and built-in self-repair (BISR) of memory defects is apparent and critical.

A common problem that arises in AMS testing within an SOC is that 10% of an SOC design that contains analog circuits could contribute to 90% of the total test cost during manufacturing test. Whereas the industry has found effective and efficient test solutions to significantly reduce the test cost for memory and digital logic circuits, the dominant analog test cost has erased the gain in other areas. Therefore, advanced architectures and new technologies to test the analog portion of the AMS, especially radiofrequency (RF), circuits must now also be developed to constrain the total test cost so that it stays within budget.

From the SOC testing point of view, test solutions must also address new fault models and failure mechanisms caused by manufacturing defects at the 65-nanometer (nm) process node and below. Based on the information extracted during layout, defect-based tests must supplement structural tests and functional tests in order to model and detect nontraditional manufacturing defects such as small delay defects and bridges. Advanced error and defect tolerance techniques are needed to cope with physical failures and tolerate soft errors. Test solutions must also be developed for silicon debug and diagnosis that can effectively and accurately help to localize fault sites. Better test solutions are needed for high-speed input/output (I/O) interfaces. Finally, specialized test solutions are required to target diverse network-on-chip (NOC), system-in-package (SIP), field programmable gate array (FPGA), and microelectromechanical system (MEMS) applications to ensure that testing does not become the bottleneck of SOC design and development.

As complementary metal oxide semiconductor (CMOS) technology scales toward 65 nm and below, more challenges and difficulties in circuit design and manufacturing will become prevalent as physical scaling is reaching the limit and quantum effects become more dominant. To sustain Moore’s law at the nanotechnology level (under 10-nm feature size), new device structures and circuits will be needed to either replace or augment the conventional CMOS technology. Some of the possible device structures are quantum-dot cellular automata (QCA), carbon nanotubes (CNTs), and silicon nanowires. They offer hope of very high logic density and performance, yet low power consumption at the sub-10-nm scale. However, many of these nanodevices are believed to have high defect rates and thus will impose new and extremely severe test challenges when compared to testing conventional CMOS devices. Therefore, test solutions are required before we can begin to look into the possibility of utilizing these nanodevices.

When we embarked on a mission in 2005 to write a textbook to cover advanced very-large-scale integration (VLSI) testing and design-for-testability (DFT) architectures not presented in other then-available textbooks, it became clear that it would be impossible to cover all topics in a comprehensive, yet concise manner. Although there are a number of ways to address this problem, we decided to present these advances in testing in two books that collectively address most, if not all, of the current test issues and solutions that have been developed in academia and industry.

Our first book, VLSI Test Principles and Architectures: Design for Testability, was published in 2006 as a fundamental textbook for undergraduate and graduate students and as a reference book for researchers and practitioners. That text covered basic VLSI test principles and DFT architectures with details on topics currently used in industry, including logic and fault simulation, test generation, logic BIST, test compression, logic diagnosis, memory testing, boundary scan and core-based testing, as well as analog and mixed-signal testing. Although that text included a brief overview of some advanced topics in Chapter 12 (Test Technology Trends in the Nanometer Age), it left aside many of the details of these advanced approaches. These advanced topics included delay testing, coping with physical failures, soft errors and reliability issues, FPGA testing, MEMS testing, high-speed I/O (link) testing, and RF testing.

This book, System-on-Chip Test Architectures, is the second textbook in our series and focuses on the details of the aforementioned advanced topics. Given the fact that test technology must cover techniques from the chip to board to system level, including the nanotechnology scale, we continue to face the same dilemma as we did with our first book—that is, the inclusion of all topics. Thus, we have decided to focus this text on SOC applications. In addition, the text includes chapters devoted to other topics that are relevant to SOC. These include system/network-on-chip testing, system-in-package testing, low-power testing, design for debug and diagnosis, design for manufacturability and yield, and software-based self-testing. Topics beyond this scope as well as ideas that are still under development and have not yet reached industrial SOC applications are left as subjects of future books; however, we give an overview of some of these promising techniques in many of the chapters. Memory testing as well as the Institute of Electrical and Electronics Engineers (IEEE) boundary scan and core-based test standards used in SOC testing (including 1149.1, 1149.4, 1149.6, and 1500) were covered extensively in the first book and, as a result, are not repeated in this book; instead the reader is referred to the first book and its associated references for details on these topics. It should be noted, however, that new material related to these topics is included in a number of chapters in this book.

The advanced topics covered in this book can also be categorized into multiple sections, with each section consisting of multiple chapters. They are as follows:

Each chapter of this book follows a specific format. The subject matter of the chapter is first introduced, with a historical perspective provided, if applicable. Related methods are explained in detail next. Then, industry practices, if applicable, are described before concluding remarks. Each chapter (except Chapter 17) contains a variety of exercises to allow this book to be used as a textbook for an advanced course in testing. Every chapter concludes with acknowledgment to contributors and reviewers and a list of references.

Chapter 1 introduces system-on-chip (SOC) testing. It begins with a discussion of the importance of testing as a requisite for achieving manufacturing quality and then identifies test challenges of the nanometer design era. This is followed by a brief overview of some of the IEEE boundary scan and core-based test standards that are widely used within industry (including 1149.1, 1149.4, 1149.6, and 1500). SOC examples practiced in industry are shown to illustrate the test challenges we face today.

Chapter 2 provides an overview of the most important test architectures for digital logic testing. Three basic design-for-testability (DFT) techniques widely used in industry are covered first: scan design, logic built-in self-test (BIST), and test compression. For each DFT technique, fundamental and advanced test architectures suitable for low-power and at-speed applications are discussed. The remainder of the chapter is devoted to random-access scan, a promising alternative to scan design for test power reduction.

Chapter 3 covers fault-tolerant design techniques that are applicable to both SOC designs and system applications. As the topic is quite broad, care is taken to describe widely used coding methods and fault tolerance schemes in an easy-to-grasp manner with extensive illustrations and examples. The chapter lists applications where the discussed techniques can be utilized.

Chapter 4 is devoted to both system-on-chip (SOC) and network-on-chip (NOC) test architectures. Various techniques for test access and test scheduling are thoroughly examined and presented. The chapter includes a discussion of the similarities and differences between the two as well as examples of each. Industrial designs are studied to show how these techniques are applicable to SOC and NOC testing.

Chapter 5 describes important test cost and product quality aspects of packing multiple dies in a system-in-package (SIP). After an introduction to the basic technologies, specific test challenges are presented. A number of bare-die test techniques to find known-good-dies are subsequently described. Functional system test and embedded component test techniques are then presented to test the SIP at the system level. The chapter ends with a brief discussion of future SIP design and test challenges related to nanometer technologies.

Chapter 6 addresses the testing of delay faults. The main focus of this chapter is on testing defect-based delay faults, often called small delay defect testing. Without loss of generality, however, conventional yet efficient delay fault simulation and test generation techniques for transition, gate-delay, and path-delay faults are first described. Advanced fault simulation and test pattern generation techniques associated with defect-based delay faults are then explained in detail.

Chapter 7 is devoted to low-power testing. After providing the motivations for reducing power during testing, power modeling and terminology used in the chapter are given. The main issues of excessive test power are then described. The remainder of the chapter is devoted to providing an overview of structural and algorithmic solutions that can be used to alleviate the issues raised by excessive power consumption during test application for digital nanometer designs.

Chapter 8 covers the full spectrum of defect-based test methods to cope with physical failures, soft errors, and reliability issues. First, new fault models are developed and solutions are presented to deal with noise-induced signal integrity issues. Defect-based tests are then discussed to further screen new defect-induced manufacturing faults. Finally, the rest of the chapter is devoted to illustrating adaptive designs and error-resilient architectures to tolerate soft errors and manufacturing faults.

Chapter 9 delves into the emerging hot topics of design for manufacturability (DFM) and design for yield (DFY). The chapter first describes in detail how lithography and variability during the manufacturing process can affect yield and induce defects. Then, innovative DFM and DFY techniques to improve yield and reduce defect level are explained in detail.

Chapter 10 is devoted to silicon debug and diagnosis, with heavy emphasis on design-for-debug architectures at the logic, circuit, and layout levels. This is complemented by an overview of common probing and diagnosis technologies for both wirebond and flip-chip packaging. The chapter also touches on system-level debug so as to link system issues back to silicon implementations. Finally, some of the future challenges unique to debug and diagnosis are also presented.

Chapter 11 provides a comprehensive discussion of software-based self-testing. The idea is to use on-chip programmable resources such as embedded processors to perform self-test and self-diagnosis. After explaining the basic concepts, various software-based self-test techniques are described to target processor cores, global interconnects, nonprogrammable cores, and analog and mixed-signal (AMS) circuits. Self-diagnosis techniques are also covered.

Chapter 12 addresses testing field programmable gate arrays (FPGAs) beginning with an overview of general FPGA architectures and operation. Following a discussion of the test challenges associated with FPGAs, various test approaches for FPGAs are described. The remainder of the chapter focuses on BIST and diagnosis of the programmable logic and routing resources in FPGAs. The chapter also presents new techniques for testing specialized cores such as configurable memories as well as new directions in FPGA testing using embedded processor-based on-chip reconfiguration.

Chapter 13 covers the testing of microelectromechanical systems (MEMS) devices that present new and interesting challenges as compared to the testing of microelectronics. This is partially because MEMS devices are designed to physically interact with the environment in which they operate. MEMS testing considerations, methods, and examples are presented, along with DFT and BIST techniques that have been proposed and implemented in commercially available MEMS devices.

Chapter 14 is devoted to high-speed parallel/serial I/O link testing at both component and system levels. This chapter starts with a discussion on signaling properties, such as jitter, noise, and bit error rate (BER), which impact the choice of high-speed I/O architectures. At the component level, instrumentation-based test methods for I/O characterization and DFT-assisted test methods for manufacturing test are first explained in detail. Novel DFT approaches for testing emerging circuits at signaling rates over 1 GHz, such as equalization and compensation, are also covered. At the system level, interconnect test methods using the IEEE 1149.1 and 1149.6 standards as well as the interconnect BIST (IBIST) method are then included.

Chapter 15 addresses testing analog and mixed-signal (AMS) circuits that are more frequently being incorporated in an SOC. The first book presented many of the basic issues and techniques for testing AMS circuits along with examples of testing discrete analog circuits. Although some of these basics are repeated in this book, this chapter focuses on mixed-signal BIST architectures that can be included in SOC implementations to test the analog cores and modules.

Chapter 16 extends AMS testing concepts to issues and techniques associated with testing radiofrequency (RF) circuits. This chapter outlines key test specifications for RF circuits and systems as well as covers industry practices for such devices. In addition, this chapter explains the operating principles of various test instrumentations widely used for AMS and RF testing and describes general automatic test equipment (ATE) architecture. From a production test perspective, concepts related to accuracy and repeatability are also discussed.

Chapter 17 is devoted to test technology trends for emerging nanotechnologies that are beyond the conventional CMOS. It introduces novel devices, circuits, architectures, and systems that have been proposed as alternatives to the CMOS at nanoscale dimensions, such as resonant tunneling diodes (RTDs), quantum-dot cellular automata (QCA), silicon nanowires, single electron transistors, and carbon nanotubes (CNTs). Defect characterization, fault modeling, test generation techniques, and the built-in self-test of systems built using such nanodevices, particularly for RTDs, QCA, and crossbar arrays, are discussed. Defect tolerance techniques for carbon nanotube field effect transistors (CNFETs) are also covered.