Some percentage of the manufactured devices are expected to be faulty because of manufacturing defects. The yield of a manufacturing process is defined as the percentage of acceptable parts among all parts that are fabricated:

There are two types of yield loss: catastrophic and parametric. Catastrophic yield loss is due to random defects, and parametric yield loss is due to process variations. Automation of and improvements in an integrated circuit (IC) fabrication process line drastically reduce the particle density that creates random defects over time; consequently, parametric variations resulting from process fluctuations become the dominant reason for yield loss.

Methods to reduce process variations during fabrication are generally referred to as design for yield (DFY). The circuit implementation methods to avoid random defects are generally referred to as design for manufacturability (DFM). Broadly speaking, any DFM method helps to increase manufacturing yield and thus can be considered as a DFY method. Manufacturing yield relates to the failure rate λ. The bathtub curve shown in Figure 1.2 is a typical device (or system) failure chart indicating how early failures, wearout failures, and random failures contribute to the overall device (or system) failures.

Figure 1.2. Bathtub curve.

The infant mortality period (with decreasing failure rate) occurs when a product is at its early production stage. Failures are mostly due to poor process or design which leads to poor product quality and thus the product should not be shipped during this period to avoid massive field returns. The working life period (with constant failure rate) represents the product “working life.” Failures during this period tend to occur randomly. The wearout period (with increasing failure rate) indicates the “end of life” of the product. Failures during this period are due to age defects, such as metal fatigue, hot carriers, electromigration, dielectric breakdown, etc. For electronic products, this period is of less concern because they often would not enter this region because of technology advances and obsolescence.

When ICs are tested, the following two undesirable situations may occur:

These two outcomes are often due to a poorly designed test or the lack of design for testability (DFT). As a result of the first case, even if all products pass acceptance test, some faulty devices will still be found in the manufactured electronic system. When these faulty devices are returned to the IC manufacturer, they undergo failure mode analysis (FMA) for possible improvements to the IC development and manufacturing processes [Amerasekera 1987]. The ratio of field-rejected parts to all parts passing quality assurance testing is referred to as the reject rate, also called the defect level:

For a given device, the authors in [McCluskey 1988] showed that defect level DL is a function of process yield Y and fault coverage FC:

The defect level provides an indication of the overall quality of the testing process [Williams 1981] [Bushnell 2000] [Jha 2003]. Generally speaking, a defect level of 500 parts per million (PPM) may be considered to be acceptable, whereas 100 PPM or lower represents high quality. The goal of six sigma manufacturing, also referred to as zero defects, is 3.4 PPM or less.

Traditionally, component reliability, also called device reliability, is measured by acceptable defect level (defective PPM), failure rate per 1000 hours, noise characteristics, etc. Because process yield and fault coverage affect defect level, reliability screen methods, such as stress testing (through burn-in) and I_DDQ testing (by measuring the device leakage currents), are often used to accelerate the failure rate with pre-selected test sets. These methods, called reliability screens, are mainly developed to weed out weak devices before mass production so as to reduce test escapes that will cause field returns. Once weak devices are found, FMA is performed to analyze, debug, locate, and correct the failures so the process yield can be increased later.

When a manufactured electronic system is shipped to the field, it may also undergo testing as part of the installation process to ensure that the system is fault-free before placing the system into operation. During system operation, a number of events can result in a system failure; these events include single-event upsets (SEUs), electromigration, and material aging. Suppose the state of system operation is represented as S, where S = 0 means the system operates normally and S = 1 represents a system failure. Then S is a function of time t, as shown in Figure 1.3.

Figure 1.3. System operation and repair.

Suppose the system is in normal operation at t = 0, it fails at t₁, and the normal system operation is recovered at t₂ by some software modification, reset, or hardware replacement. Similar failure and repair events happen at t₃ and t₄. The duration of normal system operation (T_n), for intervals such as t₁ – t₀ and t₃ – t₂, is generally assumed to be a random number that is exponentially distributed. This is known as the exponential failure law. Hence, the probability that a system will operate normally until time t, referred to as system reliability, is given by:

where λ is the failure rate. Because a system is composed of a number of components, the overall failure rate for the system is the sum of the individual failure rates (λ_i) for each of the k components:

The mean time between failures (MTBF) is given by:

Similarly, the repair time (R) is also assumed to obey an exponential distribution and is given by:

where μ is the repair rate. Hence, the mean time to repair (MTTR) is given by:

The fraction of time that a system is operating normally (failure-free) is called the system availability and is given by:

This formula is widely used in reliability engineering; for example, telephone systems are required to have system availability of 0.9999 (simply called four nines), whereas high-reliability systems may require seven nines or more.

In general, system reliability requires the use of spare components or units (made of components) in a fault-tolerant system to increase the system availability [Siewiorek 1998]. Device reliability, on the other hand, depends on reliability screens in very-large-scale-integration (VLSI) or SOC devices to improve process yield and hence the device defect level. Unfortunately, existing reliability screens are becoming either quite expensive (as in the case of burn-in) or ineffective (as in the case of using I_DDQ testing) for designs manufactured at 90 nm or below. Fundamentally new long-term solutions must be developed for reliability screens and may include significant on-die hardware for stressing or special reliability measurements, as indicated in [SIA 2004].

Today, little evidence shows that higher device reliability can prolong the working life of a device, but in theory, it could extend the availability of the system when embedded with such devices. Fault-tolerant architectures commonly found in high-reliability systems are now applied to robust SOC designs to tolerate soft errors and to make them error-resilient. These error resilience (or defect tolerance) schemes are now referred to as design for reliability (DFR).

The success of scan-based DFT techniques from the mid-1970s through the mid-1980s led to their adaptation for testing interconnect and solder joints on surface mount PCBs. This technique, known as boundary scan, eventually became the IEEE 1149.1 standard [IEEE 1149.1-2001] and paved the way for floating vias, microvias, and mounting components on both sides of PCBs to reduce the physical size of electronic systems. Boundary scan provides a generic test interface not only for interconnect testing between ICs but also for access to DFT features and capabilities within the core of an IC as illustrated in Figure 1.4 [IEEE 1149.1-2001] [Parker 2001]. The boundary-scan interface includes four mandatory input/output (I/O) pins for Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), and Test Data Output (TDO). A test access port (TAP) controller is included to access the boundary-scan chain and any other internal features designed into the device, such as access to internal scan chains, built-in self-test (BIST) circuits, or, in the case of field programmable gate arrays (FPGAs), access to the configuration memory. The TAP controller is a 16-state finite state machine (FSM) with standardized state diagram illustrated in Figure 1.4b where all state transitions occur on the rising edge of TCK based on the value of TMS shown for each edge in the state diagram. Instructions for access to a given feature are shifted into the instruction register (IR) and subsequent data are written to or read from the data register (DR) specified by the instruction (note that the IR and DR portions of the state diagram are identical in terms of state transitions and TMS values). An optional Test Reset (TRST*) input can be incorporated to asynchronously force the TAP controller to the Test Logic Reset state for application of the appropriate values to prevent back driving of bidirectional pins on the PCB during power up. However, this input was frequently excluded because the Test Logic Reset state can easily be reached from any state by setting TMS = 1 and applying five TCK cycles.

Figure 1.4. Boundary-scan interface: (a) boundary-scan implementation and (b) TAP controller state diagram.

The basic boundary-scan cell (BSC) used for testing interconnect on a PCB is illustrated in Figure 1.5a along with its functional operation. A more complex construction of the triple BSC bidirectional I/O buffer is illustrated in Figure 1.5b. The bidirectional buffer illustrates the need for the double-latched scan chain design of the basic BSC to prevent back driving of other bidirectional buffers on a PCB while shifting in test patterns and shifting out test responses. The Update latch holds all values (including tri-state control value) stable at the pads during the shifting process. Once the test pattern is shifted into the boundary-scan chain via the Capture flip-flops, the Update DR state of the TAP controller (see Figure 1.4b) transfers the test pattern to the Update latches for external applications to the PCB interconnect testing or access to DFT features and capabilities within the core of an IC.

Figure 1.5. Boundary-scan cells: (a) boundary-scan cell (BSC) and operation modes and (b) bidirectional buffer with BSCs.

The design of the basic BSC shown in Figure 1.5a also facilitates application of test patterns at the input buffers to the internal core of a device, as well as capture of output responses from the internal logic at the output buffers. This internal test, referred to as INTEST in the IEEE 1149.1 standard, is an optional but valuable instruction, although it is not always implemented in an effort to reduce the area overhead and performance penalty associated with boundary scan. The external test of PCB interconnects, referred to as EXTEST, is a mandatory instruction to test the PCB interconnects for which boundary scan was intended. Another mandatory feature is the BYPASS instruction and uses the bypass register (shown in Figure 1.4a and consisting of a single flip-flop), which allows the entire boundary-scan chain to be bypassed to provide faster access to other devices on the board with the daisy-chained boundary-scan interface.

The boundary-scan interface is significant for several reasons. Obviously, it provides an approach to testing interconnects on digital PCBs and overcomes the test problems encountered with surface mount technology emerging in the late 1980s. Although boundary scan does not directly address test logic internal to the devices on a PCB, it does provide a standardized interface that can be used to access internal test mechanisms, such as scan chains and BIST circuits, designed specifically for the internal logic testing. Perhaps more important, it provides a proven solution to the test problems that would later be encountered with SOC and SIP implementations. Because the basic idea is to incorporate a large number of complex cores in a single chip (in the case of an SOC) or a single package (in the case of an SIP), testing interconnects between these modules can be performed in a manner similar to boundary scan. Hence, the IEEE 1149.1 standard can be, and is, extended and adapted to test the interconnections between the cores.

Although the IEEE 1149.1 boundary-scan standard has been the mainstay for board-level interconnect testing since the early 1990s, it is becoming ineffective to test modern-day high-speed serial networks that are AC-coupled (a “blocking” capacitor is placed in the net between the driver and receiver). Also, most high-speed serial networks use differential I/O pads.

The IEEE 1149.6 standard [IEEE 1149.6-2003] was introduced to address these problems with multigigabit I/Os. It is an extension of the IEEE 1149.1 standard to deal with this differential, AC-coupled interface as illustrated in Figure 1.6. When testing the two nets using the IEEE 1149.1 standard, the presence of the coupling capacitor in AC-coupled networks “blocks” DC signals. As a result, the DC level that is applied to the net during a boundary-scan EXTEST instruction decays over time to an undefined logic level. This places a minimum frequency requirement on TCK that the 1149.1 standard cannot support. The IEEE 1149.6 standard addresses this problem by capturing the edges of data transitions instead of capturing data levels; hence, the minimum TCK frequency requirement is removed.

Figure 1.6. Differential, AC-coupled network.

IEEE 1149.6 addresses the problem of differential signaling by adding a single, boundary-scan cell, internal to the driver and boundary-scan cells on each input to the functional, differential receiver. The single boundary-scan cell on the driver side minimizes the loading and performance impact. Boundary-scan cells on each input of the receiver provide better coverage than a single boundary-scan cell implementation.

The IEEE 1149.6 circuit is composed of four parts: (1) the analog test receiver, (2) the digital driver logic, (3) the digital receiver logic, and (4) the 1149.6 test access port (TAP). Each part is discussed in the subsequent paragraphs.

The analog test receiver is the most critical part of the 1149.6 implementation because it is the test receiver that is able to capture transition edges. The test receiver uses a “self-referenced” comparator, along with voltage and delay hysteresis to capture a valid edge and filter any unwanted noise. The test receiver uses a low-pass filter to create a delayed reference signal.

The digital driver logic is a simple extension to the IEEE 1149.1 driver. Unlike the 1149.1 driver, the 1149.6 driver is required to drive a pulse when it is executing the (1149.6) EXTEST_PULSE (or EXTEST_TRAIN) instruction. The EXTEST_PULSE instruction is used to drive the output signal to the opposite state, wait for the signal to fully decay, and then drive the signal to the correct value (this is the value that gets captured). By allowing the signal to fully decay, the maximum voltage swing is generated on the next driven edge, allowing for better capture by the analog test receiver. In rare cases a continuous waveform may be required for some high-speed logic. In this case, the EXTEST_TRAIN instruction is used instead of the EXTEST_PULSE to generate a continuous waveform based on TCK. The digital driver logic must also support the 1149.1 EXTEST instruction. It simply extends the 1149.1 logic by multiplexing the 1149.6 signal into the 1149.1 shift/update circuit, after the update flip-flop.

The digital receiver logic takes the output of the analog test receiver and sets a capture flip-flop to a corresponding logical zero or one. The digital test receiver logic also ensures that a valid transition has been captured on every test vector by initializing the state of the capture memory before the transition is driven onto the net. Without this initialization, it would be impossible to determine if two sequential transitions in the same direction (positive or negative) occurred, or if only one transition occurred (i.e., if a positive transition occurs and is captured in the memory, and the subsequent test vector also generates a positive transition, there is no way to determine if the second transition occurred without clearing the contents of the capture memory before the second transition occurs).

Changes were made to the 1149.1 TAP to allow the 1149.6 driver logic to generate pulses. It was determined that the 1149.6 TAP would require an excursion through the Run-test/Idle state to allow for the generation of the pulse or pulses required by the EXTEST_PULSE and EXTEST_TRAIN instructions. Entry into the Run-test/Idle state during the execution of either EXTEST_PULSE or EXTEST_TRAIN would generate an “AC Test” signal. This would in turn cause the data which were driven onto the net during the Update-DR state to be inverted upon entry into the Run-test/Idle state (on the first falling edge of TCK) and to be inverted again on the exit from Run-test/Idle (on the first falling edge of TCK in the Select-DR state). As previously mentioned, the data signal is inverted, and then allowed to fully decay, in order to guarantee the maximum transition from the driver.

In summary, the IEEE 1149.6 standard is an extension of the IEEE 1149.1 standard; as a result, the 1149.6 standard must comply with all 1149.1 rules. The 1149.6 logic allows for testing of AC-coupled networks by capturing edges of pulses that are generated by 1149.6 drivers. A special, analog test receiver is used to capture these edges. The 1149.6 receiver logic is placed on both inputs of the differential receiver logic. Special hysteresis logic filters out noise and captures only valid transitions. These extensions allow for an equivalent level of testing (to 1149.1) for high-speed digital interconnects.

The use of BIST circuits and other embedded instruments is becoming more prevalent as devices become larger, faster, and more complex. These instruments can increase the device’s test coverage, decrease test and debug time, and provide correlation between the system and ATE environments. Examples of some of these instruments are logic BIST, memory BIST (for both internal and external memory), built-in pseudo-random bit sequence (PRBS) or bit-error-rate testing for serializer/deserializer (SerDes), power management and clock control logic, and scan register dump capabilities. Currently, many of these instruments are not documented or are documented in an ad hoc manner. This makes access to the instruments difficult and time consuming at best, and oftentimes can make access impossible. The lack of a standard interface (through the IEEE 1149.1 TAP) to these instruments makes automation virtually impossible as well.

The proposed standard P1687 (IJTAG) will develop a standard methodology to access embedded test and debug features via the IEEE 1149.1 TAP [IEEE P1687-2007]. The proposed standard does not try to define the instruments themselves but instead tries to standardize the description of the embedded features and the protocols required to communicate with the embedded instrument. The proposed standard may also define requirements for the interface to the embedded features. This proposed standard is an extension to IEEE 1149.1 and uses the 1149.1 TAP to manage configuration, operation, and collection of data from the embedded instrument. More information can be found on the IEEE P1687 Web site (http://grouper.ieee.org/groups/1687).

There are a number of important differences between PCB and SOC (or SIP) implementations that must be considered when testing cores of an SOC [Wang 2006]. Cores can be deeply or hierarchically embedded in the SOC requiring a test access mechanism (TAM) for each core. The number and types of cores can be diverse and provided by different vendors with different types of tests and test requirements, and in the case of intellectual property (IP) cores, there may be little, if any, detailed information about the internal structure of the core. Although the clock rate of information transfer between internal cores is typically much high than that of the I/O pins of the SOC, additional ports to a core are much less costly compared to additional pins on a package. As a result, boundary scan alone does not provide a complete solution to the problem of testing the cores in an SOC. Therefore, the IEEE 1500 standard was introduced to address the problems associated with testing SOCs [Seghal 2004] [IEEE 1500-2005].

The most important feature of the IEEE 1500 standard is the provision of a “wrapper” on the boundary (I/O terminals) of each core to standardize the test interface of the core. An overall architecture of an SOC with N cores, each wrapped by an IEEE 1500 wrapper, is shown in Figure 1.7, and the structure of a 1500 wrapped core is given in Figure 1.8. The wrapper serial port (WSP) is a set of I/O terminals of the wrapper for serial operations, which consists of the wrapper serial input (WSI), the wrapper serial output (WSO), and several wrapper serial control (WSC) terminals. Each wrapper has a wrapper instruction register (WIR) to store the instruction to be executed in the corresponding core, which also controls operations in the wrapper including accessing the wrapper boundary register (WBR), the wrapper bypass register (WBY), or other user-defined function registers. The WBR consists of wrapper boundary cells (WBCs) that can be as simple as a single storage element (flip-flop for observation only), similar to the BSC shown in Figure 1.5a, or a complex cell with multiple storage elements on its shift path.

Figure 1.7. Overall architecture of a system per the IEEE 1500 standard.

Figure 1.8. A core with the IEEE 1500 wrapper.

The WSP supports the serial test mode similar to that in the boundary-scan architecture, but without using a TAP controller. This implies that the serial control signals of 1500 can be directly applied to the cores and hence provide more test flexibility. For example, delay testing that requires a sequence of test patterns to be consecutively applied to a core can be supported by the 1500 standard. As shown in Table 1.1, in addition to the series I/O data signals WSI and WSO, the WSC consists of six mandatory terminals (WRCK, WRSTN, SelectWIR, CaptureWR, UpdateWR, and ShiftWR), one optional terminal (TransferDR), and a set of optional clock terminals (AUXCKn). The functions of CaptureWR, UpdateWR, and ShiftWR are similar to those of CaptureDR, UpdateDR, and ShiftDR of boundary scan, respectively (see Figure 1.5a). The SelectWIR is used to determine whether to select the WIR or not. This is required because no TAP controller is available for the 1500 standard. The TransferDR is used to transfer test data to correct positions on the shift path of a WBC when the shift path contains multiple storage elements. This enables multiple test data to be stored in consecutive positions of the shift path and hence allows delay testing to be carried out. Finally the AUXCKn terminals can be used to test cores with multiple clock domains.

In addition to the serial test mode, the 1500 standard also provides an optional parallel test mode with a user-defined, parallel test access mechanism (TAM). Each core can have its own wrapper parallel control (WPC), wrapper parallel input (WPI), and wrapper parallel output (WPO) signals. A user-defined parallel TAM, as summarized in the final three entries of Table 1.1 [IEEE 1500–2005], can transport test signals from the TAM-source (either inside or outside the chip) to the cores through WPC and WPI, and from the cores to the TAM-sink through WPO in a parallel manner; hence, it can greatly reduce the test time.

A variety of architectures can be implemented in the TAM for providing parallel access to control and test signals (both input and output) via the wrapper parallel port (WPP) [Wang 2006]. Some of these architectures are illustrated in Figure 1.9, including (1) multiplexed access where the cores time-share the test control and data ports, (2) daisy-chained access where the output of one core is connected to the input of the next core, and (3) direct access to each core.

Figure 1.9. Example of user-defined parallel TAM architectures: (a) multiplexed, (b) daisy-chain, and (c) direct access.

Although it is not required or suggested in the 1500 standard, a chip with 1500-wrapped cores may use the same four mandatory pins as in the IEEE 1149.1 standard for chip interface so that the primary access to the IEEE 1500 architecture is via the boundary scan. An on-chip test controller with the capability of the TAP controller in the boundary-scan standard can be used to generate the WSC for each core. This on-chip test controller concept can also be used to deal with the testing of hierarchical cores in a complex system [Wang 2006].

An additional problem encountered with the increasing complexity of SOCs is the ability to verify or debug a design once it has been implemented in its final medium, for example silicon. The IEEE 1500 standard can be used for core-level testing with some capability for debug [Marinissen 2002] [Zorian 2005]. However, the process of post-silicon qualification or debug is time consuming and expensive, requiring as much as 35% to 70% of the total time-to-market interval. This is due in part to limited internal observability but primarily to the fact that internal clock frequencies are generally much higher than can be accessed through IEEE 1500 circuitry. One solution to this problem of design for debug and diagnosis (DFD) is the insertion of a reconfigurable infrastructure used initially for silicon validation or debug, with later application to system-level test and performance measurement. The infrastructure includes a wrapper fabric similar in some ways to the 1500 wrapper but reconfigurable in a manner similar to the programmable logic and routing resources of an FPGA. In addition, a signal monitoring network is incorporated along with functions analogous to an embedded logic analyzer for in-system, at-speed triggering and capture of signals internal to the SOC [Abramovici 2006].

There are also mixed-signal SOC implementations that include analog circuitry not addressed by either the IEEE 1149.1 or 1500 standard. Boundary scan for PCBs was extended to include mixed-signal systems with both digital and analog components in the IEEE 1149.4 standard [IEEE 1149.4-1999]. The purpose of the IEEE 1149.4 standard is “to define, document, and promote the use of a standard mixed-signal test bus that can be used at the device and assembly levels to improve the controllability and observability of mixed-signal designs and to support mixed-signal built-in test structures in order to reduce both test development time and test cost, and to improve test quality.” Figure 1.10 shows a typical 1149.4 equipped IC and its PCB-level environment. At the chip level, an 1149.4 IC has two internal analog buses (AB1/AB2) connected to its analog pins. At the board level, AB1 and AB2 are connected to two board-level analog buses through two analog testability ports (AT1/AT2). Hence, one is able to access analog pins through the testability construct.

Figure 1.10. IEEE 1149.4 internal test configuration.

The IEEE 1149.4 standard defines test features to provide standardized approaches to (1) interconnect testing that tests the open/short of simple interconnects, (2) parametric testing that measures electrical parameters of extended interconnects with passive devices, and (3) internal testing that tests the functionality of on-chip analog cores.

An 1149.4-compliant design has a typical circuit architecture shown in Figure 1.11. In addition to boundary-scan circuitry for the digital domain, the standard includes an analog test access port (ATAP) which consists of a minimum of one analog test input and one analog test output connection. Connections between the two internal analog test buses (AB1 and AB2) and the ATAP are controlled by the test bus interface circuit (TBIC). The analog test buses provide connections to the analog boundary modules (ABMs), which are analogous to the BSCs in the digital domain. Each ABM (see Figure 1.12) includes switches that allow connection to AB1, AB2, a high voltage (V_H), a low voltage (V_L), a reference voltage (V_G), or an I/O pin of an analog core. This allows not only interconnect testing of analog signal nets on the PCB for opens and shorts, but perhaps more important, it allows for the test and measurement of passive components such as resistors and capacitors commonly used for filtering and coupling analog signal nets on a PCB [Wang 2006].

Figure 1.11. Typical IEEE 1149.4-compliant chip architecture.

Figure 1.12. IEEE 1149.4 analog boundary module (ABM).

The IEEE 1149.4 standard is a superset of the IEEE 1149.1 standard, so each component responds to the mandatory instructions defined in 1149.1 [IEEE 1149.1-2001]. Herein, three types of instruction are defined: (1) mandatory instructions, (2) optional instructions, and (3) user-defined instructions.

Mandatory instructions include (1) BYPASS that isolates the chip from the entire DFT construct; (2) SAMPLE/PRELOAD that captures a digitized snapshot of the analog signal on the pin or loads a digital data pattern to specify the operation of the ABM; (3) EXTEST that disconnects analog pins from the core to perform open/short and parametric testing of the interconnects; and (4) PROBE that connects analog pins to internal buses for allowing access to the pins from edge connectors of the board.

Optional instructions recommended in the standard include (1) INTEST for internal core testing based on the PROBE instruction; (2) RUNBIST for the application of BIST circuitry; (3) CLAMP for properly conditioning the pin to V_H, V_L, or V_G; (4) HIGHZ for isolating the pin; and (5) device identification register such as IDCODE and the USERCODE as defined in the IEEE 1149.1 standard. In addition, users can define their own instructions, which will be treated as the extension of optional instructions.

Based on the preceding instructions, open/short interconnect testing, extended interconnect measurement, and internal analog core testing can be executed. Let us use interconnect testing as an example to show how 1149.4 works. Without external instrument, the ABM can perform interconnect testing in general and open/short in particular, as shown in Figure 1.13. The tested wire (shown in bold in the figure) connects analog Pin1 of Chip1 to Pin2 of Chip2. The three-step test procedure is as follows:

Figure 1.13. Example for interconnect testing using the IEEE 1149.4 bus.

Normally, V_H and V_L are set to V_DD and V_SS, and V_TH is set to 0.5V_DD. The procedure detects static short faults and 1-to-0 and 0-to-1 transitions of open faults.

The most serious drawback of the 1149.4 standard is the parasitic effect associated with the long buses. A typical pin has a stray capacitance of 2~4 pF, a via has 0.5~1 pF, and a 1cm wire has 0.25~0.5 pF. Therefore, the bandwidth is severely limited by the stray capacitance of the bus and the stray resistance of the switches (in KΩ range). In that case, the standard recommends the replacement of passive switches with active current buffers and voltage buffers.

The wireless bioMEMS sensor developed at National Taiwan University is the first wearable prototype to detect C-reactive protein (CRP) based on nanomechanics [Chen 2006]. The CRP concentration in human serum is below 1μg/mL for a healthy person but may rise up to 100 or even 500 times in response to infection in the body. In [Blake 2003], the authors showed that high levels of CRP in the bloodstream raise the risk of a heart attack. One of the greatest benefits of this biosensor is that cardiovascular-event-related proteins, such as CRP, can be dissociated from anti-CRP by applying a low-frequency AC electric field (with 0.2 Hz 1 V electrical signal) to the sensor. This allows the design of a wireless label-free detection system for disease-related CRP using a microcantilever [Arntz 2003] with a safe “reusable” feature.

The CRP sensing mechanism is shown in Figure 1.15 [Chen 2006]. First, CMOS compatible silicon nitride is deposited on the silicon substrate. Next, a MEMS cantilever is fabricated by photolithography followed by micromachining technology. The optimum sensor size of a length of 200μm with each leg 40μm wide is determined by the balance among spring constant, bio-induced stress and stability in the flow field. On the top side of the cantilever, chromium (Cr), gold (Au), bio-linker, and anti-CRP are deposited. Chromium is adopted to improve the adhesion of gold to silicon nitride, whereas the gold layer is used to immobilize the bio-linker. The anti-CRP is bonded to the bio-linker for probing CRP. Specific biomolecular interactions between CRP and anti-CRP alter the intermolecular nanomechanical interactions within the bio-linker layer. As a result, the cantilever is bent. The bending of the cantilever can be measured by optical beam deflection or piezoresistive techniques. The authors adopted the former approach because of its excellent minimum detection limit of 0.1 nm.

Figure 1.15. CRP sensing mechanism using microcantilever.

To demonstrate how the prototype works, the authors in [Chen 2006] further set up an experiment, as shown in Figure 1.15. After placing a poly-dimethyl-siloxane (PDMS)-based “cap” above the functionalized cantilever, two microfluidic channels and one liquid chamber for reaction are formed. The reagents are injected into the channels and chamber using a syringe pump. A laser beam through the optically transparent PDMS cap is focused onto the tip of the cantilever with the help of a charge-coupled device (CCD) camera, thereby ensuring the alignment among the laser beam, the cantilever, and the position-sensitive detector (PSD). The function blocks of the wireless CRP measurement system are shown in Figure 1.16 [Chen 2006]. Custom commands from a personal computer (PC) are received by a 0.45V operated ASK receiver consisting of a common-source amplifier, gain stages, and a diode-RC demodulator. The 0.45 V operation is achieved by using low-threshold (0.2V) transistors. After decoding the commands, the microcontroller unit (MCU) activates the 8-bit charge-redistributed analog-to-digital converter (ADC) and preamplifier to convert the analog bio-signals measured by the commercially available PSD into digital values. Finally, an ASK transmitter comprising a ring oscillator and a common-source class-C power amplifier transmits the digital values to the PC for analysis.

Figure 1.16. Function blocks of the wireless CRP measurement system.

Fabricated at a 180-nm process node, the wireless ASK chip is operated at 500KHz and has a die size of 3.4 mm². Although this chip is small, the wireless CRP measurement system presents many test challenges, because it includes a microfluidic bioMEMS sensor, a PSD module, an RF transceiver (transmitter and receiver), an analog preamplifier, an ADC, and an MCU embedded with memory and analog circuits state control logic. Today, semiconductor lasers [Arntz 2003] and microlenses used in a compact disc (CD) player can be placed on top of the PDMS cap to replace the He-Ne laser, the reflected mirror, and the lens. A standard CMOS poly-resistor layer can be also used as the cantilever for the detection of the piezoresistive change caused by bending. Thus, the authors anticipate that the bioMEMS sensor, the semiconductor laser, and the microlenses can be also integrated with the PSD module and the wireless ASK circuit on the same die. This will make testing of this SOC device more challenging. Self-diagnosis and self-calibration might be needed to ensure the correct operation of the device all the time. When the device becomes implantable, it will require BISR.

The Cell processor [Pham 2005, 2006] co-designed by Sony, Toshiba, and IBM is one of the earliest network-on-chip (NOC) processors developed to address high-performance distributed computing. Built as the first-generation multiprocessor with a vision of bringing supercomputer power to everyday life, the Cell processor supports multiple operating systems including Linux and is designed for natural human interactions including photorealistic, predictable real-time response, and virtualized resource for concurrent activities. The processor architecture includes one power processor element (PPE), eight synergistic processor elements (SPEs), an element interconnection bus (EIB), a memory interface controller (MIC), a bus interface controller (BIC), a pervasive unit (PU) that supports extensive test, monitoring, and debug functions, a power management unit (PMU), and a thermal management unit (TMU). The chip was fabricated at a 90-nm process node and can operate at more than 4 GHz at a nominal voltage of 1.1 V or higher. The high-level chip diagram is shown in Figure 1.17.

Figure 1.17. The EIB in the Cell processor.

The PPE is a 64-bit dual-threaded processor based on the Power Architecture [Rohrer 2004]. The processor contains a power execution unit (PXU), 32-KB instruction and data caches (L1), and a 512-KB cache (L2). Each SPE contains a synergistic execution unit (SXU), which is an independent processor, and a 256-KB local store (LS). The EIB connects the PPE, the eight SPEs, the MIC, and the BIC. The EIB is central to the Cell processor. This coherent bus transfers up to 96 bytes per processor cycle. The bus is organized as four 16-byte-wide (half-rate) rings, each of which supports up to three simultaneous data transfers. A separate address and command network manages bus requests and the coherence protocol. With a dual-threaded PPE and eight SPEs, this Cell processor is capable of handling 10 simultaneous threads and over 128 outstanding memory requests.

The MIC supports two Rambus XDR memory banks. For added reliability, the MIC supports error correcting code (ECC) and a periodic ECC scrub of memory. For debug and diagnosis, the MIC also allows the processor to be stopped and its system state scanned out. The BIC provides two Rambus RRAC flexible I/O (FlexIO) interfaces with varying protocols and bandwidth capabilities to address differing system requirements. The interfaces can be configured as either two I/O interfaces (IOIF 0/1) or as an I/O and a coherent SMP interface (IOIF and BIF). Both MIC and BIC are operated asynchronously to the processor; hence, each bus contains speed-matching SRAM buffers and logic. The processor side operates at half the global processor clock rate, whereas the XDR side operates at one half the rate of the XDR interface and the FlexIO side operates at 1/2 or 1/3 the rate of the RRAC transceivers.

The PU (not shown in Figure 1.17) contains all of the global logic needed for basic functional operation of the chip, lab debug, and manufacturing test. To support basic functional operation of the chip, the PU contains a serial peripheral interface (SPI) to communicate with an external controller during normal operation, clock generation and distribution logic to enable the correct phase-locked loop (PLL) functions on the chip, and power-on-reset (POR) that systematically initializes all the units of the processor. The POR engine has a debug mode that allows its embedded 32 instructions to be single-stepped, skipped, or performed out of order. For lab debug and bring up, the PU contains chip-level global fault isolation registers to allow the operating system to quickly determine which unit generated an error condition and a performance monitor (PFM), which consists of a centralized unit connected to all functional units on the chip via a trace/debug bus to assist with performance analysis. An on-board programmable trace logic analyzer (TLA) captures and stores internal signals while the chip is running at full speed to assist with debug. An on-chip control processor, with an IEEE 1149.1 boundary-scan interface, is also available to help with debug. For manufacturing test, the PU supports 11 different test modes, including the array built-in self-test (ABIST), commonly referred to as memory BIST (MBIST), which tests all memories in parallel to reduce test time, and the logic BIST (LBIST) that includes a centralized controller in the PU and 15 LBIST satellites elsewhere in the design. At-speed BIST is provided on both ABIST and LBIST, and at-speed scan is implemented on internal scan chains. The PU also provides the logic used for programming and testing electronic fuses (eFuses), which are used for array repair and chip customization during the manufacturing test.

The PMU and TMU (not shown in Figure 1.17) work in tandem to manage chip power and avoid permanent damage to the chip because of overheating. For power reduction, the PMU provides a mechanism to allow software controls to reduce chip power when the full processing capabilities are not needed. The PMU also allows the operating system to throttle (by adjusting instruction issue rate), pause, or stop single or multiple elements to manage chip power. The processor embeds a linear sensor (linear diode) to monitor the global chip temperature for controlling external cooling mechanisms. Ten digital thermal sensors are distributed on the chip to monitor temperatures in critical local regions (hot spots). One digital thermal sensor (DTS) is located in each element, and one is adjacent to the linear sensor. The TMU continuously monitors each DTS and can be programmed to dynamically control the temperature of each element and interrupt the PPE when a temperature specified for each element is observed. Software controls the TMU by setting four temperature values and the amount of throttling for each sensor in the TMU. With increasing temperature, the first temperature specifies when the throttling of an element stops, the second when throttling starts, the third when the element is completely stopped, and the fourth when the chip’s clocks are shut down.

In contrast to bus interconnect technology commonly found in SOC designs, NOC-platform-based SOC designs tend to contain two or more processors and a programmable crossbar switch (for dynamic routing) to improve on-chip communication efficiency [Dally 2004] [Jerraya 2004] [McNairy 2005] [Naffziger 2005, 2006] [De Micheli 2006]. The multiprocessor architecture and crossbar switch have represented additional test challenges and spurred eminent DFT needs for at-speed BIST [Wang 2006], silicon debug and diagnosis [Abramovici 2006] [Wang 2006], online self-checking and fault tolerance [Siewiorek 1998], software-based self-testing [Cheng 2006], FPGA testing [Stroud 2002], and high-speed I/O interfaces testing [Gizopoulos 2006].

SOC designs contain a variety of components, including digital, memory, as well as analog and mixed-signal circuits, all of which need to be tested. DFT is essential for reducing test costs and improving test quality.

Scan is widely used for digital logic testing. However, one of the challenges in the nanometer design era is dealing with the rapidly growing amount of scan data required for testing complex SOC designs. The bandwidth between an external ATE and the device under test is limited, creating a bottleneck on how fast the chip can be tested. This has led to the development of test compression and logic BIST architectures, which reduce the amount of data that needs to be transferred between the ATE and device under test. Another key issue for scan testing is applying at-speed tests, which are crucial for detecting delay faults. Chapter 2 reviews the basics of scan testing and presents test compression and logic BIST architectures as well as architectures for applying at-speed tests.

SOC designs contain numerous embedded cores, each of which has a set of tests that need to be applied. This presents challenges in terms of providing test access to the embedded cores and dealing with high test data volumes. Chapter 4 presents DFT architectures that facilitate low-cost modular testing of SOCs. Optimization techniques are described for wrapper designs and test access mechanisms to facilitate efficient test scheduling and reduce test data volume. Network-on-chips (NOCs), which provide a packet-based mechanism for transferring data between cores, are becoming increasingly attractive as nanometer design complexity increases. Chapter 4 discusses DFT architectures for testing NOCs including the interconnect, router, and network interface.

A system-in-package (SIP) is a combination of semiconductors, passives, and interconnect integrated into a single package. The use of SIPs is growing rapidly. A SIP contains multiple dies in the same package that presents additional test issues beyond those of an SOC. The assembly of the SIP needs to be tested, and the SIP may include MEMS and RF components. Chapter 5 provides background on SIPs and discusses the test challenges along with some solutions.

Field programmable gate arrays (FPGAs) are widely used and have grown in complexity to where they are able to implement very large systems. The reprogrammability of FPGAs makes them an attractive choice, not only for rapid prototyping of digital systems but also for low-to-moderate volume or fast time-to-market systems. Testing FPGAs requires loading numerous test configurations, which can be time consuming. Chapter 12 provides background on the architecture and operation of FPGAs and presents approaches for testing FPGAs as well as RAM cores embedded in FPGAs.

High-speed I/O interfaces involve using source-synchronous serial links that can have speeds exceeding 1 Gb/s. These interfaces are often used on digital systems and, for economic reasons, it is necessary to test them using a digital tester. Chapter 14 describes high-speed I/O architectures and techniques for testing them.

Analog ICs and the analog portions of mixed-signal circuits require different test techniques than those applied to digital components. Analog testing involves specification-based approaches as opposed to the fault-model-based and defect-based approaches used for digital testing. Chapter 15 reviews analog testing and then focuses on test architectures that can be used for on-chip testing and measurement of the analog portion(s) of SOC designs.

Nanometer technology is more susceptible to process variations and smaller defects, which often manifest themselves as timing-related problems. Conventional stuck-at fault testing becomes increasingly less effective, and new fault models need to be considered. Moreover, the lower voltage levels and smaller noise margins in nanometer technology make it increasingly susceptible to transient errors, thereby creating new challenges in terms of dealing with soft errors and reliability issues.

Delay faults are prevalent in nanometer technology and must be detected to achieve high quality. Delay faults can arise because of global process variations or local defects. Testing for delay faults typically requires two-pattern tests, which add an additional complication for test application in scan circuits. Chapter 6 describes delay test approaches including new defect-based delay fault models along with simulation and test generation techniques.

Power dissipation is typically much higher during testing than during normal operation because there is much greater switching activity. Excessive average power during testing can result in overheating and hot spots on the chip. Excessive peak power during testing can cause ground bounce and power supply droop, which may cause a good part to fail unnecessarily. Chapter 7 presents techniques for reducing power dissipation during testing, including low-power scan and BIST techniques.

New defect mechanisms are evolving in nanometer technology such as copper-related defects, optical defects, and design-related defects caused by threshold voltage variations and the use of variable power supply voltages in low power designs. Defects do not necessarily manifest themselves as a single isolated problem such as an open or a short. A circuit parameter out of specification can cause increased susceptibility to other problems (temperature effects, crosstalk, etc.). Moreover, the lower voltage levels and smaller noise margins in nanometer technology result in increased susceptibility to radiation-induced soft errors. Chapter 8 describes techniques for coping with the physical failures, soft errors, and reliability issues that arise in nanometer technology.

SOCs typically contain one or more processors. Software running on a processor can be used to perform a self-test of the SOC. This offers a number of advantages including reducing the amount of DFT circuitry required, providing functional at-speed tests, and avoiding the problem of excessive power consumption that arises in structural tests. Chapter 11 describes software-based self-testing techniques that can target the different components of an SOC, including the processor itself, global interconnect, nonprogrammable cores, and analog and mixed-signal (AMS) circuits.

As wireless devices are becoming increasingly prevalent, RF testing has been gaining importance. RF testing has different considerations than conventional analog and mixed-signal testing and requires the use of a different set of instruments to perform the measurements. Noise is a particularly important factor in RF measurements. Chapter 16 provides background on RF devices and RF testing methods. Advanced techniques for testing RF components along with future directions in RF testing are also described.

Nanometer technology is increasingly less robust because of less precise lithography, greater process variations, and greater sensitivity to noise. To cope with these challenges, features must be added to the design to enhance yield and reliability. How to do this in a systematic and effective manner is a topic of great interest and research.

One way to improve reliability is to have a fault-tolerant design that can continue operation in the presence of a fault. Fault tolerance requires the use of redundancy and hence adds area, performance, and power overhead to a design. In the past, fault-tolerant design has mainly been used only for mission-critical applications (medical, aviation, banking, etc.) where the cost of failure is very high. Most low-cost systems have not incorporated much fault tolerance. However, as failure rates continue to rise in nanometer SOC designs, which are increasingly susceptible to noise, it is becoming necessary to incorporate fault tolerance even in mainstream low-cost systems. Chapter 3 reviews the fundamentals of fault-tolerant design and describes many of the commonly used techniques.

Design for manufacturability (DFM) involves making layout design changes to improve any aspect of manufacturability, from mask making through lithography and chemical-mechanical processing. DFM is increasingly important in nanometer technology. Design for yield (DFY) involves techniques that are specifically targeted toward improving yield. Coming up with metrics for yield that could be optimized during design is a major challenge because the manufacturing process is not static; hence the relative importance of different factors impacting yield is constantly changing as process improvements are made. Chapter 9 discusses DFM and DFY, gives examples, and highlights the issues and challenges.

An important step for ramping up yield is to be able to debug and diagnose silicon parts that fail. By identifying the root cause of a failure, it is possible to correct any design bugs that may exist and improve the manufacturing process. Debug and diagnosis can be time consuming. Chapter 10 describes design for debug and diagnosis (DFD) techniques that involve adding features to a design to help speed up the process. These techniques permit engineers to more rapidly obtain information to aid in the process of finding the root cause of a failure.

Although CMOS technology is not predicted to reach fundamental scaling limits for another decade, alternative emerging technologies are being researched in hopes of launching a new era in nanoelectronics. Future nanoelectronic devices are expected to have extremely high defect rates, making test and fault tolerance key factors for obtaining working devices. Another emerging technology is microelectromechanical systems (MEMS) devices, which are miniature electromechanical sensors and actuators fabricated using VLSI processing techniques. Testing MEMS is an interesting topic as MEMS physically interact with the environment, rather than only electrical interfaces like traditional ICs, as illustrated in the bioMEMS sensor example presented in this chapter.

MEMS has many application arenas, including accelerometers, pressure sensors, microoptics, inkjet nozzles, optical scanners, and fluid pumps, and has the potential to be used in many other applications. Chapter 13 describes MEMS devices and discusses the techniques that are used to test and characterize them. In addition, DFT and BIST techniques are presented that have been proposed as well as implemented on commercially available MEMS devices.

Several promising nanoelectronic technologies are emerging, including resonant tunneling diodes (RTDs), quantum-dot cellular automata (QCA), silicon nanowiressingle electron transistors, and carbon nanotubes (CNTs). These are all described in Chapter 17, along with the research work that has begun to develop test techniques for them.