Figure 2.2 shows a sequential circuit example with three D flip-flops. The corresponding muxed-D full-scan circuit is shown in Figure 2.3. An edge-triggered muxed-D scan cell design is shown in Figure 2.3a. This scan cell is composed of a D flip-flop and a multiplexer. The multiplexer uses a scan enable (SE) input to select between the data input (DI) and the scan input (SI.) The three D flip-flops, FF₁, FF₂, and FF₃, as shown in Figure 2.2, are replaced with three muxed-D scan cells, SFF₁, SFF₂, and SFF₃, shown in Figure 2.3b.

Figure 2.2. Sequential circuit example.

Figure 2.3. Muxed-D scan design: (a) muxed-D scan cell and (b) muxed-D scan design.

In Figure 2.3a, the data input DI of each scan cell is connected to the output of the combinational logic as in the original circuit. To form a scan chain, the scan inputs SI of SFF₂ and SFF₃ are connected to the outputs Q of the previous scan cells, SFF₁ and SFF₂, respectively. In addition, the scan input SI of the first scan cell SFF₁ is connected to the primary input SI, and the output Q of the last scan cell SFF₃ is connected to the primary output SO. Hence, in shift mode, SE is set to 1, and the scan cells operate as a single scan chain, which allows us to shift any combination of logic values into the scan cells. In capture mode, SE is set to 0, and the scan cells are used to capture the test response from the combinational logic when a clock is applied.

In general, combinational logic in a full-scan circuit has two types of inputs: primary inputs (PIs) and pseudo primary inputs (PPIs). Primary inputs refer to the external inputs to the circuit, whereas pseudo primary inputs refer to the scan cell outputs. Both PIs and PPIs can be set to any required logic values. The only difference is that PIs are set directly in parallel from the external inputs, whereas PPIs are set serially through scan chain inputs. Similarly, the combinational logic in a full-scan circuit has two types of outputs: primary outputs (POs) and pseudo primary outputs (PPOs). Primary outputs refer to the external outputs of the circuit, and pseudo primary outputs refer to the scan cell inputs. Both POs and PPOs can be observed. The only difference is that POs are observed directly in parallel from the external outputs, and PPOs are observed serially through scan chain outputs.

An edge-triggered clocked-scan cell can also be used to replace a D flip-flop in a scan design [McCluskey 1986]. Similar to a muxed-D scan cell, a clocked-scan cell also has a data input DI and a scan input SI; however, in the clocked-scan cell, input selection is conducted using two independent clocks, data clock DCK and shift clock SCK, as shown in Figure 2.4a.

Figure 2.4. Clocked-scan design: (a) clocked-scan cell and (b) clocked-scan design.

Figure 2.4b shows a clocked-scan design of the sequential circuit given in Figure 2.2. This clocked-scan design is tested using shift and capture operations, similar to a muxed-D scan design. The main difference is how these two operations are distinguished. In a muxed-D scan design, a scan enable signal SE is used, as shown in Figure 2.3a. In the clocked scan shown in Figure 2.4, these two operations are distinguished by properly applying the two independent clocks SCK and DCK during shift mode and capture mode, respectively.

Figure 2.5 shows a polarity-hold shift register latch (SRL) design described in [Eichelberger 1977] that can be used as an LSSD scan cell. This scan cell contains two latches: a master two-port D latch L₁ and a slave D latch L₂. Clocks C, A, and B are used to select between the data input D and the scan input I to drive +L₁ and +L₂.

Figure 2.5. Polarity-hold shift register latch (SRL).

LSSD scan designs can be implemented using either a single-latch design or a double-latch design. In single-latch design [Eichelberger 1977], the output port +L₁ of the master latch L₁ is used to drive the combinational logic of the design. In this case, the slave latch L₂ is used only for scan testing. Because LSSD designs use latches instead of flip-flops, at least two system clocks C₁ and C₂ are required to prevent combinational feedback loops from occurring. In this case, combinational logic driven by the master latches of the first system clock C₁ are used to drive the master latches of the second system clock C₂, and vice versa. For this to work, the system clocks C₁ and C₂ should be applied in a nonoverlapping fashion. Figure 2.6a shows an LSSD single-latch design using the polarity-hold SRL shown in Figure 2.5.

Figure 2.6. LSSD designs: (a) LSSD single-latch design and (b) LSSD double-latch design.

Figure 2.6b shows an example of LSSD double-latch design [DasGupta 1982]. In normal mode, the C₁ and C₂ clocks are used in a nonoverlapping manner, where the C₂ clock is the same as the B clock. The testing of an LSSD scan design is conducted using shift and capture operations, similar to a muxed-D scan design. The main difference is how these two operations are distinguished. In a muxed-D scan design, a scan enable signal SE is used, as shown in Figure 2.3a. In an LSSD scan design, these two operations are distinguished by properly applying nonoverlapping clock pulses to clocks C₁, C₂, A, and B. During the shift operation, clocks A and B are applied in a nonoverlapping manner, and the scan cells SRL₁ ~ SRL₃ form a single scan chain from SI to SO. During the capture operation, clocks C₁ and C₂ are applied in a nonoverlapping manner to load the test response from the combinational logic into the scan cells.

The operation of a polarity-hold SRL is race-free if clocks C and B as well as A and B are nonoverlapping. This characteristic is used to implement LSSD circuits that are guaranteed to have race-free operation in normal mode as well as in test mode.

Testing for a delay fault requires applying a pair of test vectors in an at-speed fashion. This is used to generate a logic value transition at a signal line or at the source of a path, and the circuit response to this transition is captured at the circuit’s operating speed. Applying an arbitrary pair of vectors as opposed to a functionally dependent pair of vectors, generated through the combinational logic of the circuit under test, allows us to maximize the delay fault detection capability. This can be achieved using enhanced scan [Malaiya 1983] [Glover 1988] [Dervisoglu 1991]. The enhanced-scan or hold-scan test circuit was implemented in the 90-nm Intel Pentium 4 processor [Kuppuswamy 2004].

Enhanced scan increases the capacity of a typical scan cell by allowing it to store two bits of data that can be applied consecutively to the combinational logic driven by the scan cells. For a muxed-D scan cell or a clocked-scan cell, this is achieved through the addition of a D latch.

Figure 2.7 shows a general enhanced-scan architecture using muxed-D scan cells. In this figure, in order to apply a pair of test vectors < V₁, V₂ > to the design, the first test vector V₁ is first shifted into the scan cells (SFF₁ ~ SFF_s) and then stored into the additional latches (LA₁ ~ LA_s) when the UPDATE signal is set to 1. Next, the second test vector V₂ is shifted into the scan cells while the UPDATE signal is set to 0 in order to preserve the V₁ value in the latches (LA₁ ~ LA_s). Once the second vector V₂ is shifted in, the UPDATE signal is applied, in order to change V₁ to V₂ while capturing the output response at-speed into the scan cells by applying CK after exactly one clock cycle.

Figure 2.7. Enhanced-scan design.

The main advantage of enhanced scan is that it allows us to achieve high delay fault coverage by applying any arbitrary pair of test vectors, that otherwise would have been impossible. The disadvantages, however, are that each enhanced-scan cell needs an additional scan-hold D latch and that maintaining the timing relationship between UPDATE and CK for at-speed testing may be difficult. An additional disadvantage is that many false paths, instead of functional data paths, may be activated during test, causing an over-test problem. To reduce over-test, the conventional launch-on-shift (also called skewed-load [Savir 1993]) and launch-on-capture (also called broad-side in [Savir 1994] or double-capture in [Wang 2006a]) delay test techniques using normal scan chains can be used.

A simple approach to reducing test power is to reduce the supply voltage. By reducing the supply voltage by 2X, a reduction of 4X in test power can be immediately achieved. The problem with this approach is that the circuit may not be designed to function at the reduced supply voltage.

Another approach is to slow down the shift clock frequency [Chandra 2001]. By reducing the shift clock frequency by 10X, a reduction of 10X in test power can be immediately achieved. The drawback of this approach is that test application time is increased by 10X, as test application time is mainly dominated by shift clock frequency. This can result in a dramatic increase in test cost.

One common approach to reduce test power is to apply shift clocks in a multiphase (nonoverlapping) or multi-duty (skewed) order [Bonhomme 2001] [Saxena 2001] [Yoshida 2003] [Rosinger 2004]. The multi-phase clocking technique splits the shift clock into a number of nonoverlapping clock phases each for driving a small scan segment of scan cells. Thus, test power is reduced, but test application time may be increased. To avoid test application time increase, the scan inputs and the scan outputs of all scan segments can be tied together and multiplexed with the original shift clock, respectively [Bonhomme 2001] [Saxena 2001] [Rosinger 2004]. The low-power scan design described in [Yoshida 2003] uses a multi-duty clocking technique to avoid test application time increase. This is done by adding delays to the shift clock so a skewed clock phase is applied to a small scan segment of scan cells. This technique also helps reduce peak power, but total energy consumption and heat dissipation may not change. A multi-phase or multi-duty low-power scan design reconfigured from Figure 2.3b is shown in Figure 2.8 where the clock CK shown in Figure 2.3b is split (or skewed) into three clock phases: CK₁, CK₂, and CK₃. Using this scheme, up to 3X reduction in test power can be achieved. The disadvantage of this approach is increased routing overhead and complexity during clock tree synthesis (CTS).

Figure 2.8. Multi-phase or multi-duty low-power scan design.

It is also possible to reduce test power by splitting each scan chain into multiple scan chains and reducing the shift clock frequency. This is accomplished by using pairs of serial-in/parallel-out shift register and parallel-in/serial-out shift register for bandwidth matching [Whetsel 1998] [Khoche 2002]. Consider a design with 16 scan chains running at a shift clock frequency of 10 MHz. Each scan chain is split into 10 subscan chains with the SI and SO ports of each 10 subscan chains connected to a serial-in/parallel-out shift register and a parallel-in/serial-out shift register, respectively. In this case, the 16 pairs of shift registers run at 10 MHz, whereas all 160 subscan chains can now be shifted at 1 MHz. As a result, because test power is proportional to the shift clock frequency, a reduction of 10X in test power is achieved, without a corresponding increase in test time. Figure 2.9 shows the bandwidth-matching low-power scan design. The time-division demultiplexer (TDDM) is a serial-in/parallel-out shift register, whereas the time-division multiplexer (TDM) is a parallel-in/serial-out shift register. The main drawback of this approach is the induced area overhead.

Figure 2.9. Bandwidth-matching low-power scan design.

Any of the above-mentioned low-power scan designs can typically achieve 2X to 10X reduction in test power (either shift power or capture power). When combined, further test power reduction is possible. In cases where a 100X reduction in shift power is required, one can consider using random-access scan designs as detailed in Section 2.5 or resort to a hybrid approach that combines two or more low-power test techniques. These advanced techniques are discussed in Chapter 7.

A test-per-scan BIST design was presented in [Bardell 1982]. This design, shown in Figure 2.16, contains a PRPG (parallel shift register sequence generator [SRSG]) and a MISR. The scan chains are loaded in parallel from the PRPG. The system clocks are then triggered and the test responses are shifted to the MISR for compaction. New test patterns are shifted in at the same time while test responses are being shifted out. This BIST architecture using the test-per-scan BIST scheme is referred to as self-testing using MISR and parallel SRSG (STUMPS) [Bardell 1982].

Figure 2.16. STUMPS.

Because of the ease of integration with traditional scan architecture, the STUMPS architecture is the only BIST architecture widely used in industry to date. To further reduce the lengths of the PRPG and MISR and improve the randomness of the PRPG, a STUMPS-based architecture that includes an optional linear phase shifter and an optional linear phase compactor is often used in industrial applications [Nadeau-Dostie 2000] [Cheon 2005]. The linear phase shifter and linear phase compactor typically comprise a network of XOR gates. Figure 2.17 shows the STUMPS-based architecture.

Figure 2.17. A STUMPS-based architecture.

STUMPS is the widely adopted logic BIST architecture for scan-based designs. The acceptance of this STUMPS architecture is mostly because of the ease with which the BIST circuitry is integrated into a scan design. The efforts required to implement the BIST circuitry and the loss of the fault coverage for using pseudo-random patterns, however, have prevented the STUMPS-based logic BIST architecture from being widely used across all industries.

One solution to solve the fault coverage loss problem is to use the concurrent bulit-in logic block observer (CBILBO) approach [Wang 1986]. The CBILBO is based on the test-per-clock BIST scheme and uses two registers to perform test generation and signature analysis simultaneously. A CBILBO design is shown in Figure 2.18, where only three modes of operation are considered: normal, scan, and test generation and signature analysis. When B₁ = 0 and B₂ = 1, the upper D flip-flops act as a MISR for signature analysis, whereas the lower two-port D flip-flops form a TPG for test generation. Because signature analysis is separated from test generation, an exhaustive or pseudo-exhaustive pattern generator (EPG/PEPG) can now be used for test generation; therefore, no fault simulation is required, and it is possible to achieve 100% single-stuck fault coverage using the CBILBO architectures for testing designs shown in Figure 2.19. However, the hardware cost associated with using the CBILBO approach is generally higher than for the STUMPS approach.

Figure 2.18. A three-stage concurrent BILBO (CBILBO).

Figure 2.19. CBILBO architectures: (a) for testing a finite-state machine and (b) for testing a pipelined-oriented circuit.

Typically, weighted pseudo-random patterns are used to increase the circuit’s fault coverage. A weighted pattern generation technique employing an LFSR and a combinational circuit was first described in [Schnurmann 1975]. The combinational circuit inserted between the output of the LFSR and the CUT is to increase the frequency of occurrence of one logic value while decreasing the other logic value. This approach may increase the probability of detecting those faults that are difficult to detect using the typical LFSR pattern generation technique.

Implementation methods for realizing this scheme are further discussed in [Chin 1984]. The weighted pattern generation technique described in that paper modifies the maximum-length LFSR to produce an equally weighted distribution of 0’s and 1’s at the input of the CUT. It skews the LFSR probability distribution of 0.5 to either 0.25 or 0.75 to increase the chance of detecting those faults that are difficult to detect using just a 0.5 distribution. Better fault coverage was also found in [Wunderlich 1987], where probability distributions in a multiple of 0.125 (rather than 0.25) are used. For some circuits, several programmable probabilities or weight sets are required to further increase each circuit’s fault coverage [Waicukauski 1989] [Bershteyn 1993] [Kapur 1994] [Lai 2005]. Additional discussions on weighted pattern generation can be found in [Rajski 1998a] and [Bushnell 2000]. Figure 2.20 shows a four-stage weighted (maximum-length) LFSR with probability distribution 0.75 [Chin 1984].

Figure 2.20. Example weighted LFSR as PRPG.

Although weighted pattern generation is simple in design, achieving adequate fault coverage for a BIST circuit remains a problem. Test points can then be used to increase the circuit’s fault coverage to a desired level. Figure 2.21 shows two typical types of test points that can be inserted. A control point can be connected to a primary input, an existing scan cell output, or a dedicated scan cell output. An observation point can be connected to a primary output through an additional multiplexer, an existing scan cell input, or a dedicated scan cell input.

Figure 2.21. Typical test points inserted for improving a circuit’s fault coverage: (a) test point with a multiplexer and (b) test point with AND-OR gates.

Figure 2.22b shows an example where one control point and one observation point are inserted to increase the detection probability of a 6-input AND-gate given in Figure 2.22a. By splitting the six-input AND gate into two fewer-input AND gates and placing a control point and an observation point between the two fewer-input AND gates, we can increase the probability of detecting faults in the original six-input AND gate, (e.g., output Y stuck-at-0 and any input X_i stuck-at-1), thereby making the circuit more RP testable. After the test points are inserted, the most difficult fault to detect is the bottom input of the four-input AND gate stuck-at-1. In that case, one of inputs X₁, X₂, and X₃ must be 0, the control point must be 0, and all inputs X₄, X₅, and X₆ must be 1, resulting in a detection probability of 7/128 (= 7/8 × 1/2 × 1/2 × 1/2 × 1/2).

Figure 2.22. Example of inserting test points to improve detection probability: (a) an output RP-resistant stuck-at-0 fault and (b) example of inserted test points.

A major drawback of test point insertion is that it requires modifying the circuit under test. In some cases this is not possible or not desirable (e.g., for hard cores, macros, hand-crafted designs, or legacy designs). An alternative way to improve fault coverage without modifying the CUT is to use mixed-mode BIST. Pseudo-random patterns are generated to detect the RP-testable faults, and then some additional deterministic patterns are generated to detect the RP-resistant faults. There are a number of ways for generating deterministic patterns on-chip. Three approaches are described next.

LFSR Reseeding

Instead of storing the test patterns themselves in a ROM, techniques have been developed for storing LFSR seeds that can be used to generate the test patterns [Könemann 1991]. The LFSR that is used for generating the pseudo-random patterns is also used for generating the deterministic patterns by reseeding it with computed seeds. The seeds can be computed with linear algebra as described in [Könemann 1991]. Because the seeds are smaller than the test patterns themselves, they require less ROM storage. One problem is that for an LFSR with a fixed characteristic (feedback) polynomial, it may not always be possible to find a seed that will efficiently generate the required deterministic test patterns. A solution to this problem was proposed in [Hellebrand 1995a] in which a multiple-polynomial LFSR (MP-LFSR), as illustrated in Figure 2.23, is used. An MP-LFSR is an LFSR with a reconfigurable feedback network. A polynomial identifier is stored with each seed to select the characteristic polynomial that will be used for that seed. Techniques for further reductions in storage can be achieved by using variable-length seeds [Rajski 1998b], a special ATPG algorithm [Hellebrand 1995b], folding counters [Liang 2001], and seed encoding [Al-Yamani 2005].

Figure 2.23. Reseeding with multiple-polynomial LFSR.

Embedding Deterministic Patterns

A third approach for mixed-mode BIST is to embed the deterministic patterns in the pseudo-random sequence. Many of the pseudo-random patterns generated during pseudo-random testing do not detect any new faults, so some of those “useless” patterns can be transformed into deterministic patterns that detect RP-resistant faults [Touba 1995]. This can be done by adding mapping logic between the scan chains and the CUT [Touba 1995] or in a less intrusive way by adding the mapping logic at the inputs to the scan chains to either perform bit-fixing [Touba 2001] or bit-flipping [Kiefer 1998]. Figure 2.24 shows a bit-flipping BIST scheme taken from [Kiefer 1998]. A bit-flipping function detects these “useless” patterns and maps them to deterministic patterns through the use of an XOR gate that is inserted between the LFSR and each scan chain.

Figure 2.24. Bit-flipping BIST.

For manufacturing fault coverage enhancement where a tester is present, deterministic data from the tester can be used to improve the fault coverage. The simplest approach is to perform top-up ATPG for the faults not detected by BIST to obtain a set of deterministic test patterns that “top-up” the fault coverage to the desired level and then store those patterns directly on the tester. In a system-on-chip, test scheduling can be done to overlap the BIST run time with the transfer time for loading the deterministic patterns from the tester [Sugihara 1998] [Jervan 2003]. More elaborate hybrid BIST schemes have been developed, which attempt to store the deterministic patterns on the tester in a compressed form and then make use of the existing BIST hardware to decompress them. Such techniques are described in [Das 2000], [Dorsch 2001], [Ichino 2001], [Krishna 2003a], [Wohl 2003a], [Jas 2004], and [Lei 2005]. More discussions on test compression can be found in the following section.

One simple approach is to design a low-transition PRPG that generates test patterns with low switching activity. [Wang 1999] belongs to this category. The low-transition random test pattern generator (LT-RTPG) described in [Wang 1999] and used as a PRPG that is shown in Figure 2.25 inserts an AND gate and a toggle (T) flip-flop at the scan input of the scan chain. The inputs of the AND gate are connected to a few outputs of the LFSR. If the output of the AND gate in the LT-RTPG is 0 for k cycles, then identical values are applied at the scan input for k clock cycles. Hence, the switching activity is reduced. This approach is less design-intrusive and entails no performance degradation. It also requires low hardware overhead. The drawback of this approach is low fault coverage or long test sequence when required to achieve adequate fault coverage.

Figure 2.25. Low-transition random test pattern generator (LT-RTPG) as PRPG.

Another approach is to inhibit the LFSR-generated pseudo-random patterns, which do not contribute to fault detection from being applied to the circuit under test (CUT). This test-vector-inhibiting technique can reduce test power while achieving the same fault coverage as the original LFSR. [Manich 2000] belongs to this category. A test-vector-inhibiting RTPG (TVI-RTPG) is shown in Figure 2.26 for use as a PRPG. When a pseudo-random pattern generated by the PRPG does not detect any faults, the pattern is not transmitted to the CUT. For this purpose, a decoding logic is connected to the output of the LFSR and outputs a 0 to inhibit the pseudo-random pattern from passing through the transmission gate network to the CUT. A transmission gate can be an XOR gate. Whereas this approach targets test-per-clock BIST, it is applicable for test-per-scan BIST designs. The drawback of this approach is high area overhead and impact on circuit performance.

Figure 2.26. Test-vector-inhibiting RTPG (TVI-RTPG) as PRPG.

The third approach is to use a modified LFSR structure, composed of two separated or interleaved n/2-stage LFSRs, to drive the circuit under test (CUT). The two n/2-stage LFSRs would activate only one part of the CUT in a given time interval. [Girard 2001] belongs to this category. It was demonstrated in the paper that shorter test length to reach target fault coverage can be achieved with the proposed modified LFSR structure as shown in Figure 2.27. A test clock module is used to generate the two nonoverlapping clocks, CK₁ and CK₂, for driving LFSR-1 and LFSR-2, respectively. Because only one part of the CUT is activated at any given time, this BIST scheme provides high percentage of power (and energy) reduction and results in no performance degradation and test time increase. The drawback of this approach is the requirement of constructing special clock trees.

Figure 2.27. Two n/2-stage LFSRs as PRPG.

Single-capture is a slow-speed test technique in which only one capture pulse is applied to each clock domain. It is the simplest for testing all intra-clock-domain and inter-clock-domain structural faults. Two approaches can be used: (1) one-hot single-capture and (2) staggered single-capture.

One-Hot Single-Capture

Using the one-hot single-capture approach, a capture pulse is applied to only one clock domain during each capture window, while all other test clocks are held inactive. A sample timing diagram is shown in Figure 2.28. In the figure, because only one capture pulse (C1 or C2) is applied during each capture window, this scheme can only test intra-clock-domain and inter-clock-domain structural faults. The main advantage of this approach is that the designer does not have to worry about clock skews between the two clock domains during self-test, as each clock domain is tested independently. The only requirement is that delays d1 and d2 be properly adjusted; hence, this approach can be used for slow-speed testing of both synchronous and asynchronous clock domains. Another benefit of using this approach is that a single, slow-speed global scan enable (GSE) signal can be used for driving both clock domains, which makes it easy to integrate with scan. A major drawback is longer test time, as all clock domains have to be tested one at a time.

Figure 2.28. One-hot single-capture.

Staggered Single-Capture

The long test time problem using one-hot single-capture can be solved using the staggered single-capture approach [Wang 2006b]. A sample timing diagram is shown in Figure 2.29. In this approach, capture pulses C1 and C2 are applied in a sequential or staggered order during the capture window to test all intra-clock-domain and inter-clock-domain structural faults in the two clock domains. For clock domains that are synchronous, adjusting d2 will allow us to detect inter-clock-domain delay faults between the two clock domains at-speed. In addition, because d1 and d3 can be as long as desired, a single, slow-speed GSE signal can be used. This significantly simplifies the logic BIST physical implementation for designs with multiple clock domains. There may be some structural fault coverage loss between clock domains if the ordered sequence of capture clocks is fixed for all capture cycles.

Figure 2.29. Staggered single-capture.

Skewed-load is an at-speed delay test technique in which a last shift pulse followed immediately by a capture pulse, running at the test clock’s operating frequency, are used to launch the transition and capture the output response [Savir 1993]. It is also referred to as launch-on-shift. This technique addresses the intra-clock-domain delay fault detection problem, which cannot be tested using single-capture schemes. Skewed-load uses the value difference between the last shift pulse and the next-to-last-shift pulse to launch the transition and uses the capture pulse to capture the output response. For the last shift pulse to launch the transition, the scan enable signal associated with the clock domain must be able to switch operations from shift to capture in one clock cycle. Three approaches can be used: (1) one-hot skewed-load, (2) aligned skewed-load, and (3) staggered skewed-load.

One-Hot Skewed-Load

Similar to one-hot single-capture, the one-hot skewed-load approach tests all clock domains one by one [Bhawmik 1997]. A sample timing diagram is shown in Figure 2.30. The main differences are (1) it applies shift-followed-by-capture pulses (S1-followed-by-C1 or S2-followed-by-C2) to detect intra-clock-domain delay faults, and (2) each scan enable signal (SE₁ or SE₂) must switch operations from shift to capture within one clock cycle (d1 or d2). Thus, this approach can only be used for at-speed testing of intra-clock-domain delay faults in both synchronous and asynchronous clock domains. The disadvantages are (1) it cannot be used to detect inter-clock-domain delay faults, (2) it has a long test time, and (3) it is incompatible with scan, as a single, slow-speed GSE signal can no longer be used.

Figure 2.30. One-hot skewed-load.

Aligned Skewed-Load

The disadvantages of one-hot skewed-load can be resolved by using the aligned skewed-load scheme. One aligned skewed-load approach that aligns all capture edges together is illustrated in Figure 2.31 [Nadeau-Dostie 1994] [Nadeau-Dostie 2000]. The approach is referred to as capture aligned skewed-load. The major advantage of using this approach is that all intra-clock-domain and inter-clock-domain faults can be tested. The arrows shown in Figure 2.31 indicate the delay faults that can be tested. For example, the three arrows from S1 (CK₁) to C are used to test all intra-clock-domain delay faults in the clock domain controlled by CK₁, and all inter-clock-domain delay faults from CK₁ to CK₂ and CK₃. The remaining six arrows shown from S2 (CK₂) to C, and S3 (CK₃) to C are used to test all the remaining delay faults.

Figure 2.31. Capture aligned skewed-load.

Because the active edges (rising edges) of the three capture pulses (see dash line C) must be aligned precisely, the circuit must contain one reference clock, and the frequency of all remaining test clocks must be derived from the reference clock. In the example given here, CK₁ is the reference clock operating at the highest frequency, and CK₂ and CK₃ are derived from CK₁ and designed to operate at 1/2 and 1/4 the frequency, respectively; therefore, this approach is only applicable for at-speed testing of intra-clock-domain and inter-clock-domain delay faults in synchronous clock domains.

A similar aligned skewed-load approach that aligns all last shift edges, rather than capture edges, is shown in Figure 2.32 [Hetherington 1999] [Rajski 2003]. This approach is referred to as launch aligned skewed-load. Similar to capture aligned skewed-load, it is also only applicable for at-speed testing of intra-clock-domain and inter-clock-domain delay faults in synchronous clock domains.

Figure 2.32. Launch aligned skewed-load.

Consider the three clock domains, driven by CK₁, CK₂, and CK₃, again. The eight arrows among the dash line S and the three capture pulses (C1, C2, and C3) indicate the intra-clock-domain and inter-clock-domain delay faults that can be tested. Unlike in Figure 2.31, however, to test the inter-clock-domain delay faults from CK₁ to CK₃, a special shift pulse S1 (when SE₁ is set to 1) is required. As this method requires a much more complex timing-control diagram, a clock suppression circuit is used to enable or disable selected shift or capture pulses [Rajski 2003]. The dotted clock pulses shown in the figure indicate the suppressed shift pulses.

Staggered Skewed-Load

Although the aligned skewed-load approaches can test all intra-clock-domain and inter-clock-domain faults in synchronous clock domains, their physical implementation is extremely difficult. There are two main reasons. First, to effectively align all active edges in either capture or last shift, the circuit must contain a reference clock. This reference clock must operate at the fastest clock frequency, and all other clock frequencies must be derived from the reference clock; such designs rarely exist. (2) For any two edges that cannot be aligned precisely because of clock skews, we must either resort to a one-hot skewed-load approach or add capture-disabling circuitry on the functional data paths of the two clock domains to prevent the cross-domain logic from interacting with each other during capture. This increases the circuit overhead, degrades the functional circuit performance, and reduces the ability to test inter-clock-domain faults.

The staggered skewed-load approach shown in Figure 2.33 relaxes these conditions [Wang 2005b]. For test clocks that cannot be precisely aligned, a delay d3 is inserted, to eliminate the clock skew interaction between the two clock domains. The two last shift pulses (S1 and S2) are used to create transitions at the outputs of some scan cells, and the output responses to these transitions are captured by the following two capture pulses (C1 and C2), respectively. Both delays d1 and d2 are set to their respective clock domains’ operating frequencies; hence, this scheme can be used to test all intra-clock-domain faults and inter-clock-domain structural faults in asynchronous clock domains. A problem still exists, as each clock domain requires an at-speed scan enable signal, which complicates physical implementation.

Figure 2.33. Staggered skewed-load.

The physical implementation difficulty using skewed-load can be resolved by using the double-capture scheme. Double-capture is another at-speed test technique in which two consecutive capture pulses are applied to launch the transition and capture the output response. It is also referred to as broad-side [Savir 1994] or launch-on-capture. The double-capture scheme can achieve true at-speed test quality for intra-clock-domain and inter-clock-domain faults in any synchronous or asynchronous design and it is easy for physical implementation. Here, true at-speed testing is meant to (1) allow detection of intra-clock-domain faults within each clock domain at its own operating frequency and detection of inter-clock-domain structural faults or delay faults, depending on whether the circuit under test is synchronous, asynchronous, or a mix of both, and (2) ease physical implementation for seamless integration with the conventional scan/ATPG technique.

One-Hot Double-Capture

Similar to one-hot skewed-load, the one-hot double-capture approach tests all clock domains one by one. A sample timing diagram is shown in Figure 2.34. The main differences are (1) two consecutive capture pulses are applied (C1-followed-by-C2 or C3-followed-by-C4) at their respective clock domains’ frequencies (of period d1 or d2) to test intra-clock-domain delay faults, and (2) a single, slow-speed GSE signal is used to drive both clock domains. Hence, this scheme can be used for true at-speed testing of intra-clock-domain delay faults in both synchronous and asynchronous clock domains. Two drawbacks remain: (1) it cannot be used to detect inter-clock-domain delay faults, and (2) it has a long test time.

Figure 2.34. One-hot double-capture.

Aligned Double-Capture

The drawbacks of the one-hot double-capture scheme can be resolved by using an aligned double-capture approach. Similar to the aligned skewed-load approach, the aligned double-capture scheme allows all intra-clock-domain faults and inter-clock-domain faults to be tested [Wang 2006b]. The main differences are (1) two consecutive capture pulses are applied, rather than shift-followed-by-capture pulses, and (2) a single, slow speed GSE signal is used. Figures 2.35 and 2.36 show two sample timing diagrams. This scheme can be used for true at-speed testing of synchronous clock domains. One major drawback is that precise alignment of the capture pulses is still required. This complicates physical implementation for designs with asynchronous clock domains.

Figure 2.35. Capture aligned double-capture.

Figure 2.36. Launch aligned double-capture.

Staggered Double-Capture

The capture alignment problem in the aligned double-capture approach can finally be relaxed by using the staggered double-capture scheme [Wang 2005a, 2006b]. A sample timing diagram is shown in Figure 2.37. During the capture window, two capture pulses are generated for each clock domain. The first two capture pulses (C1 and C3) are used to create transitions at the outputs of some scan cells, and the output responses to the transitions are captured by the second two capture pulses (C2 and C4), respectively. Both delays d2 and d4 are set to their respective domains’ operating frequencies. Because d1, d3, and d5 can be adjusted to any length, we can simply use a single, slow-speed GSE signal for driving all clock domains; hence, true at-speed testing is guaranteed using this approach for asynchronous clock domains. Because a single GSE signal is used, this scheme significantly eases physical implementation and allows us to integrate logic BIST with scan/ATPG easily to improve the circuit’s manufacturing fault coverage.

Figure 2.37. Staggered double-capture.

A class of test stimulus compression schemes is based on using linear decompressors to expand the data coming from the tester to fill the scan chains. Any decompressor that consists of only XOR gates and flip-flops is a linear decompressor [Könemann 1991]. Linear decompressors have a very useful property: their output space (i.e., the space of all possible test vectors that they can generate) is a linear subspace that is spanned by a Boolean matrix. In other words, for any linear decompressor that expands an m-bit compressed stimulus from the tester into an n-bit stimulus (test vector), there exists a Boolean matrix A_nxm such that the set of test vectors that can be generated by the linear decompressor is spanned by A. A test vector Z can be compressed by a particular linear decompressor if and only if there exists a solution to a system of linear equations, AX = Z, where A is the characteristic matrix of the linear decompressor and X is a set of free variables stored on the tester (every bit stored on the tester can be thought of as a “free variable” that can be assigned any value, 0 or 1).

The characteristic matrix for a linear decompressor can be obtained by symbolic simulation where each free variable coming from the tester is represented by a symbol. An example is shown in Figure 2.39, where a sequential linear decompressor containing an LFSR is used. The initial state of the LFSR is represented by free variables X₁ – X₄, and the free variables X₅ – X₁₀ are shifted in from two channels as the scan chains are loaded. After symbolic simulation, the final values in the scan chains are represented by the equations for Z₁ – Z₁₂. The corresponding system of linear equations for this linear decompressor is shown in Figure 2.40.

Figure 2.39. Example of symbolic simulation for linear decompressor.

Figure 2.40. System of linear equations for the decompressor in Figure 2.39.

The symbolic simulation goes as follows. Assume that the initial seed X₁ – X₄ has been already loaded into the flip-flops. In the first clock cycle, the top flip-flop is loaded with the XOR of X₂ and X₅, the second flip-flop is loaded with X₃), the third flip-flop is loaded with the XOR of X₁ and X₄, and the bottom flip-flop is loaded with the XOR of X₁ and X₆. Thus, we obtain Z₁ = X₂ ⊕ X₅, Z₂ = X₃, Z₃ = X₁ ⊕ X₄, and Z₄= X₁ ⊕ X₆. In the second clock cycle, the top flip-flop is loaded with the XOR of the contents of the second flip-flop (X₃) and X₇, the second flip-flop is loaded with the contents of the third flip-flop (X₁ ⊕ X₄), the third flip-flop is loaded with the XOR of the contents of the first flip-flop (X₂ ⊕ X₅) and the fourth flip-flop (X₁ ⊕ X₆), and the bottom flip-flop is loaded with the XOR of the contents of the first flip-flop (X₂ ⊕ X₅) and X₈. Thus, we obtain Z₅ = X₃ ⊕ X₇, Z₆ = X₁ ⊕ X₄, Z₇ = X₁ ⊕ X₂ ⊕ X₅ ⊕ X₆, and Z₈ = X₂ ⊕ X₅ ⊕ X₈. In the third clock cycle, the top flip-flop is loaded with the XOR of the contents of the second flip-flop (X₁ ⊕ X₄) and X₉, the second flip-flop is loaded with the contents of the third flip-flop (X₁ ⊕ X₂ ⊕ X₅ ⊕ X₆); the third flip-flop is loaded with the XOR of the contents of the first flip-flop (X₃ ⊕ X₇) and the fourth flip-flop (X₂ ⊕ X₅ ⊕ X₈), and the bottom flip-flop is loaded with the XOR of the contents of the first flip-flop (X₃ ⊕ X₇) and X₁₀. Thus, we obtain Z₉ = X₄ ⊕ X₉, Z₁₀= X₁ ⊕ X₆, Z₁₁ = X₂ ⊕ X₅ ⊕ X₈, and Z₁₂ = X₃ ⊕ X₇ ⊕ X₁₀. At this point, the scan chains are fully loaded with a test cube, so the simulation is complete.

Sequential Linear Decompressors

Sequential linear decompressors are based on linear finite-state machines such as LFSRs, cellular automata, or ring generators [Mrugalski 2004]. The advantage of a sequential linear decompressor is that it allows free variables from earlier clock cycles to be used when encoding a scan slice in the current clock cycle. This provides greater flexibility than combinational decompressors and helps avoid the problem of the worst-case most highly specified scan slices limiting the overall compression. The more flip-flops that are used in the sequential linear decompressor, the greater the flexibility that is provided. [Tobua 2006] classified the sequential linear decompressors into two classes:

1. Static reseeding. The earliest work in this area was based on static LFSR reseeding, a technique that computes a seed (an initial state) for each test cube [Touba 2006]. This seed, when loaded into an LFSR and run in autonomous mode, produces the test cube in the scan chains [Könemann 1991]. This technique achieves compression by storing only the seeds instead of the full test cubes.

   One drawback of using static reseeding for compressing test vectors on a tester is that the tester is idle while the LFSR is running in autonomous mode. One way around this is to use a shadow register for the LFSR to hold the data coming from the tester while the LFSR is running in autonomous mode [Volkerink 2003] [Wohl 2003b].

   Another drawback of static reseeding is that the LFSR must be at least as large as the number of specified bits in the test cube. One way around this is to only decompress a scan window (a limited number of scan slices) per seed [Krishna 2002] [Volkerink 2003] [Wohl 2005].

2. Dynamic reseeding. [Könemann 2001], [Krishna 2001], and [Rajski 2004] proposed dynamic reseeding approaches. Dynamic reseeding calls for the injection of free variables coming from the tester into the LFSR as it loads the scan chains [Touba 2006]. Figure 2.41 shows a generic example of a sequential linear decompressor that uses b channels from the tester to continuously inject free variables into the LFSR as it loads the scan chains through a combinational linear decompressor, which typically is a combinational XOR network. This network expands the LFSR outputs to fill n scan chains. The advantages of dynamic reseeding compared with static reseeding are that it allows continuous flow operation in which the tester is always shifting in data as fast as it can and is never idle, and it allows the use of a small LFSR.

Figure 2.41. Typical sequential linear decompressor.

In [Rajski 2004], the authors described a methodology for scan vector compression based on a sequential linear decompressor. Instead of using an LFSR, this work uses a ring generator [Mrugalski 2004], which improves encoding flexibility and provides performance advantages. A fixed number of free variables are shifted in when decompressing each test cube. In this case, the control logic is simple because this methodology decompresses every test cube in exactly the same way. Constraining the ATPG generates test cubes that are encodable using the fixed number of free variables.

In [Könemann 2001], the authors described a methodology for scan vector compression in which the number of free variables used to encode each test cube varies. The method requires having an extra channel from the tester to gate the scan clock. For a heavily specified scan slice, this extra gating channel stops the scan shifting for one or more cycles, allowing the LFSR to accumulate a sufficient number of free variables from the tester to solve for the current scan slice before proceeding to the next one. This approach makes it easy to control the number of free variables that the decompressor uses to decompress each test cube. However, the additional gating channel uses some test data bandwidth.

Another class of test stimulus compression schemes is based on broadcasting the same value to multiple scan chains. This was first proposed in [Lee 1998] and [Lee 1999]. Because of its simplicity and effectiveness, this method has been used as the basis of many test compression architectures, including some commercial design for testability (DFT) tools.

Broadcast Scan

To illustrate the basic concept of broadcast scan, first consider two independent circuits C₁ and C₂. Assume that these two circuits have their own test sets T₁ = < t₁₁, t₁₂,..., t_1k > and T₂ = < t₂₁, t₂₂,..., t_2l >, respectively. In general, a test set may consist of random patterns and deterministic patterns. In the beginning of the ATPG process, usually random patterns are initially used to detect the easy-to-detect faults. If the same random patterns are used when generating both T₁ and T₂ then we may have t₁₁ = t₂₁, t₁₂ = t₂₂,..., up to some ith pattern. After most faults have been detected by the random patterns, deterministic patterns are generated for the remaining difficult-to-detect faults. Generally these patterns have many “don’t care” bits. For example, when generating t_1(i+1), many don’t care bits may still exist when no more faults in C₁ can be detected. Using a test pattern with bits assigned so far for C₁, we can further assign specific values to the don’t care bits in the pattern to detect faults in C₂. Thus, the final pattern would be effective in detecting faults in both C₁ and C₂.

The concept of pattern sharing can be extended to multiple circuits as illustrated in Figure 2.42. One major advantage of using broadcast scan for independent circuits is that all faults that are detectable in all original circuits will also be detectable with the broadcast structure. This is because if one test vector can detect a fault in a stand-alone circuit then it will still be possible to apply this vector to detect the fault in the broadcast structure. Thus, the broadcast scan method will not affect the fault coverage if all circuits are independent. Note that broadcast scan can also be applied to multiple scan chains of a single circuit if all subcircuits driven by the scan chains are independent.

Figure 2.42. Broadcasting to scan chains driving independent circuits.

Illinois Scan

If broadcast scan is used for multiple scan chains of a single circuit where the subcircuits driven by the scan chains are not independent, then the property of always being able to detect all faults is lost. The reason for this is that if two scan chains are sharing the same channel, then the ith scan cell in each of the two scan chains will always be loaded with identical values. If some fault requires two such scan cells to have opposite values in order to be detected, it will not be possible to detect this fault with broadcast scan.

To address the problem of some faults not being detected when using broadcast scan for multiple scan chains of a single circuit, the Illinois scan architecture was proposed in [Hamzaoglu 1999] and [Hsu 2001]. This scan architecture consists of two modes of operations, namely a broadcast mode and a serial scan mode, which are illustrated in Figure 2.43. The broadcast mode is first used to detect most faults in the circuit. During this mode, a scan chain is divided into multiple subchains called segments and the same vector can be shifted into all segments through a single shared scan-in input. The response data from all subchains are then compacted by a MISR or other space/time compactor. For the remaining faults that cannot be detected in broadcast mode, the serial scan mode is used where any possible test pattern can be applied. This ensures that complete fault coverage can be achieved. The extra logic required to implement the Illinois scan architecture consists of several multiplexers and some simple control logic to switch between the two modes. The area overhead of this logic is typically quite small compared to the overall chip area.

Figure 2.43. Two modes of Illinois scan architecture: (a) broadcast mode and (b) serial chain mode.

The main drawback of the Illinois scan architecture is that no test compression is achieved when it is run in serial scan mode. This can significantly degrade the overall compression ratio if many test patterns must be applied in serial scan mode. To reduce the number of patterns that need to be applied in serial scan mode, multiple-input broadcast scan or reconfigurable broadcast scan can be used. These techniques are described next.

Reconfigurable Broadcast Scan

The multiple-input broadcast scan may require a large number of channels to achieve high fault coverage. To reduce the number of channels that are required, a reconfigurable broadcast scan method can be used. The idea is to provide the capability to reconfigure the set of scan chains that each channel drives. Two possible reconfiguration schemes have been proposed, namely static reconfiguration [Pandey 2002] [Samaranayake 2003] and dynamic reconfiguration [Li 2004] [Sitchinava 2004] [Wang 2004] [Han 2005c]. In static reconfiguration, the reconfiguration can only be done when a new pattern is to be applied. For this method, the target fault set can be divided into several subsets, and each subset can be tested by a single configuration. After testing one subset of faults, the configuration can be changed to test another subset of faults. In dynamic reconfiguration, the configuration can be changed while scanning in a pattern. This provides more reconfiguration flexibility and hence can in general lead to better results with fewer channels. This is especially important for hard cores when the test patterns provided by core vendor cannot be regenerated. The drawback of dynamic reconfiguration versus static reconfiguration is that more control information is needed for reconfiguring at the right time, whereas for static reconfiguration the control information is much less because the reconfiguration is done only a few times (only after all the test patterns using a particular configuration have been applied).

Figure 2.44 shows an example multiplexer (MUX) network, which can be used for dynamic configuration. When a value on the control line is selected, particular data at the four input pins are broadcasted to the eight scan chain inputs. For instance, when the control line is set to 0 (or 1), the scan chain 1 output will receive input data from pin 4 (or pin 1) directly.

Figure 2.44. Example MUX network with control line(s) connected only to select pins of the multiplexers.

Virtual Scan

Rather than using MUX networks for test stimulus compression, combinational logic networks can also be used as decompressors. The combinational logic network can consist of any combination of simple combinational gates, such as buffers, inverters, AND/OR gates, MUXs, and XOR gates. This scheme, referred to as virtual scan, is different from reconfigurable broadcast scan and combinational linear decompression where pure MUX and XOR networks are allowed, respectively. The combinational logic network can be specified as a set of constraints or just as an expanded circuit for ATPG. In either case, the test cubes that ATPG generates are the compressed stimuli for the decompressor itself. There is no need to solve linear equations, and dynamic compaction can be effectively utilized during the ATPG process.

The virtual scan scheme was proposed in [Wang 2002] and [Wang 2004]. In these papers, the decompressor was referred to as a broadcaster. The authors also proposed to add additional logic, when required, through VirtualScan inputs to reduce or remove the constraints imposed on the decompressor (broadcaster), thereby yielding little or no fault coverage loss caused by test stimulus compression.

In a broad sense, virtual scan is a generalized class of broadcast scan, Illinois scan, multiple-input broadcast scan, reconfigurable broadcast scan, and combinational linear decompression. The advantage of using virtual scan is that it allows the ATPG to directly search for a test cube that can be applied by the decompressor and allows very effective dynamic compaction. Thus, virtual scan may produce shorter test sets than any test stimulus compression scheme based on solving linear equations; however, because this scheme may impose XOR or MUX constraints directly on the original circuit, it may take more time than schemes based on solving linear equations to generate test cubes or compressed stimuli. Two examples of virtual scan decompression circuits are shown in Figure 2.45.

Figure 2.45. Example virtual scan decompression circuits: (a) broadcaster using an example XOR network with additional VirtualScan inputs to reduce coverage loss and (b) broadcaster using an example MUX network with additional VirtualScan inputs that can be also connected to data pins of the multiplexers.

In this section, we compare the encoding flexibility for different types of combinational decompression techniques: Illinois scan using a pure buffer network, reconfigurable broadcast scan using MUX networks, and linear combinational decompression using only one-level 2-input XOR gates or one-level, three-input XOR gates [Dutta 2006].

Consider the bits coming from the tester each clock cycle as a tester slice. Then the tester slice gets expanded every clock cycle to fill the scan slice, which equals the number of scan chains. The authors in [Dutta 2006] did some experiments to measure the encoding flexibility of different ways of expanding the tester slices into scan slices. Figure 2.46 shows the percentage of all possible scan slices with different number of specified bits that can be encoded in each case for expanding a 16-bit tester slice to a 160-bit scan slice with an expansion ratio (or split ratio) of 10. The x-axis is the number of specified bits in the scan slice, and the y-axis is the percentage of all possible combinations of that number of specified bits that can be encoded. As the graph shows, all the decompression networks can always encode one specified bit. However, as the number of specified bits increases, the probability of being able to encode the scan slice drops. Because Illinois scan has the least encoding flexibility, it has the lowest probability of being able to encode a scan slice. The results for using MUXs are shown for two cases. One is where the control and data lines are separated (i.e., one of the tester channels is dedicated to driving the select line and the other 15 tester channels are used to drive the data lines). The other is where combinations of all 16 tester channels are used to drive either the select or data lines of the MUXs. The results indicate that greater encoding flexibility can be obtained by not having a separate control line. Another interesting result is that using two-input XOR gates is not as good as using MUXs for low numbers of specified bits, but it becomes better than MUXs when the number of specified bits is equal to 10 or more. Using three-input XORs provides considerably better encoding flexibility, although it comes with the tradeoff of adding more complexity to the ATPG than the others.

Figure 2.46. Encoding flexibility among combinational decompression schemes.

The experiments indicate that using the combinational XOR network for test stimulus decompression provides the highest encoding flexibility and hence can provide better compression than using other broadcast-scan-based schemes. The more inputs used per XOR gate, the better the encoding flexibility. Better encoding flexibility allows a more aggressive expansion ratio and allows the ATPG to perform more dynamic compaction resulting in better compression.

A space compactor is a combinational circuit for compacting m outputs of the circuit under test to n test outputs, where n < m. Space compaction can be regarded as the inverse procedure of linear expansion (which was described in Section 2.4.1.2). It can be expressed as a function of the input vector (i.e., the data being scanned out) and the output vector (the data being monitored):

Y = Φ(X)

where X is an m-bit input vector and Y is an n-bit output vector, n < m. Because each output sequence can contain unknown values (X’s), the space compaction scheme in use shall have the capability to mask off or tolerate unknowns in order to prevent faults from going undetected.

X-Compact

X-compact [Mitra 2004] is an X-tolerant response compaction technique and has being used in several designs. The combinational compactor circuit designed using the X-compact technique is called an X-compactor. Figure 2.47 shows an example of the X-compactor with eight inputs and five outputs. It is composed of 4 three-input XOR gates and 11 two-input XOR gates.

Figure 2.47. An X-compactor with eight inputs and five outputs.

The X-compactor can be represented as a binary matrix (matrix with only 0’s and 1’s) with n rows and k columns; this matrix is called the X-compact matrix. Each row of the X-compact matrix corresponds to a scan chain, and each column corresponds to an X-compactor output. The entry in row i and column j of the matrix is 1 if and only if the jth X-compactor output depends on the ith scan chain output; otherwise, the matrix entry is 0. The corresponding X-compact matrix M of the X-compactor shown in Figure 2.47 is as follows:

For a conventional sequential compactor, such as a MISR, there are two sources of aliasing: error masking and error cancellation. Error masking occurs when one or more errors captured in the compactor during a single cycle propagate through the feedback path and cancel out with errors in the later cycles. Error cancellation occurs when an error bit captured in a shift register is shifted and eventually cancelled by another error bit. The error cancellation is a type of aliasing specific to multiple-input sequential compactor. Because the X-compactor is a combinational compactor, it only results in error masking. To handle aliasing, the following theorems provide a basis for systematically designing X-compactors:

X-Masking

Although it may not result in fault coverage loss, the X-blocking technique does add area overhead and may impact delay because of the inserted logic. It is not surprising to find that, in complex designs, more than 25% of scan cycles could contain one or more X’s in the test response. It is difficult to eliminate these residual X’s by DFT; thus, an encoder with high X-tolerance is very attractive. Instead of blocking the X’s where they are generated, the X’s can also be masked off right before the response compactor [Wohl 2004] [Han 2005a] [Volkerink 2005] [Rajski 2005, 2006]. An example X-masking circuit is shown in Figure 2.48. The mask controller applies a logic value 1 at the appropriate time to mask off any scan output that contains an X.

Figure 2.48. An example X-masking circuit.

Mask data are needed to indicate when the masking should take place. These mask data can be stored in compressed format and can be decompressed using on-chip hardware. Possible compression techniques are weighted pseudo-random LFSR reseeding or run-length encoding [Volkerink 2005].

Example 2.1

An example of algorithmically handling X-impact is shown in Figure 2.49. Here, SC1 to SC4 are scan cells connected to a space compactor composed of XOR gates G7 and G8. Lines a, b,..., h are internal signals, and line f is assumed to be connected to an X-source (memory, non-scan storage element, etc.). Now consider the detection of the stuck-at-0 (SA0) fault f1. Logic value 1 should be assigned to both lines d and e in order to activate f1. The fault effect will be captured by scan cell SC3. If the X on f propagates to SC4, then the compactor output q will become X and f1 cannot be detected. To avoid this outcome, ATPG can try to assign either 1 to line g or 0 to line h in order to block the X from reaching SC4. If it is impossible to achieve this assignment, ATPG can then try to assign 1 to line c, 0 to line b, and 0 to line a in order to propagate the fault effect to SC2. As a result, fault f1 can be detected. Thus, X-impact is avoided by algorithmic assignment without adding any extra circuitry.

Figure 2.49. Handling of X-impact.

Example 2.2

It is also possible to use the X-impact approach to reduce aliasing. An example of algorithmically handling aliasing is shown in Figure 2.50. Here, SC1 to SC4 are scan cells connected to a compactor composed of XOR gates G7 and G8. Lines a, b,..., h are internal signals. Now consider the detection of the stuck-at-1 fault f2. Logic value 1 should be assigned to lines c, d, and e in order to activate f2, and logic value 0 should be assigned to line b in order to propagate the fault effect to SC2. If line a is set to 1, then the fault effect will also propagate to SC1. In this case, aliasing will cause the compactor output p to have a fault-free value, resulting in an undetected f2. To avoid this outcome, ATPG can try to assign 0 to line a in order to block the fault effect from reaching SC1. As a result, fault f2 can be detected. Thus, aliasing can be avoided by algorithmic assignment without any extra circuitry.

Figure 2.50. Handling of aliasing.

A time compactor uses sequential logic (whereas a space compactor uses combinational logic) to compact test responses. Because sequential logic is used, one must make sure that no unknown (X) values from the circuit under test will reach the compactor. If that happens, X-bounding or X-masking must be employed.

The most widely adopted response compactor using time compaction is the multiple-input signature register (MISR). The MISR uses m extra XOR gates for compacting each m-bit-wide output sequence into the LFSR simultaneously. The final contents stored in the MISR after compaction is called the (final) signature of the MISR. For more information on signature analysis and the MISR design, refer to [Wang 2006a].

The previous two sections introduced different kinds of compactors for space compaction and time compaction independently. This section introduces mixed time and space compactors [Saluja 1983]. A mixed time and space compactor combines the advantages of a time compactor and a space compactor. Many mixed time and space compactors have been proposed in the literature, including OPMISR [Barnhart 2002], convolutional compactor [Rajski 2005], and q-compactor [Han 2003] [Han 2005a,b].

Because q-compactor is simple, this section uses it to introduce the conceptual architecture of a mixed time and space compactor. Figure 2.51 shows an example of a q-compactor assuming the inputs are coming from scan chain outputs. The spatial part of the q-compactor consists of single-output XOR networks (called spread networks) connected to the flip-flops by means of additional two-input XOR gates interspersed between successive storage elements. As the figure shows, every error in a scan cell can reach storage elements and then outputs in several possible ways. The spread network that determines this property is defined in terms of spread polynomials indicating how particular scan chains are connected to the register flip-flops.

Figure 2.51. An example q-compactor with single output.

Different from a conventional MISR, the q-compactor presented in Figure 2.51 does not have a feedback path; consequently, any error or X injected into the compactor is shifted out after at most five cycles. The shifted-out data will be compared with the expected data and then the error will be detected.

A progressive random-access scan (PRAS) design [Baik 2005a] was proposed in an attempt to alleviate the problems associated with the traditional serial scan design. The PRAS scan cell, as shown in Figure 2.55a, has a structure similar to that of a static random access memory (SRAM) cell or a grid-addressable latch [Susheel 2002], which has significantly smaller area and routing overhead than the traditional scan cell design [Ando 1980]. In normal mode, all horizontal row enable RE signals are set to 0, forcing each scan cell to act as a normal D flip-flop. In test mode, to capture the test response from D, the RE signal is set to 0 and a pulse is applied on clock Φ, which causes the value on D to be loaded into the scan cell. To read out the stored value of the scan cell, clock Φ is held at 1, the RE signal for the selected scan cell is set to 1, and the content of the scan cell is read out through the bidirectional scan data signals SD and . To write or update a scan value into the scan cell, clock Φ is held at 1, the RE signal for the selected scan cell is set to 1, and the scan value and its complement are applied on SD and , respectively.

Figure 2.55. Progressive random-access scan design: (a) PRAS scan cell design, (b) PRAS architecture, and (c) PRAS test procedure.

The PRAS architecture is shown in Figure 2.55b, where rows are enabled in a fixed order, one at a time, by rotating a 1 in the row enable shift register. That is, it is only necessary to supply a column address to specify which scan cell in an enabled row to access. The length of the column address, which is ⌈log₂ m⌉ for a circuit with m columns, is considerably shorter than a full (row and column) address; therefore, the column address is provided in parallel in one clock cycle instead of providing a full address in multiple clock cycles. This reduces test application time. To minimize the need to shift out test responses, the scan cell outputs are compressed with a multiple-input signature register (MISR).

The test procedure of the PRAS design is shown in Figure 2.55c. For each test vector, the test stimulus application and test response compression are conducted in an interleaving manner when the test mode signal TM is enabled. That is, all scan cells in a row are first read into the MISR for compression simultaneously, and then each scan cell in the row is checked and updated if necessary. Repeating this operation for all rows compresses the test response to the previous test vector into the MISR and sets the next test vector to all scan cells. Next, TM is disabled and the normal clock is applied to conduct test response acquisition. The figure shows that the smaller the number of scan cells to be updated for each row, the shorter the test application time. This can be achieved by reducing the Hamming distance between the next test vector and the test response to the previous test vector. Possible solutions include test vector reordering and test vector modification [Baik 2004; 2005a,b; 2006] [Le 2007].

The PRAS design has demonstrated that it can significantly reduce shift power dissipation by 100X and reduce routing overhead to within 10%. One difficulty is the control complexity of the test control logic for updating the selected scan cells one at a time. In fact, when a PRAS design contains 100 or more rows (scan cells), reduction in shift power dissipation could also possibly reach 100X, even if all columns would have to be updated simultaneously [Wang 2006c].

The shift-addressable random-access scan (STAR) architecture proposed in [Wang 2006c] uses only one row (X) decoder and supports two or more SI and SO ports. All rows are enabled (selected) in a fixed order one at a time by rotating a 1 in the row enable shift register. When a row is enabled, all columns (or scan cells) associated with the enabled row are selected at the same time; therefore, there is no need to provide a column address. This reduces the test application time as opposed to traditional RAS designs, which require a column address to write a selected scan cell one at a time [Ando 1980] [Baik 2005a] [Mudlapur 2005] [Hu 2006]. The STAR architecture and its associated test procedure are shown in Figure 2.56. The STAR architecture can use any RAS scan cell design as proposed in [Wagner 1984], [Baik 2005a], or [Mudlapur 2005].

Figure 2.56. Test procedure for a shift-addressable random-access scan (STAR) design: (a) STAR architecture and (b) STAR test procedure.

It has been reported in [Baik 2005a] and [Mudlapur 2005] that RAS design can easily provide a 100X reduction in shift power dissipation. Because each scan cell is updated when needed, a 2X to 3X reduction in test data volume and test application time is also achieved. These results indicated that RAS design achieved a significant reduction in shift power dissipation, as well as a good reduction in test data volume and test application time. Whether or not RAS design can further reduce capture power dissipation remains a research topic.