Copyright
by Nur Touba, Charles Stroud, Laung-Terng Wang
System-on-Chip Test Architectures: Nanometer Design for Testability
- Copyright
- The Morgan Kaufmann Series in Systems on Silicon
- Preface
- In the Classroom
- Acknowledgments
- Contributors
- About the Editors
- 1. Introduction
- 2. Digital Test Architectures
- About This Chapter
- 2.1. Introduction
- 2.2. Scan Design
- 2.3. Logic Built-In Self-Test
- 2.4. Test Compression
- 2.5. Random-Access Scan Design
- 2.6. Concluding Remarks
- 2.7. Exercises
- Acknowledgments
- References
- 3. Fault-Tolerant Design
- About This Chapter
- 3.1. Introduction
- 3.2. Fundamentals of Fault Tolerance
- 3.3. Fundamentals of Coding Theory
- 3.4. Fault Tolerance Schemes
- 3.5. Industry Practices
- 3.6. Concluding Remarks
- 3.7. Exercises
- Acknowledgments
- References
- 4. System/Network-on-Chip Test Architectures
- About This Chapter
- 4.1. Introduction
- 4.2. System-on-Chip (SOC) Testing
- 4.3. Network-on-Chip (NOC) Testing
- 4.4. Design and Test Practice: Case Studies
- 4.5. Concluding Remarks
- 4.6. Exercises
- Acknowledgments
- References
- 5. SIP Test Architectures
- 6. Delay Testing
- 7. Low-Power Testing
- 8. Coping with Physical Failures, Soft Errors, and Reliability Issues
- About This Chapter
- 8.1. Introduction
- 8.2. Signal Integrity
- 8.3. Manufacturing Defects, Process Variations, and Reliability
- 8.4. Soft Errors
- 8.5. Defect and Error Tolerance
- 8.6. Concluding Remarks
- 8.7. Exercises
- Acknowledgments
- References
- 9. Design for Manufacturability and Yield
- 10. Design for Debug and Diagnosis
- 11. Software-Based Self-Testing
- About This Chapter
- 11.1. Introduction
- 11.2. Software-Based Self-Testing Paradigm
- 11.3. Processor Functional Fault Self-Testing
- 11.4. Processor Structural Fault Self-Testing
- 11.5. Processor Self-Diagnosis
- 11.6. Testing Global Interconnect
- 11.7. Testing Nonprogrammable Cores
- 11.8. Instruction-Level DFT
- 11.9. DSP-Based Analog/Mixed-Signal Component Testing
- 11.10. Concluding Remarks
- 11.11. Exercises
- Acknowledgments
- References
- R11.0. Books
- R11.1. Introduction
- R11.2. Software-Based Self-Testing Paradigm
- R11.3. Processor Functional Fault Self-Testing
- R11.4. Processor Structural Fault Self-Testing
- R11.5. Processor Self-Diagnosis
- R11.6. Testing Global Interconnect
- R11.7. Testing Nonprogrammable Cores
- R11.8. Instruction-Level DFT
- R11.9. DSP-Based Analog/Mixed-Signal Component Testing
- 12. Field Programmable Gate Array Testing
- 13. MEMS Testing
- About This Chapter
- 13.1. Introduction
- 13.2. MEMS Testing Considerations
- 13.3. Test Methods and Instrumentation for MEMS
- 13.4. RF MEMS Devices
- 13.5. Optical MEMS Devices
- 13.6. Fluidic MEMS Devices
- 13.7. Dynamic MEMS Devices
- 13.8. Testing Digital Microfluidic Biochips
- 13.9. DFT and BIST for MEMS
- 13.10. Concluding Remarks
- 13.11. Exercises
- Acknowledgments
- References
- 14. High-Speed I/O Interfaces
- About This Chapter
- 14.1. Introduction
- 14.2. High-Speed I/O Architectures
- 14.3. Testing of I/O Interfaces
- 14.4. DFT-Assisted Testing
- 14.5. System-Level Interconnect Testing
- 14.6. Future Challenges
- 14.7. Concluding Remarks
- 14.8. Exercises
- Acknowledgments
- References
- 15. Analog and Mixed-Signal Test Architectures
- About This Chapter
- 15.1. Introduction
- 15.2. Analog Functional Testing
- 15.3. Analog and Mixed-Signal Test Architectures
- 15.4. Defect-Oriented Mixed-Signal BIST Approaches
- 15.5. FFT-Based Mixed-Signal BIST
- 15.6. Direct Digital Synthesis BIST
- 15.7. Concluding Remarks
- 15.8. Exercises
- Acknowledgments
- References
- 16. RF Testing
- About This Chapter
- 16.1. Introduction
- 16.2. Key Specifications for RF Systems
- 16.2.1. Test Instrumentation
- 16.2.2. Test Flow in Industry
- 16.2.3. Characterization Test and Production Test
- 16.2.4. Circuit-Level Specifications
- 16.2.4.1. Gain
- 16.2.4.2. Harmonics and Third-Order Intercept Point (IP3)
- 16.2.4.3. 1-dB Compression Point (P–1dB)
- 16.2.4.4. Total Harmonic Distortion (THD)
- 16.2.4.5. Gain Flatness
- 16.2.4.6. Noise Figure
- 16.2.4.7. Sensitivity and Dynamic Range
- 16.2.4.8. Local Oscillator Leakage
- 16.2.4.9. Phase Noise
- 16.2.4.10. Adjacent Channel Power Ratio
- 16.2.5. System-Level Specifications
- 16.2.6. Structure of RF Systems
- 16.3. Test Hardware: Tester and DIB/PIB
- 16.4. Repeatability and Accuracy
- 16.5. Industry Practices for High-Volume Manufacturing
- 16.6. Concluding Remarks
- 16.7. Exercises
- Acknowledgments
- References
- 17. Testing Aspects of Nanotechnology Trends
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Library of Congress Cataloging-in-Publication DataSystem-on-chip test architectures: nanometer design for testability / edited by Laung-Terng Wang, Charles Stroud, and Nur Touba. p. cm. Includes bibliographical references and index. ISBN 978-0-12-373973-5 (hardcover : alk. paper) 1. Systems on a chip—Testing. 2. Integrated circuits—Very large scale integration—Testing.3. Integrated circuits—Very large scale integration—Design.I. Wang, Laung-Terng. II. Stroud, Charles E. III. Touba, Nur.TK7895.E42S978 2007621.39’5–dc22 2007023373
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