F. Foster DaiAuburn University, Auburn, Alabama
Charles E. StroudAuburn University, Auburn, Alabama
The scale of analog integrated circuits (ICs) and the analog portion of mixed-signal ICs is usually relatively small compared to digital IC counterparts—hundreds of devices in an analog circuit compared to millions to hundreds of millions of devices in a digital circuit. However, testing analog circuits poses a number of unique testing problems when compared to digital circuits and, as a result, requires a variety of different and unique test architectures and approaches. For example, there are no analog fault models that have been widely accepted, as is the case in digital testing. As a result, most analog testing tends to be specification-oriented as opposed to defect-oriented approaches typically used when testing digital circuitry. This is due in part to the fact that there is a range of good circuit signal values that result from acceptable component tolerances, environmental variations (including temperature and supply voltage), and noise.
An introduction to analog and mixed-signal testing was given in [Wang 2006], and a number of exceptional books have been dedicated to testing analog and mixed-signal circuits, including [Burns 2000], [Mahoney 1987], [Roberts 1995], and [Vinnakota 1998]. Therefore, this chapter begins with an overview of some of the challenges in analog and mixed-signal testing followed by a discussion of some fundamental analog test techniques and measurements. The chapter then focuses on test architectures that can be included for on-chip test and measurement of the analog portion(s) of system-on-chip (SOC) implementations. Built-in self-test (BIST) for digital circuits has been an active area of research and development since the mid-1970s, resulting in a number of good BIST approaches to test the digital portion of mixed-signal systems. Until recently, however, BIST for analog circuitry has received much less attention. As a result, testing the analog portion of mixed-signal integrated circuits and systems has been identified as one of the major challenges for the future, and BIST has been identified as one of the potential solutions to this testing challenge [SIA 2005, 2006].
There are two basic approaches for testing analog circuitry:functional testing, also referred to as specification-oriented testing, and structural testing, also referred to as defect-oriented testing. Specification-oriented testing has long been the preferred approach because of the continuous signals produced by analog circuits, the wide range and variety of analog circuits, and their nonlinear characteristics. Feedback is frequently incorporated to overcome the effect of acceptable component parameter variations caused by the nature of the manufacturing process as well as operational temperature and voltage variations. These factors complicate the process of testing to determine if an analog circuit is faulty or operating within acceptable range. This determination often requires highly accurate (and expensive) test equipment to perform the necessary measurements. Whereas a digital circuit can be decomposed to gates or to transistors for defect-oriented testing, the components of an analog circuit function collectively to perform the overall functionality of a given circuit and, as a result, cannot always be treated as a collection of individual components.
Fault models have been proposed for defect-oriented analog and mixed-signal testing. These fault models can be classified into two categories: catastrophic faults (or hard faults) and parametric faults (or soft faults) [Kaminska 1997]. Parametric faults are deviations of component parameters that are outside the acceptable range or specified tolerance limits. A catastrophic fault is similar to digital fault models in that terminals of the component can be stuck-open or stuck-short (with another terminal). Stuck-open faults are hard faults in which the component terminals are not in contact with the rest of the circuit or create a high resistance at the location of the fault in the circuit. A stuck-short fault, on the other hand, is a short between terminals of the component, effectively shorting out the component from the circuit. Alternatively, the terminals of two different components can be shorted, similar to bridging faults in a digital circuit.
The primary purpose of fault models is to facilitate emulation of defects for the evaluation of the fault detection capabilities associated with a given set of test waveforms via fault simulation. Analog fault simulation requires many simulations of the fault-free circuit to establish normal variations in the output waveforms that result from acceptable component parameter variations as well as temperature and voltage variations. A known range of acceptable values for circuit component parameters is necessary to establish the fault-free behavior for a given circuit, which can then be used to determine if a fault can be detected. An analog fault simulator may support Gaussian (normal) or uniform component parameter variations. Standard deviation or the 1σ value is typically used for specifying the normal distribution, which, in turn, assumes the components will vary up to ±3σ while the analog circuit continues to operate within the system specifications. Monte Carlo analysis is typically used to generate different component values for fault-free components within the normal or uniform distributions. During catastrophic and parametric fault simulation, each emulated faulty circuit must also undergo a number of simulations for Monte Carlo analysis. This means that analog fault simulation is more time intensive than digital fault simulation and, as a result, the debate continues between functional (specification-oriented) and structural (defect-oriented) testing approaches.
Analog signals are continuous waveforms and, as illustrated in Figure 15.1, the interpretations for a time domain response are different in the analog and digital domains. Whereas a digital designer is primarily concerned with logic ones and zeros, an analog designer cares about the detailed shape of the waveform and its corresponding spectrum. Logic high and low voltages (VH and VL) as well as rise and fall times (tLH and tHL) are the major attributes of concern in testing a digital waveform. In an analog waveform, on the other hand, the major testing parameters include the amplitude (VA), slew rate (SR), overshoot (VOV), settling time (tSettle), bandwidth, phase noise, and timing jitter. As a result, there is a variety of different test and measurement concerns for analog designers and test engineers, as discussed in the following subsections.
Figure 15.1. Digital and analog representations for a time domain response: (a) digital and (b) analog.
Frequency response measures the frequency dependence of the output signal of an analog device under test (DUT). As an example, Figure 15.2 illustrates the frequency response of a band-pass filter, which is characterized by its pass band, stop band, and transition band in between. As shown in the figure, the pass band is defined as the frequency range in which a signal can pass with little attenuation. Conversely, a signal falling in the stop band will be significantly attenuated. Pass band ripple is the variation of the amplitude response in the pass band. The difference in attenuation from pass band to stop band is defined as the stop band rejection ratio and is measured in dB. In the transition bands, the filter rise or rolloff slope is determined by the order of the filter, which follows the 6 dB/octave/order or 20 dB/decade/order rule.
In frequency response testing, the DUT is usually driven by a signal generator and its output is analyzed by a spectrum analyzer to obtain the measurement result. To correctly use a spectrum analyzer, let’s briefly review its basic operation theory. As shown in Figure 15.3, the spectrum analyzer down-converts the input radio frequency (RF) signal to baseband frequency through two filters, an analog intermediate frequency (IF) filter and a digital video filter, whose bandwidths (BWs) are defined as resolution bandwidth (RBW) and video bandwidth (VBW), respectively and can be determined by the analyzer setting. The video filter is used to smooth noise for easier identification and measurement of low-level signals. The IF filter, on the other hand, integrates the input signal and noise power over the RBW. Hence, the phase noise reading on the spectrum analyzer is not the real noise level and is tightly dependent on the RBW. For example, a phase noise reading of –100 dBc with a RBW setting of 10 Hz in a spectrum analyzer would be –90 dBc with a RBW setting of 100 Hz. Accordingly, the best sensitivity in a spectrum analyzer is achieved by using the narrowest RBW, minimum RF attenuation, and sufficient video filtering to smooth the noise (normally, VBW is less than 1% of the RBW). Because a spectrum analyzer measures the baseband signal power, the power spectral density (PSD) reading is normally single sideband. A proper sweeping setting is required to obtain symmetric sideband measurement. The penalty for fast sweeping is an uncalibrated display on sidebands.
Linearity is an important performance measure of many analog components such as amplifiers and mixers. The nonlinear characteristics of a circuit result in intermodulation of various components of a signal, referred to as intermodulation distortion (IMD). IMD is of concern in communication circuits because it can modulate the tone in adjacent bands and cause interference. Theoretically, IMD could be tested using multitone signals. However, only two or three tones are used in real analog testing. Assume two tones x(t) = A1cosω1t + A2cosω2t with frequencies of f1 = ω1/2π and f2 = ω2/2π are applied to the input of an amplifier with transfer function expressed as y(t) = α0 + α1x(t) + α2x2(t) + α3x3(t) + ..., where αj is, in general, independent of time if the system is time invariant. Substituting the two-tone input into the transfer function, we obtain the amplifier output as:
Figure 15.4 illustrates the spectrum of a waveform in response to two tones. When the two-tone test signal passes through an amplifier, both fundamental and intermodulation (IM) terms will be present at the amplifier output. Any linear combinations of f1 and f2 may appear because of the IMD. However, the closest intermodulation terms to the fundamental terms are the third-order intermodulation (IM3) terms with frequencies of 2f1 – f2 and 2f2 – f1. Therefore, the linearity is normally measured using the third-order intercept point (IP3), where the linear term intercepts the third-order term in a two-tone test as illustrated in Figure 15.5b.
Figure 15.5. Linearity measurement using two-tones test: (a) output spectrum under two-tone test and (b) third-order intercept point (IP3).
According to Equation (15.1) with A1 = A2, the input referred IP3 (IIP3) and the output referred IP3 (OIP3) can be found as:
where the assumption for IIP3 is normally valid when the test tone magnitude is relatively small, such that the amplifier is not desensitized. In the two-tone test, the IIP3 can be found by measuring the difference, ΔP, between fundamental and IM3 terms. As shown in Figure 15.5, the IIP3 is given by:
where Pin is the signal power at the amplifier input. As discussed later in this chapter, there are various ways to generate a two-tone test for IIP3 measurement.
Another measure of the linearity is the so-called gain compression test. Referring to Figure 15.6, the gain of an amplifier, defined as the ratio of the output power to the input power, remains constant with small input power. When the input power increases, the gain is compressed, deviating from the linear gain curve. Define power unit dBm as 
. The 1-dB compression point is defined as the input signal level that causes small-signal gain to drop 1 dB from the linear gain. P1dB is the input power in dBm that corresponds to the 1-dB compression point. It is a measure of the maximum input range. With a single tone input, the P1dB can be found as:
Considering Equation (15.2), the relationship between the P1dB and the IIP3 can be estimated by:
In other words, IIP3 is about 9.66 dB higher than the P1dB value. Note that Equation (15.5) is valid only for single tone input. For two-tone input, IIP3 is about 14.4 dB higher than the P1dB value.
The signal-to-noise ratio (SNR) reflects how pure a signal is and is defined as the ratio of the signal power to the noise power represented in dB. There are many sources for noise in an electronic system including thermal noise, flicker noise, power supply noise, switching noise, coupling noise, etc. Distortions, such as harmonic distortion and IMD, further degrade the signal’s quality. Distortions often result from crossover, clip, saturation, and mismatch of differential signal paths. When a pure sinusoidal waveform is generated with additive white Gaussian noise (AWGN) and applied to the DUT, a typical output spectrum can be illustrated as in Figure 15.7.
Frequency components of a sinusoidal waveform are classified into three categories. The first category, F, is the fundamental component—the desired signal. F can be a voltage or a current signal, and F2 represents the corresponding power for P = I2R = V2/R. The second category, Hi, is the ith harmonic, and the final category, Ni, represents the ith noise term. The SNR and distortion can be obtained from the following equations:
The total harmonic distortion (THD) is the ratio of signal power to the harmonic power in total and, as a result, harmonic terms Hi are included. THD is represented in either dB or percentage. In the signal-to-noise and distortion ratio (SINAD), both noise and distortion terms are considered. The peak harmonic is also important because it can often be used to locate the source of distortion. For example, if the second harmonic is the peak harmonic, crossover distortion or symmetric nonlinear distortion is the most likely source. On the other hand, clipping and saturation are the most likely sources if the third harmonic is the peak harmonic.
In sampled systems such as mixed-signal systems with data converters, quantization noise needs to be carefully analyzed. A quantizer converts the continuous analog signal to a discrete digital signal with a characteristic shown in Figure 15.8, where the output is a function of the input, but has discrete levels. Thus, unless the input happens to be an integer multiple of the quantizer step size Δ, there will always be an error in representing the input. This error e will be bounded over one quantizer level by a value of:
Thus, the quantized signal y can be represented by a linear function Gx with an error e as y = Gx + e, where the gain G is the slope of the straight line in Figure 15.8. If the input is “random” in nature, then the instantaneous error will also be random. The error is thus uncorrelated from sample to sample and can be treated as noise. Quantization and the resultant quantization noise can be modeled as a linear circuit including an additive error source to represent the quantization noise.
The quantization noise for a random signal can be treated as additive white noise with equal probability of locating anywhere in the range –Δ/2 to Δ/2 and has probability density of:
where the normalization factor 1/Δ is needed to guarantee that 
. The mean square rms error voltage erms can be found by integrating the square of the error voltage and dividing by the quantization step size, namely:
Note that frequency spectrums of sampled systems repeat once every sampling frequency. Thus, the spectrum of the quantization noise in a sampled system will be centered around DC and spread out to fS/2, and there will be a copy of the noise spectrum from fS/2 to 3fS/2, etc. Considering that all the noise power lies in the range 0 ≤ f < ∞, the quantization noise power thus folds into the band from DC to fS/2. Assuming white noise, the power spectral density of the quantization noise is given by 
, where the sample period T = 1/fS. For a band limited signal with bandwidth over [0, f0], the quantization noise power that falls into the signal band can thus be found as:
where the oversampling rate (OSR) is defined as the ratio of the sampling frequency fS to the Nyquist rate 2f0, namely, OSR = fS/2f0. Thus, for the same amount of total quantization noise power, every doubling of the sampling frequency reduces the in-band quantization noise by 3 dB. Oversampling has the advantage that it eases requirements on analog antialiasing filters for an analog-to-digital converter (ADC) or deglitch filters for a digital-to-analog converter (DAC). This is because oversampling results in wide transition bands; hence only low-order filters are required. However, the higher sampling rate requires not only faster digital circuits but also much lower signal bandwidth, which also means a lower conversion rate.
In an N-bit sampled system, if the quantizer has 2N quantization levels equally spaced by Δ, then the maximum peak-to-peak amplitude is given by vmax = (2N– 1)·Δ. If the signal is sinusoidal, the associated signal power can be found by 
. Thus, the SNR caused by the quantization noise power that falls into the signal band becomes:
Noting that log10(x) = log10(2)·log2(x), the preceding expression can be rewritten as:
Therefore, the SNR improves by 6 dB for every bit added to the quantizer. For the same amount of total quantization noise power, every doubling of the sampling frequency reduces the in-band quantization noise by 3 dB. Hence, doubling the oversampling ratio is equivalent to increasing the quantizer levels by a half bit as far as the quantization noise is concerned.
The noise performance for an analog circuit is usually classified in terms of phase noise, which is a measure of how much the output diverges from an ideal impulse function in the frequency domain. We are primarily concerned with noise that causes fluctuations in the phase of the output rather than noise that causes amplitude fluctuations in the tone, because the oscillator output typically has limited amplitude. A spectrum analyzer is often used to test the phase noise of an analog signal. To understand the phase noise reading of dBc/Hz on a spectrum analyzer, consider a phase-locked loop (PLL) as an example. The output signal of a PLL can be described as [Rogers 2006]:
where ωLOt is the desired phase of the output and ϕn(t) is random phase fluctuations. Phase noise is often quoted in units of dBc/Hz, whereas random phase fluctuation is often quoted in units of rad2/Hz. The phase fluctuation term ϕn(t) may be random phase noise or discrete spurious tones, as shown in Figure 15.9. The discrete spurs at a synthesizer output are most likely due to the fractional-N mechanism and the phase noise in an oscillator, which is mainly due to thermal, flicker, or 1/f noise and the finite Q of the oscillator tank.
Assume the phase fluctuation is of a sinusoidal form ϕn(t) = ϕpsin(ωmt), where ϕp is the peak phase fluctuation and ωm is the offset frequency from the carrier. Substituting the phase fluctuation expression into Equation (15.13) gives:
Assuming a small phase fluctuation, Equation (15.14) can be simplified as:
It is now evident that the phase-modulated signal includes the carrier signal tone and two symmetric sidebands at any offset frequency. A spectrum analyzer measures the phase-noise power in dBm/Hz, but in most cases phase noise is normalized by the carrier power as illustrated in Figure 15.9 and reported in units of rad2/Hz or dBc/Hz, namely:
where Noise and Pcarrier are the PSD of the noise and the carrier signal, respectively. Furthermore, both single sideband and double sideband phase noise can be defined. Single sideband (SSB) phase noise-to-carrier ratio is defined as the ratio of power in one phase modulation sideband per Hertz bandwidth, at an offset Δω away from the carrier frequency, to the total signal power as:
This equation can be rewritten as:
where 
is the root mean square (rms) phase-noise power density in units of [rad2/Hz]. Alternatively, double sideband (DSB) phase noise-to-carrier ratio is given by:
Note that SSB phase noise is by far the most commonly used measure for phase noise and the subscript SSB is often ignored. From either the SSB or DSB phase noise, the rms jitter can be obtained as follows:
It is also quite common to quote rms integrated jitter which is given by:
The limits of the integration are usually the offsets of the lower and upper frequencies of the bandwidth of the information being transmitted relative to the carrier frequency. In addition, it should be noted that dividing or multiplying a signal in the time domain also divides or multiplies the phase noise. Thus, if a signal is translated in frequency by a factor N, then the phase noise is related by:
In the preceding equations, we have assumed that the circuit for frequency translation, a mixer for example, is noiseless. Also, note that the phase noise is scaled by N2 rather than N because we are dealing with noise power in units of V2 rather than noise voltage.
A phase-locked loop (PLL) is the critical component in frequency synthesis and clock data recovery (CDR). A variety of factors influence the noise and spurious outputs of a PLL. Every component in a PLL contributes a certain amount of noise at the output. As shown in Figure 15.10, the phase noise sources include noise from the reference source θREF, noise from the phase detector θPD, noise from the reference divider θR and from the feedback divider θN, noise from the low-pass loop filter θLPF, and noise from the voltage controlled oscillator (VCO) θVCO.
In a feedback system, phase noise coming from different sources is independent and has different impact on the system noise performance. The total output noise PSD can be determined by [Rogers 2006]:
where S represents the phase noise power spectral density, kPD is the phase detector gain in V/rad, kVCO is the VCO gain in rad/sec/V, GLPF is the low-pass filter transfer function, G(s) = kPDGLPFkVCO/s is the open loop transfer function, and 
is the close loop transfer function, which approaches N at DC. Notice the loop has a high-pass effect on the VCO noise because of the term 
and has a low-pass effect on other noise sources because of the term 
. Thus, the in-band phase noise is determined by noise coming from the reference, phase detector, low-pass filter, and frequency dividers. On the other hand, the out-band phase noise is dominated by VCO noise, which determines the interchannel interference.
The in-band phase noise determines the close-in noise at the synthesized frequency. Suppose the closed loop transfer function has a flat response within the pass band and the loop bandwidth is sufficient to reject the VCO noise; we obtain the phase noise within the loop bandwidth as [Larson 1996]:
Note that the PLL magnifies the noise from the reference, phase detector, low pass filter (LPF) and the dividers by the amount of 20logN dB. The phase detector gain is normally given by kPD = VPD/2π[V / rad], where VPD is the phase detector output voltage. For VPD = 500 mV, kPD = 0.0796 [V/rad].
Crystal reference noise. Quartz crystal resonators are widely used in frequency control applications because of their unequaled combination of high Q, stability, and small size. The resonators are classified according to “cut,” which is the orientation of the quartz wafer with respect to the crystallographic axes of the material. Some examples are AT-, BT-, CT-, DT-, and SC-cut, but they can also be specified by orientation, for example a +5° X-cut. Although a large number of different cuts have been developed, only AT- and SC-cuts are primarily used at frequencies above approximately 1 MHz (others either are used only at low frequencies and applications other than frequency control and selection, or have been made obsolete by later developments). In addition to the thermal noise with its floor around –160 dBm/Hz, 1/f noise exists in a crystal oscillator. The total noise power spectral density of a crystal oscillator can be determined by Leeson’s formula [Watanabe 2000]:
where f0 is the oscillator output frequency, Δf is the offset frequency, QL is the loaded Q of the resonator, and fc is the corner frequency between 1/f and thermal noise regions, which is normally in the range 1~10 kHz. Because the Q of a crystal resonator is large (e.g., 1,000,000), the reference noise contributes only to the very close-in noise and it quickly reaches the thermal noise floor at the offset frequency around fc.
Frequency divider noise. Frequency dividers consist of switching logic circuits that are sensitive to the clock timing jitter. The jitter in the time domain further converts to phase noise in the frequency domain. The origin of the time jitter/phase noise encountered with rising and falling edges of a digital divider is due to superimposed spurious signals such as Johnson and flicker noise in semiconductor materials or ambient effects (variation of the triggering level caused by temperature and humidity, etc.). Frequency dividers generate spurious noise especially at high frequency operation. Because of the frequency dependence of the timing jitter, the phase noise presented at the input of a divider will be reduced by factor of N at its output. An empirical formula for noise power spectral density of transistor-transistor logic (TTL) dividers is [Egan 1990] [Kroupa 2001] given by:
where
is the PSD of the input signal, fdo is the divider output frequency, and Δf is the offset frequency. Notice that the third term in Equation (15.26) represents the white thermal noise floor and the second term gives the flicker noise. Timing jitter, resulting from coupling, ambient, and supply variations, causes the last term.Frequency/phase detector noise. Phase/frequency detectors suffer both flicker and thermal noise. The noise power spectral density of phase/frequency detectors is given by [Kroupa 1982]:
From (15.27), a phase detector generates a white phase noise floor of around –160 dBm/Hz, which is thermal noise dominant, at large offset frequency. For example, passive phase detectors such as balanced mixers have excellent phase noise performance near –165 dBm/Hz.
Low pass loop filter noise. When the loop filter is a passive one (a simple RC lag or lag-lead network, for example), there are two major sources of noise. One source is 1/f noise generated by capacitors and resistors. The other source is thermal noise caused by LPF input resistance and possibly the decoupling resistance separating the varactor circuits from the loop filter. Thus, the noise power spectral density of a low pass filter can also be given by:
As shown, the noise outside of the PLL bandwidth is determined by VCO phase noise, namely:
Besides flicker noise and thermal noise, part of SVCO comes from the spurious noise components principally introduced by variation at the VCO control line, power supply, package, and substrate coupling. In a feedback-based model, Leeson developed a concise expression of single-sideband VCO noise power spectral density [Leeson 1966]. Accuracy is improved by various extensions to Leeson’s model [Lee 2000]. A widely accepted formula for the ratio of sideband power in a 1-Hz bandwidth at offset frequency Δf to total signal power is:
where f0 is the oscillator output frequency and fc is the boundary frequency between 1/Δf2 and 1/Δf3 regions, namely, the so-called flicker frequency. It should be pointed out that fc is an empirical parameter dependent on processing. QL is the loaded Q of the resonant circuit, ranging from 5 to 20 for an on-chip resonator and 40 to 80 for an off-chip tank. Ps is the average signal power at output of the oscillator active device, and F is the oscillator effective noise figure, which is also an empirical fitting parameter. The term 
shows that the voltage frequency response rolls off as 1/f, which contributes only to the close-in phase noise. The term 2FkT represents the thermal white noise floor. Recall that the thermal noise equivalent power is 
= 4kT · BW. For a unit bandwidth BW = 1 Hz, the thermal noise power = 1.66 × 10—20[W], namely, kT = –174dBm/Hz. Assuming Ps =0 dBm (this delivers about 224mVrms into a 50 ohm load), all the values in [dBm/Hz] are thus equivalent to the values in [dBc/Hz]). For F = 3 dB, we obtain the thermal noise floor at –174dBc/Hz.
In the preceding sections, we discussed various sources of phase noise in a PLL. For PLL testing with minimal phase noise, we need to optimally choose PLL loop parameters such as the reference frequency, the loop division ratio, and the loop bandwidth. Based on the phase noise analysis, we summarize the PLL setting and testing rules as follows:
Division ratio N. The division ratio of the feedback divider, N, has a big impact on loop noise performance. First, the in-band phase noise is magnified by 20logN dB. Second it worsens the PLL’s capability of rejecting in-band VCO noise because
. Therefore, we should choose N as small as possible to minimize the in-band phase noise. However, a small N is not suitable to synthesize high frequency, because the output frequency of the synthesizer is given by 
. Note that the minimal synthesizer step size is fref for R = 1. Therefore, choosing a large reference frequency to synthesize a high output frequency is also not acceptable when a small step size is required. This dilemma can be solved by using a fractional-N scheme with a fractional number of the step size. The major drawback of a fractional-N synthesizer is the fractional spurs that have to be canceled either by a high order loop filter or a sigma-delta noise shaper.Reference frequency. The reference frequency influences the loop division ratio, the synthesizer step size, and the loop noise performance. Choosing a large reference frequency reduces the overall division ratio N for synthesizing the same LO frequency. On the other hand, a larger reference frequency results in a lower Q of the reference resonator and, therefore, higher reference noise. A small reference frequency with a high Q reference source is desirable only when very close-in phase noise (normally <1 kHz offset) or synthesizer step size is an issue.
Loop bandwidth. Loop bandwidth influences the loop settling time, stability, and loop noise performance. The wider the loop bandwidth is, the shorter the loop settling time is. As discussed before, the PLL has a low-pass filtering effect on the in-band phase noise from the reference, phase detector, loop filter, and frequency dividers. Therefore, narrow loop bandwidth benefits the in-band noise filtering. On the other hand, the PLL demonstrates a high-pass filtering effect on the out-band phase noise from the VCO. Therefore, wide loop bandwidth benefits the out-band noise filtering. To minimize the total PLL phase noise, the optimal loop bandwidth should be chosen around the cross point of the in-band phase noise spectral density curve and the out-band (VCO) phase noise spectral density curve. Moreover, loop filter bandwidth should be properly chosen so that the fractional spur can be canceled efficiently.
A DAC is one of the critical components in a mixed-signal system. The DAC is a nonlinear system with nonlinearity, distortion, and quantization noise resulting from finite phase and amplitude resolutions. The effect of finite amplitude word length generates random quantization noise. According to Equation (15.8), at the Nyquist rate, the integrated quantization noise-to-carrier ratio resulting from finite word length, D, is given by 3/2 × 22D = 6.02 × D + 1.76 in units of dB.
On the other hand, because of the finite phase word length, a DAC shows up with the IMD effect that clock frequency fs, output frequency fo, and their harmonics tend to mix with each other and alias back to the Nyquist band. Generally speaking, those discrete aliased images cause the spurs at the following frequencies:
where m and n are integers. However, this is not always the case because the frequencies of the discrete spurs and their amplitude are also dependent on the ratio of the generated frequency, fo, to the sampling clock frequency, fS. For example, if fS is an integer multiple of fo, there will not be any spurs at the DAC’s output caused by these image frequencies. Those spurs will be attenuated by the deglitch filter transfer function and the DAC’s sample-hold function, sinc(π·fo/fs). In other words, the DAC’s zero-order sample-and-hold imposes a sinc attenuation envelope to the fundamental, images, and harmonics of the DAC output as:
While considering the quantization noise resulting from both the finite phase bits and the finite amplitude bits, the worst-case spur magnitude at the DAC output can be estimated and given by [Dai 2006b]:
where P is the number of phase bits and D is the number of DAC input bits. It should be noted that all of the preceding analysis is based on the perfect mathematical model of a DAC. But the real DAC is even more complicated and the signal quality of its output also depends on the quality of the DAC and filter designs as well as the phase noise of the clock frequency. Besides those, real DACs still suffer nonlinearities because of process mismatches, imperfect bit-weight scaling circuits, nonideal switching characteristics, etc.
Because spurs are such an important issue for a DAC, DAC tests are also concerned with output characteristics such as the SINAD and the spurious-free-dynamic-range (SFDR), defined as the ratio between the fundamental signal and the highest spurs.
We now turn our attention to test architectures that can be implemented to test analog circuits or the analog portion of mixed-signal circuits. Digital signal processing (DSP) techniques have been used since the 1980s for fast and accurate testing of analog and mixed-signal circuits [Burns 2000]. In addition, the IEEE 1194.4 standard for a mixed-signal test bus [IEEE 1149.4-1999] can be implemented to improve controllability and observability of analog circuitry as well as to support mixed-signal BIST structures [IEEE1149.4 1999]. Therefore, the focus of the remainder of the chapter will be representative BIST approaches that can be implemented in mixed-signal SOCs to test analog circuitry. However, these test architectures can also be implemented on printed circuit boards for board or system-level testing.
The oscillation BIST (OBIST) approach [Arabi 1997] represents one of the rare cases where a test technique was originally developed to test analog circuitry and was later migrated to test digital circuitry. The basic idea of the OBIST approach is to reconfigure the analog circuit under test to form an oscillating circuit and to evaluate the frequency of oscillation in order to determine the faulty/fault-free status. The basic OBIST architecture is illustrated in Figure 15.11 where the circuits to be tested are partitioned using programmable switches. Each analog circuit contains multiplexers that are used to create a feedback path in the circuit such that it will oscillate in the test mode. The output of each circuit under test is selected in turn by the multiplexer where the oscillations are converted by a level crossing detector to a square wave clock signal, which is, in turn, used to clock an M-bit counter. The test controller produces the enable to the counter. The resulting value in the counter is a function of the frequency of oscillation (fosc) of the circuit under test with respect to the reference frequency (fref). The frequency of oscillation is a function of the structure and component values of each circuit under test. Once the acceptable range of counter values has been established for each circuit under test, faults are detected when the resultant counter value falls outside the good circuit range for that circuit under test.
The OBIST technique has been shown to give high fault coverage for structural (defect-oriented) testing [Arabi 1997]. Note that although the overall approach is inherently mixed-signal because of the digital test controller and counter, the approach does not require the implementation of DACs and ADCs in the system function; instead the ADC function is performed by the level crossing detector. In addition, there is no test pattern generator (TPG), because the circuit under test autonomously produces an output as a result of oscillations. However, there is additional circuitry, not shown in Figure 15.11, required in each circuit under test to reconfigure the circuit into an oscillatory condition. This circuitry must be applied on a case-by-case basis and could impact the performance of the circuit in its system mode of operation.
A typical mixed-signal BIST architecture is shown in Figure 15.12 where the DAC and ADC are assumed to be an existing and integral part of the mixed-signal system application functionality. The majority of the BIST circuitry is then added to the digital portion of the mixed-signal circuitry. The digital BIST circuitry includes TPG and output response analyzer (ORA) functions as well as a test controller. The analog loopbacks are analog multiplexers (denoted MUX1 and MUX2 in the figure) and are the only components associated with the BIST approach to be inserted in the analog domain. As a result, this minimizes the impact of the BIST circuitry on the operation and performance of the analog circuitry. The purpose of the analog loopback is to facilitate a return path for the test signals from the TPG, through the analog circuitry under test, and back to the ORA. An additional multiplexer (denoted MUX3 in the figure) is required for the insertion of the digital test patterns into, and isolation of unknown system data from, the input data stream to the DAC. Because the target circuitry under test is the analog system circuits, including the DACs and ADCs, the digital TPG and its associated multiplexer are incorporated immediately before the digital inputs of the DAC. Similarly, the digital ORA is incorporated at the output of the ADC. This basic architecture has been referred to as the ADC/DAC loopback BIST [Burns 2000], or simply ADC/DAC BIST, and has been implemented in a number of applications including those discussed in the subsequent sections.
Faults can be effectively isolated to a given section of analog circuitry within the diagnostic resolution of the analog loopback multiplexers. For example, with analog loopback MUX1 in Figure 15.12 activated, any faults detected are isolated to that path from the TPG to the ORA through the DAC and ADC. If the first BIST sequence indicates a good circuit, then analog loopback MUX1 can be deactivated while the analog loopback MUX2 is activated and the BIST sequence is reexecuted. Faults detected during this second BIST sequence would be isolated to the analog circuitry in the right-hand portion of Figure 15.12. Therefore, by adding more analog loopback multiplexers at strategic locations, the diagnostic resolution can be improved at the expense of area overhead and possible performance penalties in the analog portion of the mixed-signal system. However, it is also important to include the ability to drive the ORA with the outputs of the TPG, via MUX4, to verify that the digital portion of the BIST circuitry is fault-free before testing the analog portion of the mixed-signal system. A digital ORA facilitates reading BIST results directly through a system processor interface without the need for an ADC to retrieve the test results from the analog portion of the mixed-signal system.
To make the BIST circuitry usable in a system for offline testing and system diagnostics, the BIST circuitry must be capable of proper initialization of the analog circuitry under test, isolation of system data inputs, and reproducible results from one execution of the BIST sequence to the next. This functionality is typically performed by the test controller where control of the start and length of the BIST sequence is implemented by enabling output response compaction in the ORA. For example, the ability to specify the number of test waveform cycles used for initialization as well as the number of test waveform cycles used for the BIST sequence facilitates testing transient or steady-state responses in the analog circuit under test. This is illustrated in Figure 15.13 where a saw-tooth test waveform is applied to an inverting high-pass filter. As can be seen from the oscilloscope picture of the actual TPG waveform at the output of the DAC (top waveform) and the output response at the input to the ADC (bottom waveform), approximately seven cycles of the input test waveform are required before steady-state conditions are achieved. With an initialization count of zero cycles and a BIST sequence count of seven cycles, the entire transient response can be tested. Conversely, with an initialization count of seven, the BIST sequence only tests the steady-state response of the circuit.
An advantage of mixed-signal BIST approaches that use the architecture of Figure 15.12 is the ability to implement a parameterized VHDL or Verilog model of the BIST circuitry. This in turn provides quick and easy incorporation and subsequent synthesis of the BIST circuitry with the digital portion of any mixed-signal system and helps to minimize any adverse performance effects on the analog domain. The BIST circuitry can be easily customized for any particular system application through the specification of the model parameters. In addition to the standard cell based digital portion of a mixed-signal application specific integrated circuit (ASIC), the BIST circuitry can also apply to FPGA-based mixed-signal systems and mixed-signal SoC implementations that incorporate embedded FPGA cores. In these programmable logic cases, the BIST circuitry can be configured into the FPGA core only during offline testing to eliminate any area or performance penalties during normal system operation because the intended system function can be reconfigured in the FPGA core once BIST of the analog circuitry is complete.
Early defect-oriented BIST approaches for the analog portion of mixed-signal systems attempted to make use of digital TPG and ORA functions that were typically used for testing digital circuitry. In the first mixed-signal BIST approach, the TPG consisted of a linear feedback shift register (LFSR) and the ORA consisted of an accumulator [Agrawal 1987]. Similarly, the second mixed-signal BIST approach used an LFSR-based TPG but also used an LFSR-based ORA for signature analysis [Ohletz 1991]. However, in traditional digital circuit signature analysis, the good circuit signature is based on the assumption that an exact output response sequence is obtained for every fault-free execution of the BIST sequence. In a mixed-signal system, the quantization (sampling) noise in the DAC and ADC as well as processing (e.g., tolerances) and environmental (e.g., temperature and voltage) variations in the analog circuitry can prevent an exact output response sequence from one execution of the BIST sequence to the next. As a result, a set of good circuit BIST signatures is difficult to obtain for the fault-free circuit with traditional signature analysis. The accumulator-based ORA [Agrawal 1987], on the other hand, sums the magnitude of the analog circuit output response and facilitates determination of a range of good circuit BIST signatures to account for acceptable changes in the output response caused by component, voltage, and temperature variations as well as quantization noise in the DAC and ADC.
LFSR-based TPGs generate pseudo-random digital patterns that look similar to white noise when passed through a DAC, considered by many to be a universal waveform for testing analog circuits [Pan 1995]. However, ramp input signals have been used in analog testing and have been found to provide good fault detection results and, in some cases, better results than sinusoidal test signals [Chatterjee 1996]. In addition, it has been observed that the detection of faults with respect to the input test signal can vary with the type of analog circuit under test [Balivada 1996]. Therefore, a variety of test waveforms is needed to provide a high probability of fault detection in a wide range of analog application circuits. As a result, some later mixed-signal BIST approaches implemented TPGs that provide a variety of test waveforms including pseudo-random, ramp, saw-tooth, triangular, step, pulse, and DC waveforms, as well as frequency sweeps using a square wave.
An example of this type of TPG is illustrated in Figure 15.14a, which includes a binary up/down counter that also functions as an LFSR [Stroud 2003]. The counter can be used to produce ramp, saw-tooth, and triangular waveforms. The bit reversal multiplexer reverses the order of the bits from the counter to the DAC (MSB becomes LSB and vice versa) and has the effect of producing test patterns with high frequency components that look like noise riding on lower frequency waveforms. When combined with a shift register and count value holding register, the counter can produce square waveforms that sweep through a frequency range. During the frequency sweep waveform generation, the counter starts counting from different initial values loaded from the count value holding register each time the counter completes a count cycle and generates a carry-out pulse. Simultaneously, the count value holding register is reloaded from the counter when the carry-out is shifted through the N-bit shift register. As a result, the contents of the count value holding register differs from the count value by a increment of N. For example, for a 5-bit shift register, an 8-bit counter will count 0–255, 5–255, 10–255, ... , 245–255, and 250–255. A larger number of bits in the shift register will result in a faster frequency sweep. The output data multiplexer sets the magnitude for the square wave whenever the output of the toggle flip-flop (denoted TFF in the figure) is a logic one; otherwise the magnitude is zero. Enabling bit reversal during a frequency sweep will load nonsequential values into the count value holding register and make the square wave frequencies appear pseudo-random in nature.
Improvements in ORA implementations were also made in later mixed-signal BIST approaches to include summing the absolute value of the difference between the input test waveform and the output response of circuit under test [Stroud 1997]. An example of this type of ORA is shown in Figure 15.14b. This facilitates detection of faults that result in noise riding on an otherwise good output response signal, phase shifts, and overshoot or ringing. This is illustrated in Figure 15.15 where the output response to a step function has a delay that can be measured via the resultant sum of the absolute value of the difference between input and output waveforms. As a result, a fault causing excessive delay in the output response will be detected. Similarly, faults that result in undershoot or overshoot/ringing in the output response will also be detected as illustrated in Figure 15.15.
The fault detection capability of these BIST approaches is illustrated in Figure 15.16 taken from an actual BIST implementation with a LPF circuit under test [Stroud 2003]. The input test waveform is a saw-tooth produced by a binary count-up TPG function and is shown as the upper waveform in the oscilloscope pictures for a faulty (see Figure 15.16a) and a fault-free (see Figure 15.16b) LPF with the output response for each circuit shown as the lower waveform. The fault inserted in the LPF was an open feedback capacitor on the op-amp. The ORA in this case is a 16-bit accumulator, which provides a range of possible signature values from 0x0000 to 0xFFFF in hexadecimal. For 1000 executions of the BIST sequence, the good circuit signatures ranged from 0xFCCB to 0xFCCE while the faulty circuit signatures ranged from 0xFB92 to 0xFBA5 as shown in the signature distributions in Figure 15.16c. This example illustrates the fact that a range of good circuit signatures is needed to allow for acceptable signal variations in the analog circuit and shows that this particular fault is always detected by the saw-tooth test waveform because all faulty circuit signatures fall outside the good circuit signature range. If the good and faulty circuit signature distributions were to overlap, then the fault would be potentially detected with the probability of detection proportional to the percentage of faulty circuit signatures that lie outside the good circuit signature range [Stroud 2002].
Fourier analysis can be used to determine an analog signal’s frequency content. Similarly, discrete Fourier transform (DFT) or fast Fourier transform (FFT) techniques can be used to determine the frequency response of discretely sampled analog signals. This section describes an FFT technique for testing analog components in a mixed-signal system.
An ADC can be used to sample an analog signal and produce a quantized version of the signal value at a discrete instant of time. The N-point DFT operation can be used to determine the frequency, or spectral, content of an N-element series of discretely (in-time) sampled signal values. The DFT operation is based on the following equation:
where the output X[k] is the complex value of the DFT at digital spectral frequency k, x[n] is the complex value of the input signal at discrete time n, N is the total number of input signal points, and WN = e–j2π/N is a complex function of N. Figure 15.17 shows an example of a quantized, discretely sampled sinusoidal time domain signal and the magnitude of its spectrum appears at its frequency illustrated in Figure 15.18 as calculated by the DFT. This relationship is key to spectral-based FFT analysis and signal generation.
To calculate the complex spectral frequency values of X[k] using Equation (15.34) requires N complex multiplications and various other complex operations. Using Equation (15.34) to calculate the values for a series of M spectral frequencies will require O(M · N) complex operations (multiplications, additions, and subtractions). Often the value of M and N are the same, and the required complex operations reduces to O(N2). Cooley and Tukey developed the N-point FFT to eliminate duplicate complex operations and reduce the complexity to O(Nlog2N) [Cooley 1965]. Figure 15.19 illustrates two equivalent symbolic representations of the butterfly processor, which is the basic processing component of the FFT algorithm. The butterfly has three complex inputs and two complex outputs. The twiddle factor Wi is a function of WN from Equation (15.34) as well as its location in the butterfly processing network, namely, 
. Figure 15.20 shows an example how an 8-point FFT is performed using a butterfly processing network.
The inverse fast Fourier Transform (IFFT) operation is important to the FFT-based TPG and is based on the inverse discrete Fourier transform (IDFT) expressed as:
where the output x[n] is the complex value of the IFFT at discrete time n, X[k] is the complex spectrum at digital frequency k, and N is the total number of spectral frequency values for the IDFT equation. By applying the IDFT operation to the spectrum shown in Figure 15.18, the original signal can be recovered as in Figure 15.17. Similar to the FFT, the IFFT also reduces the time complexity of the IDFT to O(Nlog2N).
Figure 15.21 shows the architecture for the FFT-based mixed-signal BIST approach where the digital TPG generates an m-bit digital test pattern. This test pattern is converted into an analog test signal by the DAC to stimulate the DUT. On the ORA side, the analog output of DUT is sent to the ADC and converted to an n-bit digital signal that is collected and analyzed by the digital ORA circuitry. The core component of the system is the digital TPG and ORA circuitry.
The test controller sets the modes of operation and test to be performed, and handles test sequencing. It also controls the FFT processing block working in either TPG mode or ORA mode. The explicit connections for the controller are not shown in the figure.
In the TPG mode, the FFT-based signal generator/analyzer block performs the IFFT operation to create a coherent, multitone digital test signal, which is then loaded into the parallel load circular shift register with N words of m-bit resolution. Once the register is loaded with a coherent, multitone signal, the test control circuitry puts the register in shift mode, such that every clock cycle an m-bit digital test signal is shifted out to the DAC to generate the analog test stimuli and, at the same time, circularly shifted in the other side of the register.
In the ORA mode, the serial load parallel output shift register (with N words of n-bit resolution) locks in N samples of the digital test response signal from the ADC. These N samples are then used to perform the spectral analysis with the FFT operation by the FFT-based signal generator/analyzer block. Analysis of the spectral content of the sampled test response signal provides a wealth of information on the health of the analog circuit under test.
For analog component ORA the FFT-based signal generator/analysis module is set to FFT mode to determine the frequency content of an analog signal. Typically, the input to the ORA comes from an ADC that is sampling the analog signal at frequency fs, and the time delay between sampled points (sampling period) is Ts = 1/fs. In this case, the imaginary part of each of the N complex inputs of the FFT is set to zero, so the N discrete inputs to the FFT are all real. The frequency bandwidth (BW) covered by the FFT is a function of the sampling frequency, fs, of the ADC, and Nyquist defines the base BW of the FFT as BW = fs/2. For a discrete N-point FFT the frequency spectrum is divided into N discrete frequencies or spectral bins. The FFT calculates a complex value for each spectral bin. The value in each bin represents how much signal is present in the frequency range for that bin. Each spectral bin k (where k ∊ {0, 1, 2, ... N/2 – 1}) has a frequency range k · fs/N– fs/N/2 ≤ fk · ≤ k · fs/N + fs/N/2. For real valued inputs, the values in the upper N/2 out of the N spectral bins are the complex conjugates of the values in the lower N/2 spectral bins. So usually, only the complex values in the lower N/2 out of N spectral bins are calculated. With this information the frequency resolution or the width of each spectral bin, fs/N, can be determined. The frequency resolution can be improved by increasing the number of points in the FFT calculations. For example, if fs = 1 GHz and N = 256, then the base BW is fs/2 = 500 MHz and the frequency resolution is fs/N ≅ 3.91 MHz. To improve frequency resolution N can be increased to 512 and the frequency resolution becomes fs/N ≅ 1.95 MHz.
Spectral-based techniques allow use of relative signal values, such that accuracy of the signal source and measurement devices is not as critical as it is with absolute measurement techniques. These test techniques can be used to measure parameters like SNR, gain-tracking, frequency response, distortion, and group delay, and, as a result, apply to most processing type of analog components (such as filters, amps, etc.). Therefore, many spectral tests can be performed using the FFT-based BIST approach as follows.
FFT-based BIST can be used to measure a circuit’s SNR. Hardware can be saved by eliminating the need for the square root function required to determine the actual magnitude; however, the resultant values will have a wider variation.
By controlling the magnitude of the input signal, FFT-based BIST can be used to determine the gain, G = So/Si, where So is the output signal magnitude, and Si is the input signal magnitude. The input signal, Si, is generated at some frequency of interest, f. The magnitude of So is measured as the input signal magnitude, Si, is increased. The spectral components of the output signal are used for gain comparison.
By using a single tone input signal whose frequency, f, is swept across a range of frequencies or a multitone input signal with frequencies f1, f2,..., fn, the circuit’s frequency response can be measured. Using a multitone signal can save test time by eliminating the multiple runs required for a frequency sweep.
IMD tests are particularly well suited for the FFT-based technique. Using a two-tone input signal with frequencies f1 and f2, an analog component’s IMD products, as shown in Figure 15.4 can be determined using spectral components of the output signal So. Group delay can also be determined using a two-tone test. By processing the real and imaginary components in two separate spectral bins at different points in time, the phase change, Δφ, can be calculated. The group delay can then be calculated using Δφ/Δf.
The architecture presented in this section makes use of the FFT not only for signal analysis but also for on-chip multitone signal generation [Emmert 2003, 2005, 2006]. For digital systems, the on-chip implementation of an FFT circuit can be costly relative to circuit area or data processing time; however, many mixed-signal circuits (especially for DSP applications) already have an FFT function available. Even if the FFT is not available, there are many robust approximation techniques that minimize the area overhead required for on-chip implementation. The rest of the section describes FFT-based multitone signal generation for on-chip BIST applications.
The basis for the FFT-based signal generation is the IFFT operation, which can be realized with the same functional block for FFT operation. Comparing Equation (15.34) and Equation (15.35), there are two differences between FFT and IFFT. The first difference is the scaling factor 1/N in front of the summation, and the second difference is a minus sign in the exponent of the kernel function. In fixed-point arithmetic, the scaling factor can be fulfilled with a log2N right shift of the bits and no extra hardware is required. For the second difference, it should be noted that all FFT (or IFFT) kernel points are equally spaced around the complex unit circle. It does not matter if we go clockwise or counter clockwise around the complex circle; we end up with the same points. So the extra minus sign for signal generation can be ignored. Therefore, the exact same FFT block can be used to perform the IFFT operation for signal generation as well.
To generate a multitone signal with j-tones, a series of j complex values with magnitude of 1 is created. It should be noted that this value of 1 is arbitrary, and to change the relative contribution of a tone to the overall signal, its relative magnitude in the series can be varied. Additionally, the phases of different tones can be controlled by real and imaginary parts of each of the j complex values.
Next, an N-element complex series is created with every element initialized to 0. Depending on the actual frequency bins of the j tones, the corresponding elements of the series are then assigned with the other series given in the previous section and used as input to the FFT for signal generation. Figure 15.22 shows examples of the real and imaginary inputs as well as the resulting digitized signal for a j = two-tone setting with frequencies at bin 1 and bin 4. Because a digitized j-tone signal repeats itself every period, it can be loaded into a fast circular shift register to create continuous high-speed digitized test stimuli. Once this is done, the FFT is free to process the digitized output of the analog circuit under test in ORA mode.
Figure 15.23 shows an example coherent signal generated using frequencies corresponding to spectral bins 4 and 12. The generated two-tone digital test signal is suitable for loading into the high-speed TPG register. As the signal wraps around, the coherent ends match up. If the DAC clock frequency is set to 1 GHz, a continuous signal with frequencies 15.63 MHz and 46.88 MHz is produced.
Direct digital synthesis (DDS) is an important frequency synthesis technique that provides low-cost waveform generation with ultrafine resolution. As shown in Figure 15.24, a conventional DDS includes a digital accumulator that generates the phase word based on the input frequency word. The synthesizer step size is defined as fclk/2n where n is the number of bits in the accumulator. Fine resolution can thus be achieved using a large accumulator size. The DDS utilizes a lookup table (LUT) to convert the phase word to a sinusoidal amplitude word, whose length is normally limited by the finite number of input bits of the DAC. Deglitch filters are added after the DAC to remove the spurious components generated in the data conversion process. Although a pure sinusoidal waveform is desired at the DDS output, spurious tones can occur mainly because of the following two nonlinear processes. First, to reduce the read-only memory (ROM) size of the LUT, the phase word needs to be truncated before being used as the ROM address. This truncation process introduces quantization noise, which can be modeled as a linear additive noise to the phase of the sinusoidal wave. Second, the ROM word length is normally limited by the finite number of bits of the available DAC. In other words, the sinusoidal waveform can be expressed only by words with finite length, which intrinsically contains quantization error additive to the output amplitude. In the case of DDS, the quantization errors are caused by finite phase resolution, ep, and finite amplitude resolution, eA, where eA is the same as e in Section 15.2.4. For ep, oversampling is employed in DDS, allowing noise-shaping techniques to be used to shift the phase quantization error to a higher frequency band where the noise can be removed by the deglitch filter after the DAC [Dai 2004]. Assuming ep is small relative to the phase, the DDS output can be determined as:
Analog functional testing requires fine frequency resolution and fast frequency switching time to perform tests such as frequency response and linearity measurements. The resolution and switching speed requirements of an analog BIST system surpass the performance capabilities of conventional analog PLLs. The conventional PLL-based frequency synthesizer has difficulty meeting these requirements because of internal loop delay, low resolution, and limited tuning range of the VCO. In contrast, DDS generates a digitized waveform of a given frequency by accumulating phase changes at a higher clock frequency. Because there is no feedback in a DDS structure, it is capable of extremely fast frequency switching or hopping at the speed of the clock frequency. DDS provides many other advantages including fine frequency-tuning resolution, continuous-phase switching, and various modulations. Thus, it provides a low-cost digital approach to frequency, phase, and amplitude modulations, eliminating the costly analog modulators associated with many analog measurements. The modulated waveform generation is a unique feature of the DDS-based BIST approach.
On the other hand, the DDS has two major deficiencies that are related to the inadequacy of the semiconductor technology. The first deficiency is that the output spectrum of the DDS is normally not as clean as the PLL output. The DDS quantization noise floor is limited by the finite number of amplitude bits (DAC input bits) and the finite number of phase bits. A 12-bit DAC provides a theoretical SNR of 72 dB, which is less than that of a typical PLL synthesizer. The DDS also suffers from a high level of spurious output, derived from the discrete phase accumulation and phase truncation processes as well as the DAC nonlinearity. The second deficiency is that the DDS output frequency is limited by the maximum operation frequency of the DAC and the digital logic. Although DACs with GHz sampling frequencies have been reported, they normally consume a large amount of power with poor resolution. Therefore, the DDS can be used to generate the fine-tuned frequency followed by a RF mixer and PLL used to up-convert the DDS output to the RF frequency. With careful design, the best of both DDS and PLL can be achieved [Dai 2006b].
The complete DDS-based BIST architecture is illustrated in Figure 15.25 [Dai 2006a]. The TPG provides precise frequency tone sweeps by controlling the frequency word. It can also generate quadrature phase sinusoidal waveforms simultaneously by shifting the two MSBs of the phase word. As we will show, the DDS can be used to generate the two-tone test stimuli required for IP3 measurements. The area penalty associated with the DDS approach is minimized by the delta-sigma noise shaping scheme [Dai 2006b].
The DDS-based TPG consists of three numerically controlled oscillators (NCOs) and utilizes the existing DAC from the mixed-signal system to complete the DDS. Figure 15.26 gives a more detailed view of the NCO implementation used in the TPG. The phase accumulator is used to generate the phase word based on the frequency word f and the initial phase word θ. The NCO then utilizes a LUT to convert the truncated phase word sequence to a digital sine wave sequence where the output sine wave frequency is determined as:
where n is the word width of the phase accumulator. The phase truncation noise introduced in the NCO can be reduced using a sigma-delta modulator. The BIST system shown in Figure 15.25 requires three NCOs to generate three test tones. To save area, the sine LUT of three NCOs can be shared by time-multiplexing the LUT input and output. Thus, three NCOs contain only three phase accumulators and one sine LUT. It should be noted that the sine LUT consumes the majority of the NCO area.
The ORA incorporates two multiplier/accumulators, each consisting of a D-bit multiplier (where D is the number of bits from the ADC) and a 2D + M-bit accumulator (where the number of samples to be accumulated is less than 2M. A 2’s complement transformation is performed on negative numbers entering the accumulators, Accum1 and Accum2, such that subtraction is accomplished by the adders in the accumulators. In addition, the DDS input to the two multipliers is converted to a signed magnitude number to remove any DC offset from the DDS output that could affect the accuracy of the measurement. The multipliers in the ORA serve as down-converters to selectively pick the frequency components and down-convert them into DC signals. The DC levels are then compacted by the accumulators for evaluation during various tests and measurements as described in the following subsections.
One of the major problems associated with integrated analog filters is the cutoff frequency variation caused by temperature, supply voltage, and process variations. If the cutoff frequency can be monitored on the fly during transmission idle periods, its variation can be compensated using built-in tunable circuitry in LPF designs. In addition to production testing, the frequency response monitoring can also be used to adjust the gain and bandwidth of the amplifier for multiband and multistandard applications. With wireless standards operating in very different frequency bands, market-leading wireless solutions have to offer multimode interoperability with transparent worldwide usage. Thus, the base-band gain stage needs to be tunable for different wireless standards. A DDS-based BIST approach can be used to calibrate the frequency response of the base-band gain stage and LPF in this connection.
Frequency response (both gain and phase response) is the key measure for integrated LPFs and amplifiers. The cutoff frequency of the filters and amplifiers can be found by measuring the passband and stopband amplitude response, whereas the group delay can be determined from the phase response. To test the base-band LPF in a transceiver RFIC, the DDS integrated in the base-band ASIC generates a single frequency tone that loops back from transmitter to receiver through multiplexer controls. The DDS generates frequency tones with fine resolution and can scan the pass and stop bands of the LPF with fine step size to measure the cutoff frequency, pass band, and stop-band ripples of the filter. However, there is normally a phase difference between the external path through the DUT and the internal path from the test generator to the test analyzer, so phase correction needs to be done before the frequency magnitude measurement.
To measure the frequency response, the DDS generates the test tone of x(t) = A cos ωt that is applied to the input of an amplifier with transfer function y(t) = [α0 + α1x(t) + α2x2(t) + α3x3(t) + ...]|exp(jΔφ)|, where Δφ denotes the phase delay through the amplifier and the coefficients αj are time invariant. Hence, the amplifier output is given by:
Note that if the input signal A is large, the nth harmonic grows approximately in proportion to An. Under a small-signal assumption, for example, the input signal A is small, the system is linear, the harmonics are negligible, and the small-signal gain is α1. For a large signal, nonlinearity becomes evident and the large-signal gain is α1 + ¾(α3A3, which varies when the input level changes. If α3 < 0, the output is a “compressive” or “saturating” function of the input signal, namely, the gain is compressed when the input magnitude A increases. For a small input, the linear transfer function of the DUT is:
In the ORA, the amplifier output is mixed (multiplied) with the test frequency. Assume the test tone to be mixed with the DUT output response being of the form Acos(ωt). Accumulating the mixer output, we can obtain a DC term given as follows:
where n is the number of accumulation clock cycles, and Δϕ is the phase difference between the external and internal path. The amplifier output is also mixed (multiplied) with a test tone of Asin(ωt). This mixing process produces another DC term:
Thus, the phase difference Δφ can be determined by:
Once the phase difference is measured, the test tone generated by DDS for the frequency response can be phase-adjusted such that the signals at the mixer inputs can be perfectly in-phase. In this connection, DDS should generate test tones in the form of x(t) = Acos(ωt) for the DUT and Acos(ωt-Δφ) for the mixer input in the ORA, respectively. Additional phase can be easily added to the phase word in the DDS architecture as shown in Figure 15.26. The amplifier may not have a constant group delay, namely, the delay through the DUT is normally frequency dependent, and therefore the phase correction should be performed at each frequency step when DDS generates the test tones that scan the interested band.
Figure 15.27a shows the ORA accumulated DC1 component of the DUT output mixed with Acos(ωt), and Figure 15.27b shows the ORA accumulated DC2 component of the DUT output mixed with Asin(ωt). In both cases, the phase difference Δφ = 135°. Notice the slope of DC1 is negative because of the cosΔφ term in Equation (15.40), whereas the slope of DC2 is positive because of the sinΔφ term in Equation (15.41). Based on the sign of DC1 and DC2, we can thus determine the quadrant of the phase difference. Once the phase difference is determined, the actual phase corrected frequency response can be found from either of the DC1 or DC2 measurements as:
Figure 15.27. Accumulated DC1 and DC2 components for Δφ = 135°: (a) DC1 output mixed with Acos (ωt) and (b) DC2 output mixed with Asin (ωt).
For better accuracy, the DC term with the larger slope is used for calculations. For certain phase differences such as angles close to a multiple of 90°, one of the DC terms will approach zero. In those cases, the relative phase difference Δφ can be adjusted by the desired phase delay θ at the input to the DDS as shown in Figure 15.26.
For linearity measurements with this BIST approach, the following technique is used for the ORA. As Figure 15.4 shows, the closest intermodulation terms to the fundamental are the IM3 terms with frequencies at 2ω1 – ω2 and 2ω2 – ω1. First, mixing (multiplying) the amplifier output with fundamental tone A2cosω2t, produces a DC term:
where the second term 
is normally much smaller than the linear gain, α1, if the input level is small, such that the amplifier is not desensitized. Second, mixing (multiplying) the amplifier output with the IM3 tone A1cos(2ω2 – ω1)t, produces another DC term:
Expressing these two DC terms in dB, the difference, ΔP, between the fundamental and the IM3, and thus the IIP3, can be measured using Equation (15.3). Although we can represent dB units using floating-point format, it is not necessary to find the actual IP3 value using real hardware in the ORA for a BIST implementation. Instead, ranges of acceptable values can be precalculated and compared to DC1 and DC2 values for a pass-fail BIST indication. For characterization of the circuit, the accumulated values can be read and averaged off-chip to perform the actual IP3 calculation. The complete TPG and ORA for the linearity BIST architecture are illustrated in Figure 15.25. It should be noted that the BIST circuitry for frequency response measurement is a subset of that required for linearity measurement.
For SNR and noise figure measurements, all three DDSs illustrated in Figure 15.25 are used, but these measurements use a subset of the circuitry of the linearity measurement circuitry, as the adder is not needed to superimpose the two test tones. During this measurement, NCO1 produces a constant test waveform at frequency f1. The resultant sine wave, sin(f1), is applied to the DUT for the entire test. The other two DDSs are used to produce a sine wave and cosine wave at frequency f, similar to the frequency response measurement described previously. The output response of the DUT y(t) is multiplied by both sin(f) and cos(f) in the multipliers Mult1 and Mult2, respectively. Then the outputs of the multipliers are accumulated in Accum1 and Accum2 to extract DC1 and DC2, respectively. The phase and gain of y(t) with respect to sin(f) is then calculated by the same method as in the frequency response measurement. Again, phase and gain are measured at the same time for frequency f, as DC1 and DC2 are extracted simultaneously. This gives the amplitude of the noise produced in the system at frequency f. To obtain the complete signal-to-noise ratio, a series of phase and gain measurements is made by changing the value of f during each measurement such that we sweep through the various frequencies (excluding frequency f1), averaging the measured noise. A phase and gain measurement is made at frequency f1 in order to obtain the gain of the signal at frequency f1 with the final SNR obtained by dividing the gain of the signal by the average of the noise.
Although analog ICs and the analog portion of mixed-signal ICs consist of fewer components compared to their digital counterparts, testing analog and mixed-signal devices is more complex regardless of whether the testing approach is specification oriented or defect oriented. This chapter has presented some of the important distinctions between these two approaches and some of the fundamental tests that are applied to analog circuits. In addition, this chapter has presented some representative BIST techniques that have been developed for both functional and structural testing that can be incorporated in mixed-signal IC and SOC implementations to test analog modules. Because the incorporation of BIST circuitry incurs area and associated cost penalties, there are many applications, such as low-cost consumer electronics, in which it may not be worthwhile to consider BIST. On the other hand, high-reliability applications, such as space and medical electronics, are excellent candidates for the incorporation of BIST techniques.
The implementation and operation of the BIST approaches presented in this chapter provide insight into many of the issues that must also be considered for more traditional, non-BIST approaches to analog testing. DSP and FFT-based approaches provide a wealth of test and measurement capabilities and form the core of spectrum analyzers, which, in turn, are a key component of external testing. For SOC implementations, incorporation of an FFT can be costly in terms of area, particularly for high-resolution frequency discrimination. However, when incorporated in an SOC for DSP system applications, not only can the FFT be used for output response analysis, but it can also be extended to test pattern generation during functional testing. The DDS-based approach with multiplier/accumulator ORA provides a considerable reduction area overhead at the expense of test time, as only one frequency component of the analog output response can be analyzed at a time. Otherwise, the FFT and DDS approaches provide similar functional test and measurement capabilities. One of the major advantages of functional testing over structural testing is the ability to calibrate and compensate analog circuit performance in addition to fault detection.
15.1 | (Analog Functional Testing) An amplifier operates at 2 GHz with a gain of 10 dB. A two-tone test with equal power is applied at the input; one is at 2 GHz and another is at 2.01 GHz. At the output, four tones are observed at 1.99, 2.0, 2.01, and 2.02 GHz. The power levels of the tones are –70, –20, –20, and –70 dBm. Determine the IIP3 and 1-dB compression point for this amplifier using the two-tone test. |
15.2 | (Analog Functional Testing) A sampled system samples a 4 MHz video signal with an 8-bit video ADC with sampling clock at 32 MHz. Determine the oversampling ratio and the system SNR. |
15.3 | (Defect-Oriented BIST Output Response Analysis) Assuming an N-bit ADC and an M-bit accumulator for the ORA, what is the maximum number of BIST clock cycles that can be applied without the possibility of accumulator rollover? |
15.4 | (FFT BIST Signal Analysis) Given an ADC with sampling frequency, fsampling = 250 MHz and a 256-point FFT, what is the frequency resolution for FFT based signal analysis? |
15.5 | (FFT BIST Signal Analysis) Given an ADC with sampling frequency, fsampling = 1 GHz, a 256-point FFT, and output peak signal frequency at 125 MHz, what spectral bin should the output test signal fall into? |
15.6 | (FFT BIST Signal Generation) Given a high-speed circular shift register and DAC combination running at fCLK = 100 MHz and a 256-point IFFT block, determine which spectral bin numbers to set to nonzero values to create a two-tone analog test signal with frequencies of approximately 5 MHz and 13 MHz. |
15.7 | (DDS BIST Phase Delay) Show that the accumulator values given in Figure 15.27 result in a phase delay measurement of Δφ = 135°. |
15.8 | (DDS BIST Gain Measurement) Determine the corrected gain for the frequency response from either DC1 or DC2in Figure 15.27. |
The authors wish to acknowledge Professor John (Marty) Emmert of Wright State University, Department of Electrical Engineering, for contributing the section on FFT-Based Mixed-Signal BIST, as well as Professor Robert Dean and Jie Qin of Auburn University, Department of Electrical and Computer Engineering, for their assistance during preparation of this chapter.