The most commonly used GC I/O architecture is shown in Figure 14.1. In this architecture, the signal is launched off one chip with the system clock and received at another chip at the following clock edge. At the sending end, there is a clock to signal delay (T_co) specification, and at the receiving end, there is setup (T_setup) and hold time (T_hold) on either side of the following clock edge.

Figure 14.1. Global clock (GC) data and clock timing relationship.

As the signaling rate increases, a problem arises. The clock skew between the sending component and the receiving component (board trace delay A-B shown in Figure 14.2) can cut into the cycle time. To compensate for this clock skew, the source synchronous (SS) architecture was developed [Ilkbahar 2001]. With this scheme, not only will the sending component send the signal, but also another strobe that is similar to a clock signal goes along with that signal. The receiving component uses this strobe to clock the signal. Hence, system-level clock skew is out of the picture. The designer only cares about the differential skew between the strobe and the signal, with the key timing specifications as the time valid before (the strobe) and time valid after (the strobe) (see Figure 14.3). With careful design, (e.g., identically sized drivers and matched layout), this signaling scheme allows the signaling rate to increase gradually from less than 10 to 50 Mbps to today’s 1066 Mbps.

Figure 14.2. Source synchronous (SS) signaling scheme.

Figure 14.3. SS timing definition.

As much as this new SS signaling scheme has improved system-level performance, another problem starts to show up when the data rate continues to increase. The parallel interface that we use to transfer lots of data becomes a bottleneck itself. The parallel bits of data from the sending/receiving component have to center around the strobes. The skews among these data bits caused by uneven driving speeds and propagation delays between parallel channels become a performance limitation (see Figure 14.3). Additionally, the multiple load nature of a parallel bus creates noises that also affect signal integrity (SI). Each of these loads can be considered a stub on the transmission line. Because the stub is never perfectly matched to the transmission line characteristics, some of the energy would be reflected and is superimposed on the signal, making it noisier. It is generally believed that beyond 1 Gbps, new signaling technology is required. One may still use SS or similar architectures such as hypertransport with higher data rate, but the number of loads has to be decreased correspondingly to minimize disruption to the transmission line characteristics.

Another solution to extend SS is to reduce the number of data bits per strobe or, in other words, provide more strobes for a wide data bus. This will increase the number of board traces or wires and is not economically feasible. This can continue up to the point where we need a strobe with a data bit; then there will not be data skew, but then we also expand the size of the bus to double.

As pointed out earlier, at a data rate beyond 1 Gbps, we have to treat each data channel individually because of the possible skews among data channels. One solution is to apply a serial signaling technique whereby the clock is embedded in its transmitting data stream. At the receive side, this clock is recovered through a CR circuit. PLL circuits are commonly used for clock recovery, but there also exist other digital circuit techniques for this task. Figure 14.4 illustrates the block diagram of a serial link with a CR circuit placed on the receive side.

Figure 14.4. Serial link using embedded clock signal scheme.

One may wonder: how does the clock get embedded into the data? The clock is periodic, but data are not. In other words, natural digital data do not resemble the clock. How would the clock recovery scheme work? The trick here is to make the data look more like a clock. By mapping a data word (e.g., 8 bits) onto another codeword (e.g., 10 bits), and only mapping to those with an even number of transitions (i.e., more or less an equal number of 1’s and 0’s, or DC balanced coding), the data stream will look more like a clock stream and the PLL at the receiver end can periodically synchronize to some of the transitions while it regenerates the clock.

In a serial embedded clock I/O link system, jitter is the dominant cause for performance degradation. Therefore, to recover the clock at the receiver, the PLL attempts to track the jitter to mitigate jitter’s negative impact on the receiver performance. To characterize the PLL in terms of its performance for tracking jitter, as well as to quantify the jitter “propagation” process from the transmitter to the receiver, some system transfer function concepts, such as linear time-invariant (LTI) system theory [Papoulis 1977] [Oppenheim 1996], must be incorporated. In an LTI system, its output signal can be determined by the convolution of its input and the impulse response of the system.

In the following, we start with the definition of various jitter components and their interaction hierarchy. Then, we describe how to separate jitter components, an important and practical topic in jitter testing and analysis. Finally, we discuss the extension of the jitter component concept and the separation methods for noise component analysis, and the interactions between jitter, noise, and BER.

Jitter Components

A popular and widely used definition for so-called phase jitter or accumulated jitter states that jitter is the time deviation of an edge transition from its ideal time location [Li 2004] [PCI-SIG 2004]. Phase jitter results from several sources of noise and thus it is desirable to classify jitter into components such that each of them can be attributed to a distinct process or an underlying mechanism causing the jitter. The tree given in Figure 14.5 illustrates the classification scheme of various jitter components and their relationships [Li 2000] [NCITS 2001].

Figure 14.5. Classification of various jitter components.

Jitter or total jitter (TJ) can be separated into two major components: deterministic jitter (DJ) and random jitter (RJ). DJ’s probability density function (PDF) is bounded, whereas RJ’s PDF is Gaussian and unbounded. DJ can be further separated into three types: data-dependent jitter (DDJ), periodic jitter (PJ), and bounded-uncorrelated jitter (BUJ). RJ includes Gaussian jitter (GJ) and multiple Gaussian jitter (MGJ). There are two types of DDJ: duty cycle distortion (DCD) and intersymbol interference (ISI). Figure 14.6 shows the various jitter components and their associated PDFs in the context of an eye diagram.

Figure 14.6. Various jitter components and their associated PDFs.

Another means of classifying jitter is based on whether the jitter correlates to the data pattern or not: correlated jitter and uncorrelated jitter. Correlated jitter types include DDJ, DCD, and ISI, and uncorrelated jitter types include PJ, BUJ, MGJ, and GJ. This particular means of classifying jitter components offers additional insights to the jitter processes and enables development of better quantification methods.

Each jitter component has specific physical mechanisms and root causes associated with it. For DJ components, DCD can be caused by a reference voltage offset or a time delay between the rising and falling clock edges when it is digitally synthesized. ISI results from interaction between successive data bits. These data bits form an analog waveform with rich high-frequency components. As the waveform transverses through lossy and band-limiting materials (e.g., PCB traces), energy at some specific frequencies may be attenuated, resulting in data-dependent variation; hence the term ISI. PJ can be caused by periodic modulations or interferences. BUJ can be caused by crosstalk. RJ can be caused by thermal, flicker, or shot noises. Knowing the amount of each jitter component provides valuable diagnostic information for finding and, in turn, fixing a specific jitter failure problem.

Jitter Separation

There are two major approaches to separating individual jitter components. One method is based on the jitter PDF (see Figure 14.7) or cumulative distribution function (CDF) (see Figure 14.8) measurement. PDF is the normalized histogram of the signal edge times (i.e., how often the signal transitions at a particular time point). CDF, on the other hand, sorts the sampled edge time data in an ascending order to show the distribution profile. Another method is based on the jitter time record. Jitter PDF can be measured by instruments such as the sampling oscilloscope (SO) or time interval analyzer (TIA). Jitter CDF (sometimes called BER CDF) can be measured by a bit-error-rate tester (BERT). The jitter time record can be measured by a TIA or a real-time oscilloscope (RTO).

Figure 14.7. Jitter probability density function (PDF).

Figure 14.8. Jitter cumulative distribution function (CDF).

Jitter Separation Based on Statistical PDF or CDF

A widely accepted method for conducting PDF-based jitter separation is the Tailfit method [Li 1999]. Because the deterministic PDF is bounded, beyond certain jitter limit or the range of DJ, all the PDF-based jitter will be random jitter. Random jitter is naturally modeled by a Gaussian function (bell-shaped distribution). Therefore, the tail of a jitter PDF reflects the random jitter process, which, in general should be a Gaussian-type distribution. The Tailfit algorithm identifies a Gaussian curve with a symmetrical tail region to that of the distribution under evaluation. Two Gaussian curves (left and right side of the PDF) are fitted against each of the tail regions of the distribution until optimal matches are found. When an analytical Gaussian model is used to match those measured tail region PDFs through nonlinear fit or other optimization procedures, all the parameters defining a Gaussian distribution such as mean and RMS can be determined. Then the DJ PK-PK can be estimated as the difference between two means, and RJ σ (or RMS) will be the average of two tail σs. The application of the Tailfit method to a total jitter PDF is shown schematically in Figure 14.9.

Figure 14.9. Fitting Gaussian distribution curves to a jitter histogram Tailfit.

The Tailfit method can be applied to a BER CDF if it is directly measured via instrument such as a BERT. In general, the mechanism is similar to that used in PDF fitting. However, because the base data are CDF, the model used to fit the tail region of the CDF should be an integrated Gaussian, which represents an error function [Hänsel 2004]. Also, the left tail of PDF corresponds to the right tail of the CDF. Similarly, the right tail of PDF corresponds to the left tail of the CDF. Tailfit for BER CDF is shown in Figure 14.10.

Figure 14.10. Tailfit for BER CDF.

It could be hard to extract some second- or third-level DJ components shown in Figure 14.5, such as DCD, ISI, PJ, and DDJ, from the jitter PDF or CDF data. The reason is that the features and characteristics of those jitter components are “washed out” because of the summing and integration in deriving the PDF and CDF distributions.

In addition to separating jitter to its DJ and RJ components, Tailfit is used to estimate or extrapolate total jitter (TJ) with smaller measurement sample size or time. TJ is defined as the timing closure at a low BER level (10^–12 or lower for most of the high-speed I/Os) on the BER CDF curve (see Figure 14.10). TJ can be determined based on direct measurement of BER CDF down to 10^–12, but such method is time consuming and slow. With the Tailfit method, BER CDF at a low BER level (e.g., 10^–12 or lower) can be estimated or extrapolated from a higher BER level (e.g., 10^–6 or higher) with smaller sample size, enabling TJ estimation at the low BER level with fast throughput.

Jitter Separation Based on Frequency Spectrum

If a data stream is repeatedly sampled and captured in the time-domain via instruments such as TIA or RTO, then spectrum analysis can be carried out via time to frequency domain transformations such as Fourier transformation (FT). The mainstream methods for spectrum analysis of a stochastic process such as RJ include the autocorrelation method (for the time domain) and the power spectrum density (PSD) method (for the frequency domain) [Papoulis 1977] [Oppenheim 1996]. In [Wilstrup 1998], these two methods were first applied for jitter separation in the time and frequency domains, respectively. In these methods, repeated sampling of time deviations from the ideal locations produces a distribution of both DCD and ISI, whereas the variance function in the frequency domain results in a jitter PSD for PJ and RJ, which is uncorrelated to the data patterns. An exemplar jitter PSD function having both PJ and RJ is shown in Figure 14.11.

Figure 14.11. An exemplar plot of jitter power spectrum density (PSD).

PJ components will be shown as spectral lines in the PSD function, and a sliding window technique can be used to identify the magnitude and frequency for each of the PJ components. Then, all PJ spectral lines are removed from the PSD function record. The residues can then be summed over a frequency band and the square root of the sum gives the RMS value of the RJ over that frequency band. Another similar jitter separation method—which employs undersampling, targets production testing, and measures the means of the edge transition times—has been developed by [Cai 2005].

A less accurate jitter estimation method using voltage time records can be accomplished by applying direct Fourier transform (FT) or fast Fourier transform (FFT) operation to convert the interpolated jitter time record (which is not a directly measured jitter time record) to its frequency domain spectrum. The data can then be squared to derive an approximated PSD [Ward 2004]. Unlike the spectrum shown in Figure 14.11, all jitter components, including the DJs, will show up in the PSD derived by this direct FFT approach. The DJs will appear as spectral lines as well. Therefore, if there is a PJ component whose frequency is an integer fraction of the pattern repeating frequency, then PJ and DDJ can no longer be separated. Similarly, this method will also introduce inaccuracy in the RJ estimation [Davenport 1987].

Jitter, Noise, and Bit-Error-Rate Interactions

A bit error can be caused by either timing jitter or amplitude noise, or both. An exemplar eye diagram degraded by both timing jitter and amplitude noise is shown in Figure 14.12. If both timing jitter and amplitude noise are considered for estimating the BER, then the BER CDF will become a two-dimensional (2-D) function. At 0.5 UI of the eye diagram, the noise PDF will contribute to the BER CDF in a manner similar to that of the timing jitter at zero-cross voltage. A 2-D jitter and noise PDF can be measured by a SO or RTO. Although a BERT can measure the 2-D BER CDF, the test time will be very long (several hours, typically) for BER measurement at the 10^–12 level. Figure 14.12 shows an eye diagram in which the associated jitter and noise PDFs are highlighted.

Figure 14.12. A distorted eye diagram caused by timing jitter and amplitude noise.

Receiver Jitter Transfer Function

It is well known that a PLL [Gardner 1979] [Best 1999] has certain frequency response characteristics. Therefore, when a receiver uses a PLL to recover the clock and then to time/retime the received data, the jitter that the receiver “sees” will follow those certain frequency characteristics as well. Any good simulation or test methodology should emulate the actual system/device behavior. In the case of jitter output/receiver jitter input determination, the model setup for both design and test should be such that it determines the jitter specifically as what a receiver sees in the link system [Li 2003, 2004]. A receiver sees jitter on the data from its recovered clock; therefore it is a difference function from clock to data as shown in Figure 14.13.

Figure 14.13. A receiver jitter model.

Because the clock recovery circuits (e.g., PLL) typically have a low-pass transfer function H_L(s), the jitter output will have a high-pass transfer function of H_H(s) as shown in Figure 14.14. This is because H_H(s) = 1–H_L(s), assuming that there is no phase delay between data and clock.

Figure 14.14. Receiver jitter transfer function.

Receiver Jitter Tolerance Function

The high-pass jitter magnitude transfer function |H_H(s)| shown in Figure 14.15 suggests that a receiver is able to track or attenuate more low-frequency jitter at f < fc than at a higher frequency of f > fc·fc is the corner frequency below which the transfer function magnitude begins to decrease and above which it maintains a constant. This implies that a receiver can tolerate more low-frequency jitter than high-frequency jitter for a given BER performance goal. Therefore, the jitter tolerance function is the “mirror” function of the jitter transfer function around the unity gain, as shown in Figure 14.15. The higher the corner frequency (f_c) is, the better the jitter tolerance capability will be. Similarly, the steeper the jitter transfer function slope is, the better the jitter tolerance capability will be. The corner frequency (f_c) is typically defined as the data rate divided by 1667 for data communication standards such as FC. For example, when the data rate is 2.5 Gbps, the corner frequency fc is 1.5MHz (2.5GHz/1667), whereas the number 1667 is inherited from the early SONET standard and is related to the PLL phase track speed capability. Note that jitter transfer function determines the receiver jitter tolerance.

Figure 14.15. Receiver jitter tolerance function.

Obviously, the slope for the jitter transfer function k_tra and the slope k_tor for the jitter tolerance function both satisfy the relationship of k_tra =–k_tor. If the CR PLL, as shown in Figure 14.4, is a second-order system, then we will have k_tra = 40 dB/decade. For a first-order or “golden” PLL, we will have k_tra = 20 dB/decade. Certainly, a clock and data recovery unit using a higher order PLL will result in a better jitter tolerance capability. For the same corner frequency (f_c), a second-order PLL has better jitter tolerance compared to a first-order PLL.

Testing of global clock interfaces is relatively straightforward on commercial automatic test equipment (ATE). The input waveform of both the clock and data inputs can be generated from the tester with the proper format and timing control. Because the clock is preprogrammed (usually set at somewhere within the tester’s cycle), all input setup and hold time will simply be timing generator edge placement around that clock edge (see Figure 14.16). The tester can strobe the output signal using either window strobe mode or edge strobe mode. The strobe edge or strobe window will be defined by the delay time specification.

Figure 14.16. Global clock I/O timing tests as implemented on ATE.

The testing of source synchronous interfaces is somewhat more complicated. For testing the input side, not much is changed from that of the global clock situation. One can program where the clocks (or strobes) are and then the other input signals are programmed around it according to the setup and hold time specification.

However, at the output side, the device under test (DUT) will send out both a strobe and the output data. The tester is supposed to use the strobe to strobe the data and has to ensure that the data have sufficient valid time before and after the strobe; however, the traditional tester architecture is not designed to use an external clock to strobe the data. This earlier architecture of the tester is designed to parallel-process all data coming from the DUT. Because of the limited level of tester pin-electronics integration, there is simply not enough time for the signal coming in through a pin-electronics card to be routed to another card to strobe the data.

Ten years after the introduction of the first source synchronous (SS) bus, newer generations of ATE are finally able to take advantage of the pin-electronics integration to route signals between the channels. The tester can now take the clock/strobe signal(s) out of the DUT to strobe the rest of the data pins natively [Sivaram 2004].

With the earlier generations of ATE, the usual way to get around the problem of testing for SS is to program a search routine to find where the output clock edge is and then program the window strobe for the corresponding data to ensure that the data are stable within the valid specification window (see Figure 14.17). This has the disadvantage of a longer test time, as time search is time consuming on the tester (each setting and resetting of the timing generator requires some time to settle once programmed). The tester accuracy also cuts into the measurement twice (first for the clock, and then for the data valid check) and will pose a hefty toll on product margin and yield. Another solution is to use the capture memory of the tester to undersample the outputs over a range of cycles to estimate where the data pin timing distribution is.

Figure 14.17. Source synchronous timing tests as implemented on ATE.

Both methods may work well for lower data rate (<400 Mbps) but are usually ineffective for higher data rate because of the native common mode noises, such as coupling and ground bounce effects, present on the SS bus. If there is a noise source in the DUT, this noise usually will manifest itself as a common mode symptom causing both strobe and data to jitter. Although the SS receiver may interpret the data correctly, external instrumentation using search or undersampling methods can see that the data eye shrinks, causing yield loss or lower bin-split.

An alternative test method is to add DFT to support high-speed SS I/O testing, which is the subject of Section 14.4.1. Because of the availability of newer generations of ATE that can support native SS, the problem also goes away if there is liberty to upgrade the tester fleet to support high-performance bus signaling.

We focus on JNB tests for an embedded clock serial I/O, as they are the most challenging tasks because of the complexity in the test method and high precision requirements for the test equipment. We classify JNB tests into three major categories: (1) the JNB output test, (2) the JNB tolerance test, and (3) the link system test. JNB output is typically tested at either the transmitter output pin or the receiver input connector. For most long-haul network devices, a JNB output test verifies the performance of either the transmitter or the transmitter plus the medium or channel. For some new Gbps computer I/O standards, JNB testing may also include the reference clock. A JNB tolerance test involves setting the worst-case jitter and noise condition(s) at the receiver input pin and measuring the BER at its output. A JNB system test checks the overall BER comparing the data bits received by the receiver with the data bits sent by the transmitter.

Transmitter

There are two closely related requirements for a JNB output test: (1) a minimum eye-opening at BER = 10^–12 under a compliance clock recovery jitter transfer function, and (2) worst-case test patterns. The minimum eye-opening defines two important metrics: TJ and total noise (TN), both correspond to a BER at the 10^–12 level. A worst-case test pattern for generating worst-case DDJ and crosstalk jitter is needed for compliance test. Jitter components such as DJ and RJ are required for diagnostic testing and may also be required for some types of compliance testing.

Figure 14.18 shows a generic setup for JNB output testing. The critical elements of the clock recovery function (in terms of H[s]) and the data and clock input difference functions need to be in place. The eye diagram and its corresponding PDFs and CDFs measured in this way will have the right transfer function applied. Important jitter components, such as DJ, RJ, and TJ, as well as noise components, such as DN, RN, and TN, will be derived from those PDFs and CDFs with the required statistical confidence level.

Figure 14.18. A test setup for JNB output.

Figure 14.19 illustrates the effect of using a recovered clock and a noncompliant clock (i.e., a jitter-free clock whose phase does not track the phase of data) when making a clock-to-data measurement at 2.5 Gbps with a 200-KHz periodic modulation added to the data signal. The measurement was performed with a built-in, programmable hardware clock recovery circuit. The results show that the DJ was 13 ps with the recovered clock (with a corner frequency f_c = 1.5 MHz) and 140 ps with a noncompliant clock. Eye diagrams for both are also provided. This example illustrates the importance of incorporating the clock recovery frequency response in testing because the system with a higher corner frequency can tolerate more periodic jitter. Without a correct clock recovery frequency response incorporated in the testing system, good parts could easily be rejected, resulting in serious yield and revenue losses.

Figure 14.19. Eye diagrams based on compliance and noncompliance clocks.

Figure 14.20 shows an example of JNB output compliance test results. This example shows a relatively clean eye diagram with sufficient jitter and noise margin with respect to a≤10^–12 BER compliance zone. A good JNB output will have a wide-open eye with large eye-openings in both timing and amplitude axes or, equivalently, small timing jitter and amplitude noise.

Figure 14.20. A compliance JNB output test example.

Channel or Medium

The channel or medium of a high-speed I/O plays an important role in determining both system and component architectures. Because of the infrastructure legacy limitations and cost constraints, the improvement of channel performance has not been able to keep up with the data rate increase. Most of the improvements were in the architecture of the link as well as in the integrated circuits of transmitters and receivers.

Most channels used for high-speed I/O link are either copper or fiber-optics based. Most computer system channels, for example, are copper traces on PCB with FR-4 material. A copper-based channel typically suffers from frequency-dependent losses such as conductive skin effect and dielectric losses [Johnson 1993].

The effect of the lossy channel to the bit symbol, the waveform, the DDJ, and the data dependent noise (DDN) can be seen in the eye diagram shown in Figure 14.21. If the bandwidth of the channel is greater than the highest frequency content of the signal, then there will be no waveform distortion nor any DDJ or DDN introduced by the channel.

Figure 14.21. Lossy channel effect in terms of eye diagrams.

In theory, the channel can be characterized by a transfer function based on the LTI theorem. In practice, a channel is commonly characterized by the S-parameters that can be measured by a vector network analyzer (VNA) instrument. The S₂₁ parameter gives the loss function from port 1 (input) to port 2 (output) and is the same as the channel transfer function H_ch(s) in the LTI description of the channel.

For any given reference transmitter and receiver, the channel characteristic requirements can be specified to achieve the overall BER performance goal of the link [PCI-SIG, 2007]. If frequency-dependent loss is the only concern, then whether a channel meets the compliance requirement or not may be judged by comparing the measured S₂₁ parameters function with the compliance mask, as shown in Figure 14.22.

Figure 14.22. S-parameter magnitude function for a channel.

However, a go-no go test method for the channel simply based on S₂₁ magnitude can be too coarse because (1) S₂₁ phase information is ignored, and (2) crosstalk and reflection-caused ripple may not be well captured and factored in for worst-case scenarios. If the channel is known to have a linear phase or a constant group delay, and has insignificant crosstalk and reflection, then the simple S₂₁ magnitude-based channel test method may still work well.

Receiver

The ultimate goal for JNB tolerance testing of a receiver is to verify that the receiver can operate at a target BER (i.e., 10^–12) when either the input signal or jitter is operating under the worst possible conditions. There are two aspects regarding JNB tolerance testing. The first aspect involves verifying whether the receiver CR tolerance frequency response is indeed better than that of the target threshold. Figure 14.23 shows the concept for testing the receiver CR jitter tolerance frequency response.

Figure 14.23. Receiver jitter tolerance threshold for testing.

The target threshold curve of the frequency response is indicated in the figure. If the measured jitter frequency tolerance curve is above the threshold curve, it indicates a passing result because the receiver clock recovery can tolerate or track more jitter than required. On the other hand, if the measured jitter frequency tolerance curve is below the threshold curve, then it indicates a failing result. Note that all three curves shown in the figure correspond to the same target BER (e.g., 10^–12).

The second aspect is to verify the receiver tolerance capability under worst-case signaling, jitter, and noise input conditions. The worst-case conditions critically depend on the link architecture, and the jitter and signaling budgets [Li 2004] [PCI-SIG 2004, 2007]. A worst-case input signaling condition can be intuitively viewed with a worst-case input eye as shown in Figure 14.24.

Figure 14.24. A worst-case eye condition for receiver tolerance testing.

Attention must be paid to the frequency content for this worst-case eye diagram because different jitter or noise spectrum content can give rise to a seemingly worst-case eye, yet the stressing level to the receiver and, in turn, the resulting BER can be quite different because of different receiver architectures.

To test for the worst-case jitter and noise condition, all the possible jitter and noise components should be present in the input signal. Figure 14.25 shows a testing setup to stress the worst-case receiver tolerance condition for achieving good test quality. The frequency response tolerance test is covered in this generic setup. Receiver jitter, noise, and signaling test can be exhaustive, given the relatively small number of potential control parameters and the resulting possible combinations. Furthermore, accurately calibrating the signal, jitter, and noise stimulus is important because inaccuracy in the jitter and noise stimulus can cause inaccurate results.

Figure 14.25. A generic setup for receiver jitter and signaling tests.

Specialized methodologies for receiver tolerance testing can be found in the literature. For example, in [Yamaguchi 2002], the authors proposed a method for measuring jitter tolerance of a high-speed receiver by utilizing the timing misalignment between the jittered source clock and the recovered clock.

Reference Clock

When testing Tx output or Rx input for a PI-based architecture, as shown in Figure 14.4, the reference clock signal needs to be clean so that there will be no contamination in JNB between the Tx, medium, and reference clock. At the same time, the reference clock itself must be tested according to bandpass filter function [Li 2004] [PCI-SIG 2004]. Figure 14.26 shows a typical transfer function magnitude frequency response. Notice that it is a bandpass function with a peaking. The 3 dB frequencies, peaking, and the overall shape depend on the PLL parameters and the propagation delay between the Tx and Rx route for the reference clock. An example of a reference clock jitter spectrum before and after the filter function that tracks the shape of the transfer function is illustrated in Figure 14.27.

Figure 14.26. Jitter transfer function for a reference clock.

Figure 14.27. Reference clock jitter spectra before and after the filter function.

System-Level Bit-Error-Rate Estimation

An approach proposed in [Hong 2004] and [Hong 2007] attempts to estimate the BER using the following two sets of parameters: (1) the jitter spectral information, extracted from the signal at the input of the receiver, which includes the RMS value of the RJ and the DJ characteristics, such as frequencies and amplitudes of the PJ components, and (2) the jitter transfer characteristics of the clock and data recovery (CDR) circuit including both magnitude and phase responses. In principle, if the frequency of input jitter is relatively low, the CDR circuit can track the jitter, and thus insignificant bit errors will occur. However, if the input jitter varies rapidly, the CDR circuit may not track the jitter, and some bit errors will occur. On the other hand, the CDR circuit has an opposite reaction to the internal noise of the CDR circuit. That is, the high-frequency component of the internal noise is transparent (and thus will be directly added) to the recovered clock, instead of being filtered out by the CDR circuit. In addition, the phase response of the CDR circuit, which determines the timing response in clock recovery, has a strong correlation to the BER [Hong 2004]. If the jitter frequency falls into the range where the phase delay is nonzero, the CDR circuit introduces some timing delay to the recovered clock, which will, in turn, contribute to the BER. At a specific frequency range, this timing delay can cause a significant increase of the BER. This work provides insight to the dependency of the BER variations on the jitter spectrum and the jitter transfer characteristics of a CDR circuit. Equations were derived for BER estimation based on the measured parameters mentioned above. The results of Figure 14.28 comparing the estimated and measured BER on a 2.5-Gbps commercial CDR circuit show high accuracy of the estimation technique.

Figure 14.28. BER estimation considering the CDR and jitter characteristics at the frequency region.

Tester Apparatus Considerations

The accuracy of any tester apparatus used will affect the pass/fail results and product yield in testing JNB. This is true for both on-chip and off-chip testing, with a laboratory instrument or a production-oriented ATE system. Receiver emulation with appropriate clock recovery built-in may be achieved using a loopback method for system testing, but it remains a challenging problem for component testing. Also, BER at the level of 10^–12 or below is not test-time friendly. Test time in the range of hours is required for BER at the level of 10^–12. In this section, we discuss challenges related to the tester apparatus, as well as possible solutions.

Hardware Bandwidth and Accuracy

Testing hardware, including both the signal source stimulus and measurement receiver, needs to have little intrinsic DJ, RJ, DN, RN, as well as sufficient bandwidth for testing JNB. A bandwidth of 2.5 to five times the data rate is generally needed to generate an accurate JNB, its waveform, and the associated rise/fall time measurements. Figure 14.29 is an example of such a requirement with the assumption of a 10% total jitter margin for BER at the 10^–12 level, of which 2% is from DJ and 8% from RJ. Using a 10-Gbps data rate as an example for which UI = 100 ps, at 10^–12 BER, we obtain TJ = 0.1UI = 10 ps, DJ = 0.02UI = 2 ps, and RJ (rms) = (0.08UI)/14 = 0.571ps. The corresponding numbers can be derived for other data rates and the graph shows the upper limits of RJ and DJ as a function of data rate.

Figure 14.29. DJ and RJ for the tester as a function of data rate.

“In Situ” Testing to Emulate the Receiver

As described earlier, serial data communication uses the recovered clock as its reference for recovering data at the receiver. This CR unit forms a high-pass frequency response that allows the receiver to track the low-frequency jitter, as well as constitutes the mask for jitter tolerance testing. The jitter transfer function must be incorporated in JNB testing. Otherwise, JNB testing would result in either underestimation or overestimation. Both hardware clock recovery and digital-signaling-processing (DSP) based soft clock recovery can be used for JNB testing. However, designing a programmable clock recovery receiver for JNB testing, which has the features of sub-ps jitter generation and UI jitter tolerance at low frequency, is a nontrivial task. Soft clock recovery is possible if the real-time record has sufficient resolution and is obtained by a real-time sampling circuit. The real-time record is the key to enable the soft clock recovery, as it captures the phase information of the JNB [Li 2003].

Throughput

Throughput is a critical metric for production testing. To catch one error at 10^–12 BER for a 1-Gbps link requires about 10³ seconds. To enhance the statistical confidence, a bit error sample of about 20 or more is needed per Poisson statistical requirement. This means that a good BER measurement with a BERT will take about 2×10⁴ seconds to complete, which is too long for any practical production test to accept. Consider another example where an equivalent sampling scope is used for testing jitter via its eye-diagram function. Obtaining a timing jitter histogram with only a few thousand hits will take a few minutes. Although the time needed is much less than that required for taking 10¹² samples, it is still much longer than the typical IC production test time, which often is less than 10 to 100 ms. Fortunately, there are available model-based extrapolation methods that have demonstrated the capability of estimating the TJ at 10^–12 BER with good accuracy and high confidence at a total test time around 50 ms [Li 1999] [Hänsel 2004] [Cai 2005]. While achieving high test throughput is always favorable for any test process, this goal is more critical for high-volume and low-cost production test than low-volume laboratory design verification and characterization test.

In the early 1990s, an I/O structural test methodology called I/O wrap [Gillis 1998] was developed. More commonly called I/O loopback, this method involves applying a transition fault test methodology to I/O circuitry. By tying an output to an input, the output data are launched and latched back into the input buffer on the following clock. As most signal pads are I/O in nature, the I/O wrap (I/O loopback) methodology is convenient. Input-only or output-only pads can be connected with the DFT circuit or wires/relays present on the loadboard. The limitation to this method is that, because the delay path is tested with the clock, the delay cannot be characterized without overstressing the other peripheral circuits. This approach is limited to testing gross delay defects, and timing specifications cannot be measured.

By the early 2000s, a test methodology known as AC I/O loopback testing had been proposed (see Figure 14.30). This uses the same loopback principle, but with a twist [Tripp 2004]. Rather than just using the clock to launch and capture the signal, the launch can be carried out by a delayed version of the clock or the capture be accomplished using an early version of the clock (see Figure 14.31). By controlling the delay, the relative delay between the strobes and data can be actually measured without precision timing measurements from ATE.

Figure 14.30. Using IO buffers as loopback components for an SS interface in which the strobes that clock the data out to the receive side also strobe the data loopback to itself.

Figure 14.31. AC I/O loopback testing as a defect-based test method.

Essentially, this is transition fault testing of the I/O pair with a tighter clock cycle. Only the I/O circuits are tested in this method, thus preventing false fails from other circuits as in the case of speeding up the I/O wrap. This method works well with the source synchronous (SS) scheme, where the strobes are generated by the transmit side. In the SS signaling protocol, the absolute delay of the I/O is not critical; instead, the relative delay of the strobes and any associated data bits are important. These timing delays, denoted as time valid before (Tvb) and time valid after (Tva), describe the relationships between the strobe and the data bit (see Figure 14.3). So by moving the strobes from their central position to the trailing edges of the data (see Figure 14.32), we are stressing Tva and the setup time of the receiver latch. If we move the strobes toward the leading edge of the data, we are stressing Tvb and the receiving latch’s hold time. By stressing this combined timing, we know how much margin there is with the combined pair. If the induced delay to the clock/strobes is calibrated, we can even have more accurate measurements (timing margining) using this combined loop time than is possible with external instrumentation (see Figure 14.32). Because the failure mechanisms for signal delay and input setup/hold time are different, the probability of aliasing is low. Slightly different implementations can be applied to global clock (GC) interfaces.

Figure 14.32. Various elements in the AC IO loopback system to facilitate accurate timing test.

Furthermore, because we are not measuring each data bit independently (this is a bus nonetheless), the delays of all of these data bits should be close to one another unless there are defects or local process variations. If a particular data bit is substantially different from the other data bits (see Figure 14.31), we can also conclude that a defect or local process variation exists with that particular bit and declare that to be a failure. This can also be viewed as a defect-based test method, especially if no calibration of the induced delay is made. The testing can also be carried out faster when all bits of the bus are compared simultaneously when the loop timing is tightened. A tight distribution of the passing region indicates all the bits are aligned, and a wider distribution of the passing region indicates some bits are slow or mis-aligned; all are causes to fail the chip. If further diagnosis is desired, then we can resume the stressing of individual bits.

Instrumentation-based testing as explained in the previous section is much more accurate than that of DFT-assisted loopback test. However, it also requires special instruments to be set up, calibrated, and integrated into test platforms. The lengthy setup time, long test pattern sequence application, and data capture, which is typically followed by extensive numerical analysis, often require experienced personnel (e.g., a technician) and longer test time than would be desired in a high-volume manufacturing setting. As serial link technologies are deployed to an increasingly cost-sensitive commodity computing world, it is required to lower test costs.

For high-speed serial links, loopback testing is common, because input and output are conducted on separate channels (serial pair) and there is usually the accompanying transmit and receive channels even in a given component. Loopback testing has been around for as long as serial interfaces have been around.

However, simple loopback testing is just a simple functional test. All the required jitter and noise tests are not possible with this method, and there is no guarantee that the simple loopback test can interoperate with other similar components in an extreme environment. Loopback also makes diagnosis difficult because the defective component cannot be easily located. There is also the nonzero probability of aliasing—that is, a bad receiver, for example, may be covered up with an extremely good transmitter. Thus, within the industry one may also characterize loopback test as just a “system test,” as it is commonly used in a system setting to verify that the system is functional.

To improve on simple loopback testing, several approaches have incorporated jitter injection capabilities into the loopback to “stress” the signal and thus test the receiver’s jitter rejection or noise-tolerant capabilities [Laquai 2001] [Cai 2002, 2005] [Lin 2005]. Many of these approaches consist of passive resistance-inductance-capacitance (RLC) filters, which introduce frequency-dependent delays and losses to the various frequency components (or harmonics) of a high-speed serial signal. When various combinations of 1’s and 0’s are transmitted (e.g., ISI patterns), the signal will appear as various frequency harmonics (as data are never constant in the frequency domain). As different frequency components are attenuated differently, the resultant timing waveform will be distorted enough to resemble that of a worst-case jittering data eye. The filter can simply be placed on the loadboard between the input and output channels. It is a relatively cheap solution to an expensive test problem. Of course, the filter design has to be coupled with the driver’s characteristics (original spectral components), and it is data rate dependent (which determines the base frequency). This method also does not address the need to test the transmitter’s drive characteristics. A jittering transmitter signal will add to the distortion of the filter and will likely cause the Tx-Rx pair to fail to communicate reliably, resulting in the rejection of otherwise working devices. However, an extremely good receiver can also potentially hide a marginal transmitter, as the pair is essentially tested together.

Another proposed jitter measuring solution utilizes a undersampling method [Huang 2001] [Cai 2005]. The method utilizes the Rx to capture the data sent from its Tx via a loopback on the TIU or on the die itself. Instead of using the recovered clock to strobe the data, an alternate reference clock that has a frequency close enough to the data clock frequency is used to strobe the data. It will result in a much lower data rate (the “beat” f_B of the two frequencies f_D and f_S) as shown in Figure 14.33, where f_D is the frequency of the data, f_S is the frequency of the sampling clock, and f_B is the frequency of the “beat.” The jitter that exists on the data channel will dither the data captured. By analyzing the percentage of 1’s versus 0’s, one can deduce the jitter amount. Hardware and methodologies for performing this analysis in real time have been developed [Sunter 2004a, 2004b, 2005]. This can be implemented as a field programmable gate array (FPGA) on the loadboard (see Figure 14.34) or even embedded in the silicon itself, making the whole thing close enough to be called IOBIST. While undersampling has been proven to work theoretically, the authors have not addressed the issue with practical implementation (e.g., finding the right PLL for the 9.999-GHz sampling clock for a 10-GHz data frequency or the jitters introduced with routing this external clock to various serializers/deserializers on a chip with many high-speed serial channels).

Figure 14.33. Principle of undersampling for jitter measurement.

Figure 14.34. Jitter measurement setup where reference clock, pattern generator, and analysis can be off-chip.

In [Sunter 2005], the authors proposed that by monitoring the placement of the recovered clock versus the received data eye, jitter tolerance can be reduced. Although this is one indication that the recovered clock has centered and has the highest probability of correctly strobing the data eye, it cannot predict the dynamic behavior of the CDR circuit well enough for high-frequency jitters (i.e., the data eye and the recovered clock may close down the margins statistically, but the CDR may still be able to recover the data should the CDR circuit be dynamic enough to track the jittering signal). Hence, the scheme may be more conservative and may reject devices that are operational.

The last method as proposed in [Mak 2005] involves assessing data eye via margining as an approach to testing Gbps SerDes. The approach assumes that defective components are relatively rare, and loopback is established with a data pattern streaming through the lookback path. Testing consists of two parts. The first part uses the receiver, which is assumed to be good, to test for the size of a valid data eye. By varying the data strobe point (i.e., by changing the phase of the recovered clock) and the receiver threshold, an eye for the resulting data can be captured [Casper 2003]. A production test can consist of the four points that define the size of the minimum data eye required. The second part of this method is the stress test of the receiver with the transmitter. Again, it is assumed that the transmitter is good. Additional DFT, such as jitter injection into the high-speed clock or introducing small delays into the signal stream (such as those in pre- or de-emphasis circuits) will play the role in jitter injection so that the receiver can be stress tested. It is virtually impossible to generate all kinds of deterministic and random jitter required for the characterization of the serial link with all the necessary built-in DFT, particularly when a new interface is first designed and there is no way of knowing what the receivers are sensitive to; however, it is advisable for these jitter injection circuits to be programmable so that a richer or more diverse set of stimuli can be generated. The proper set of stimuli is defined only after extensive characterization of early samples to minimize both escapes and test time.

Similar techniques have also been reported in [Robertson 2005]. These techniques may not fully test the CDR circuit, as the same clock source may be used to generate the output data stream at the transmit side and drive the receiver circuits. One has to study the actual design to be sure that the jitter generated at the transmit side indeed can stress test the receiver circuits without aliasing.

A comprehensive test methodology would be more desirable and unavoidable as the frequency/data rate continues to increase. At a higher data rate, signal degradation through the channel will simply close the data eye. To alleviate the problem of signal degradation, modern receiver design employs a means for compensating or reducing the ISI in the received signal. The compensator for the ISI is called the equalizer. Various equalization techniques, which multiply the inverse response of the channel to flatten out the overall frequency response, have been developed to compensate for this channel effect. In addition, the channel characteristics may not be known in advance and might be time variant. To cope with such problems, several adaptation algorithms have also been developed to adjust the overall response depending on the channel conditions. The equalizer can be implemented either in the transmitter or in the receiver. The implementation of the transmitter equalizer is relatively easier than that of the receiver equalizer because the required finite impulse response (FIR) filter deals with the digital data at the transmit side, rather than the received analog data at the receive side. However, as channel information is not easily available at the transmitter, it is difficult to apply the adaptive technique at the transmitter. More recent publications [Jaussi 2005] tend to use the latter.

The approaches of equalization at the receiver can be divided into two categories: discrete-time equalization and continuous-time equalization. A discrete-time equalizer, which is based on the FIR filter, can take advantage of various digital adaptive algorithms. However, because equalization is based on the samples captured by the receiver’s recovered clock, there exists a cross-dependence between the equalizer and the clock recovery circuit. As the data rate increases, the power consumption would increase dramatically as a result of the large number of taps implemented in this type of equalizer. On the other hand, a continuous-time equalizer does not require a sampling clock, and thus the equalizer would work independent of the clock recovery circuit. Continuous-time equalizers have been investigated for low power and high-speed applications, and promising performance has been reported.

A DFT concept for testing digital equalizers is developed in [Lin 2006]. This proposed technique can be applied to a wide range of linear equalizers using various adaptive algorithms. The extra hardware required for the DFT solution needs only a scan chain, which can directly observe the state of the adaptation status of the equalizer, and one simple digital pattern generator. The overhead and the additional design effort of the approach are insignificant. With the proposed DFT solution, the equalizer in the serial-link receiver can be characterized and tested without direct access to the equalizer output. This alleviates the need for observing the equalizer output, which is often infeasible.

A method for testing continuous-time adaptive equalizers has recently been proposed [Hong 2007] which was validated by simulation on a low-power, 20-Gbps continuous-time adaptive passive equalizer. Figure 14.35 shows the architecture of a typical continuous-time adaptive equalizer. The equalizing filter either boosts the high-frequency components or attenuates the low-frequency components of the received input signal to compensate the high-frequency loss resulting from the channel. The adaptive servo loop, which adjusts the compensation gain of the equalizing filter, determines the control voltage by comparing the input and the output signals of the comparator. In practice, it is difficult to design a comparator that can generate a clean waveform for comparison at very high frequencies. Several design approaches for adaptation have been proposed to address this problem. These new methods use the power spectrum derived from the output signal of the equalizing filter for the adaptation, as shown in Figure 14.36. Because the power spectrum of a random signal can be described by a sinc-square function, the high-frequency loss can be detected by comparing the power densities of two different frequency ranges. Three different methods have been proposed to compare the power spectrum of the random signal: (1) two band-pass filters can be used to compare the power of two specific frequencies (see Figure 14.37a); (2) one low-pass filter and one high-pass filter can be used to compare the power between low-frequency and high-frequency portions of the signal (see Figure 14.37b); and (3) only one low-pass filter is used and the entire signal power is compared to the power of the low-frequency portion of the signal (see Figure 14.37c).

Figure 14.35. Architecture of a conventional continuous-time adaptive equalizer.

Figure 14.36. Architecture of a modified continuous-time adaptive equalizer.

Figure 14.37. Three different architectures for power spectrum comparison.

The main idea behind the approach in [Hong 2007] is to directly apply a two-sinusoidal-tone signal as test stimulus at the input of the equalizer, as opposed to a data pattern stressed through the channel, which has been commonly used for validating and characterizing the equalizers. The frequency for one of the two sinusoidal tones, denoted as f_L, falls within the frequency band of the left filter in Figures 14.37a and 14.37b, and the frequency of the other tone, denoted as f_H, falls within the frequency band of the right filter in Figures 14.34a, 14.34b, and 14.34c. To thoroughly mimic the channel response, this technique repeatedly applies the two-tone signal by gradually varying the magnitude ratio of f_H and f_L. Such test stimuli mimic different relative loss of the high-frequency components caused by the channel.

With the test stimuli, the RMS value at the output of the equalizer is measured for characterization and for fault detection. Based on the principle of how the continuous-time equalizer works, the adaptive servo loop of the equalizer attempts to maintain the ratio of f_L to f_H to the expected level based on the sinc² function. Thus, if the test stimulus’s f_L and f_H magnitudes are within the range of the equalizer’s maximum compensation gain, the RMS value of the equalizer output should be a constant. Therefore, by carefully crafting the two-tone stimuli and inserting an RMS detector on-chip for monitoring the equalizer’s response to the two-tone stimuli, this technique can detect defects either in the equalization filter or in the adaptive servo loop that might not be easily detectable by the eye-diagram method.

In addition to the equalizers, other types of compensation elements are used in advanced I/O interfaces. One type of such compensation elements is the crosstalk canceler. Figure 14.38 illustrates an example architecture of an advanced transceiver, which includes a CDR circuit and a decision-feedback equalizer (DFE) in the receiver, a feed-forward equalizer (FFE) in the transmitter, and a crosstalk canceler between the transmitter and receiver. Such a transceiver has the capability to equalize the lossy channels, to remove signal reflections, and to actively cancel the crosstalk noise in the transceiver. For 10-Gbps data rate over backplane channels or other long-range applications, crosstalk that is the dominant noise for microstrip interconnects is becoming a limiting factor for signal integrity. Among various types of crosstalk sources, the near-end crosstalk (NEXT) is the most severe one [Vrazel 2006]. Active NEXT cancellation using a crosstalk canceler in the transceiver could be an effective solution to addressing the crosstalk problem [Pelard 2004] [Hur 2005].

Figure 14.38. Architecture of an advanced transceiver with a crosstalk canceler.

A DFT solution for such an advanced transceiver is recently proposed in [Lin 2007]. The solution is an enhancement of the technique proposed in [Lin 2006]. The hardware requirement for the DFT solution contains only one shift-register chain and one simple digital pattern generator in the DFE, and three full-swing taps in the crosstalk canceler. With the proposed DFT solution, the transfer characteristic of the CDR in the receiver can be derived, and the DFE can be characterized and tested without direct access to the DFE output. This alleviates the need of external instruments for jitter testing and the need for observing the equalizer output, which are often infeasible in the high-volume production environment.

The aim for this test method is to primarily identify board-level manufacturing problems, such as incorrectly placed devices (chips do look alike), rotated devices, bent leads, cold solder joints, improper socketing (if sockets are used), cracked PCB and traces, via problems, etc. The IEEE 1149.1 boundary-scan standard [IEEE 1149.1-2001] is commonly used for interconnect testing of above-mentioned manufacturing problems (see Figure 14.39).

Figure 14.39. P1149.1 system-level interconnect test.

The basic concept of the 1149.1 standard is the addition of a boundary-scan cell for every input or output pad in the chip. Through the test access port (TAP), each boundary-scan cell can be set to 1 or 0 independently through the boundary-scan chain. When the net connected to both ends of two chips (chip 1 and chip 2) implemented per the IEEE 1149.1 standard, the data that are driven by one end of the net are captured by the receiving boundary-scan cell and subsequently shifted out through the boundary-scan chain for analysis. This can detect and locate permanent faults, such as stuck-at, open, and short faults on the nets. Each chip often includes a 32-bit device identification (device-ID) register, which stores the vendor’s identification code (containing the manufacturer’s identity, the part number, and the version number of the chip). The 1149.1 boundary scan allows the designer or user to immediately pinpoint the errors to the defective interconnects or bad chips.

Many interconnect test algorithms and solutions have been proposed [Wang 1992]. For more information on the basics of the IEEE 1149.1 standard, please refer to [Bushnell 2000] and [Wang 2006].

The IEEE 1149.1 boundary-scan standard has been the mainstay for board-level interconnect testing since the early 1990s. However, the world of chip-level interconnects has changed from tens to hundreds of Mbps to that of multiple Gbps data rate. The signaling technologies for transferring those data have also changed from single-ended signaling to that of differential, clock embedded, and in some situation, even AC-coupled. Although one can design in the 1149.1 test access port (TAP) controller to run faster for testing these modern-day high-speed (SS) buses and serial links, it is becoming ineffective because of the non-performance-driven nature of the 1149.1 architecture. The state transition through the 1149.1 TAP controller state diagram (see Figure 1.4b in Chapter 1) from Update-DR (data are driven onto the net in one chip) to Capture-DR (data on the net are captured in the other chip) takes 2.5 TCK cycles (see [IEEE 1500-2005]). Moreover, the nature of differential and AC-coupled (there is no DC path) signaling on high-speed serial links also makes it incompatible with the 1149.1 standard.

The IEEE 1149.6 standard [IEEE 1149.6-2003] is an extension of the IEEE 1149.1 standard to deal with this differential, AC-coupled interface. With this standard, independently controllable digital driver logic and digital receiver logic (with the analog test receiver) under the control of the 1149.1 TAP controller are now implemented on both ends of the differential pads of the serial link so interconnect tests can be applied on these differential pads to detect defects that may exist between the differential lines. The analog test receiver is specially designed for edge detection for capacitive coupling. For a more thorough description of the IEEE 1149.6 standard, please refer to [IEEE 1149.6-2003] or Chapter 10 of [Wang 2006]. Because it is an extension of the 1149.1 standard and there is no change to the underlying TAP architecture, 1149.6 still basically runs at a relatively slow data rate. What this test method fails to address is that these new high-speed serial interfaces have to run billions of bits every second. Passing 1149.6 testing alone cannot guarantee the data rate nor transmission reliability, particularly when the system I/O is running at multiple Gbps data rate.

To examine this high-speed signaling issue a bit further, we can look into the test pattern requirement of testing these high-speed serial channels (interconnects). Because of the loss of signal energy in the medium (sockets, PCB traces, or cables), simple 1 and 0 patterns (or clock patterns) do not stress the interface enough. While an extended JTAG architecture to test SOC interconnects (parallel buses) for signal integrity has been reported in [Ahmed 2003], [Tehranipour 2003a], and [Tehranipour 2003b] where maximum aggressor (MA) and multiple transition (MT) fault models are employed (see Chapter 8), these methods have limited use for testing high-speed serial channels. Because differential signaling is used, they are resistant to common mode noises, such as coupling and ground bounce effects. The common mode noises are simply canceled out unless they make a difference between both lines. The issue with serial signaling is that the pattern changes so fast that before the pattern has a chance to go from one state to the opposite state fully, it has to go back to the original state again because of fast data changes (see the tightly packed data train in Figure 14.40). This creates data waveforms that are more difficult to differentiate (whether it is a 1 or a 0). Also, a long series of 0 or 1 patterns (the fatter portion of the waveform in Figure 14.40) also makes the signal saturated to one side, and when a single bit of data change comes along the signal will take a longer time to ramp before it has to change again. This makes for the worst-case data eye. This is called ISI. So data pattern is critical for board-level and system-level testing when the media play a major role.

Figure 14.40. Signal effect of intersymbol interference (ISI) on a high-speed serial link.

Interconnect built-in self-test (IBIST) was introduced in [Nejedlo 2003]. It is based on the premise that high-performance interfaces have to be tested at high speed. In a board manufacturing environment, it is desirable to separate board assembly defects without running full board-level functional tests. These types of tests should be carried out before the system attempts to boot/start up to increase the confidence level of the overall board manufacturing process.

Figure 14.41 shows an IBIST example with two components as applied for high-speed serial testing at the board level. The two sides (components) of the I/O interface are named master and slave (the order is not that important as the role of master/slave can be reversed). On the transmit side, IBIST consists of a programmable pattern generator behind the Tx driver or transmitter of the I/O interface in the high-speed serial link. On the receive side, IBIST consists of logic to route the received data (Rx) back to their own transmitter as well as error checking logic (XOR gates), which can check the pattern transmitted versus the received pattern. To further reduce the circuit requirement, the slave can simply implement the internal loopback circuit to support only the bounced back mode. With this reduced logic, it cannot independently send a pattern but will support the bounced back mode only. The independent pattern generator allows the interface to be tested independent of the core logic of the chip that has these high-speed interfaces. With this scheme, the master will take control of the whole test process. The included pattern generator on the master then drives a high-speed pattern to the slave side. Upon receiving it, the slave resends all the data that it has received (in bounce-back mode) immediately (bit-per-bit) through its own transmitter. The master’s receiver receives this retransmitted pattern and checks it against the original transmitted pattern. Error checking is done on a symbol-by-symbol basis so that the error can be pinned down to the exact bits and further logic reasoning can be done to figure out what the cause of the error may be. A second stream of data can also be initiated from the slave side to aid with further diagnosis. Control registers keep track of when an error is first detected and can be examined after the test patterns are transmitted and received.

Figure 14.41. BIST as applied for high-speed serial testing at the board level.

To stress test the system, ample data varieties—from pseudo-random pattern generation to specific preloaded patterns (some specific patterns may be needed for specific jitter and ISI requirements)—can all be supported.

From the manufacturer standpoint, if such a system can be coupled with the electrical AC loopback system (described in an earlier section), in-system margin characterization is also possible, providing a much richer set of characterization data. This simply cannot be done with any aforementioned methods.