Robert C. AitkenARM, Sunnyvale, California
Design for manufacturability (DFM) in the context of integrated circuit design is a broad topic that covers a number of activities, all loosely connected by their intention to improve yield. Clearly, no one sets out to design against manufacturability. Instead, many design methods have tended to ignore manufacturability and treat yield as a problem to be solved by the wafer fabrication facility (fab) or foundry. This has happened both in vertically oriented organizations and in fabless environments, but it has been worse in the latter. In some ways, this has been a direct result of progress in the semiconductor industry. Future progress now depends on reversing this trend.
In this chapter, we first provide some background information and historical context for DFM and show how it fits into the modern semiconductor industry. Next, we introduce and define the concept of yield, introduce a variety of yield models, and show how these models can be used to quantify the benefits of repairable circuit elements. This is followed by an introduction to the basic concepts of photolithography. All these concepts are then combined, and we show how they interact for both DFM and design for yield (DFY). We also show their relationship with design for testability (DFT). Following this discussion, we introduce process variation and its relationship to DFM, DFY, and DFT. The combination of these topics is known as DFX, where “X” stands for any of the aforementioned letters, but it might also be thought of as design for excellence. We discuss metrics for quantifying various aspects of DFX, and, finally, we present future directions and conclusions.
In 1965, Gordon Moore published his famous observation in Electronics magazine [Moore 1965]. He predicted that technology innovation would allow the number of transistors to double in a given silicon area every year (he revised the scale to every 2 years in 1975) [Hiremane 2005]. For more than 40 years, the semiconductor industry has been able to track this prediction. In 2006, chips with hundreds of millions of transistors were produced. Moore’s prediction has been so prescient that it is now referred to as Moore’s law.
When Moore made his prediction, he was director of research and development at Fairchild Semiconductor. His biography lists him as “one of the new breed of electronic engineers, schooled in the physical sciences rather than in electronics.” In 1965, when a chip consisted of roughly 50 transistors and only a small number of chips were in production, design and manufacturing were difficult to separate. The entire chip life cycle would fit within a single organization. This remained true through the 1980s. When a company wanted chips for a product, it was often economical to build a fab to go with it. Large companies often ended up with multiple fabs working on multiple product lines (e.g., calculators and computers at Hewlett-Packard, with fabs in Corvallis, Oregon for the former and Fort Collins, Colorado for the latter).
As the integrated circuit (IC) business evolved, it made sense to specialize. When the number of transistors climbed into the hundreds and thousands, digital design split between circuit design (schematics) and transistor design (artwork layout), and manufacturing with its own specialties (mask making, transistor fabrication {front end}, metal fabrication {back end}, and test). Links between design and manufacturing were formalized: design rules to make layout manufacturable and associated design rule checkers (DRCs) [Lindsay 1976], plus design for testability (DFT) rules and methods [Eichelberger 1977]. Eventually, the IC design and manufacturing process stratified into a large number of layers, approximated by Figure 9.1, where it has remained relatively stable. Economic pressure and the benefits of specialization has led to disaggregation of the industry and the introduction of companies specializing in one or more layers, including entire new industries such as wafer foundries and intellectual property (IP) companies. Note that mask making, foundry equipment, etc., are not represented in this example, but they could be.
The existence of this layered structure has allowed organizations to concentrate on areas where they can add the most value, whereas the introduction of standard approaches and hand-offs at layer boundaries have allowed for increasing levels of abstraction with the understanding that the underlying components are sound. For example, a register-transfer-level (RTL) designer can synthesize an RTL design to a standard cell library with confidence that each of the functions in the library will behave in silicon precisely as its model predicts it will. The library designer is able to guarantee this result because each cell follows the design rules specified by the foundry and is simulated using models extracted from actual silicon. Each step in the chain is supported by standard methods (synthesis, characterization, design rule checking) and by commercial tools.
Notice that these examples all relate to digital design. For analog circuits, abstraction has been more difficult to achieve. It has been and continues to be common practice to tune circuits through an iterated process of schematic design, layout, extraction, and simulation. Often, the tuning continues with multiple iterations on silicon as well. Variation in circuit behavior across the manufacturing process has been modeled using Monte Carlo methods [Kennedy 1964] [Balaban 1975], and designs are crafted to be “centered” within a manufacturing process window [Director 1977] (see Figure 9.2). As a result, analog design is tightly linked to manufacturability. An odd side effect, however, is that yield of analog designs is less precisely defined than for digital designs. As will be discussed later, a simple practical definition of yield is “fraction of parts passing applied tests,” and pass/fail criteria are usually easier to specify for a digital design than its analog counterpart.
In its most basic form, yield for a semiconductor manufacturing process can be expressed as:
“Total chips” is easy to calculate (although care needs to be taken to include or exclude certain classes of chips—those from zero yielding wafers, for example). “Good chips,” on the other hand, is much more difficult to define and measure. The ideal definition of a good chip is one that works in a customer’s application, but two problems exist with this definition: (1) it cannot be determined until it is too late, and (2) the requirements may differ between customers and over time. Consider two users of a cell phone as an example. The first uses it to store a couple dozen phone numbers and make phone calls a few times per day, whereas the second adds custom applications, uses it for text messaging, Web access, e-mail, and music video downloads, as well as near constant phone calls. The second user would be far more likely to encounter an inherent flaw than will the first user. There is also a time-based reliability component to “good,” based on expected product lifetime, but we will ignore this factor in the following discussion.
The definition of “good” is ambiguous; so is the measurement of “good.” For example, a chip with higher-than-average leakage could be the result of an unintended resistive short or of faster-than-average transistors. Similarly, there are specified versus observed quantities. Suppose a design is specified to operate above 0.8 V, but the vast majority of manufactured chips are able to operate down to 0.65 V. When a chip is found that fails at 0.75 V, is it good? It meets the spec, but is clearly different from all the other chips. Work in statistical post processing of test results suggests that using “different” as a predictor of “bad” works well in improving shipped quality and future reliability (e.g., the authors in [Madge 2002] showed a 30% to 60% reduction in defective parts per million [DPM] levels by applying such techniques). This emphasizes that the nature and quality of tests is a vital factor in determining both yield and quality. The ambiguous nature of test can be used to expand the definition of measured yield:
“Test escapes” are also known as type II failures—chips that pass the tests but will fail in the application. “False rejects” are also known as type I failures—chips that fail the test but would work in the application. Relative costs vary, but a common rule of thumb is that it is worth having 10 false rejects to avoid 1 test escape. This discussion shows that test and yield are tightly coupled and that failing to consider both can lead to suboptimal results.
Chips fail for a number of reasons, and these can be grouped to form a classification of yield types:
The first class is known as systematic yield. Systematic yield loss affects the process as a whole and must be dealt with by the fab. Examples include equipment-related problems, material quality and delivery, managing contamination sources, etc. These operations are managed as an aggregate across all products being run on a wafer line. Additional details are available in the books [Nishi 2000] and [May 2006].
The second class is parametric yield. Example parameters include critical lithography dimensions (CD), device mobility, threshold voltage, oxide thickness, metal resistance, etc. These also affect the process as a whole, but they can be accommodated by a mixture of fab adjustments and design tolerance. The important feature of this class of yield is that the parametric variations are inherent in the process rather than induced by the design.
The third class is defect-related yield. Defects are imperfections in a fabricated chip, including particle-induced shorts, cracks, poorly formed vias, etc. These defects tend to fall in random locations and be somewhat unpredictable in their properties. The detection and avoidance of defects is the subject of much interest in test, and solutions must be applied throughout the design process. Segura and Hawkins have produced a good overview of the topic of defects [Segura 2004].
The fourth class is design-related yield. This category is similar to parametric yield but emphasizes the deterministic aspect of parametric variation, particularly those variations or deformations that can be predicted based on design layout and margining techniques. These will be discussed in detail in the remainder of this chapter.
The final category is test-related yield. This category explicitly includes the false rejects mentioned earlier, as well as quantification of those based on design and test decisions. As an example, if a part’s spec requires that it operate at 1.0V+/–10%, with minimum operating voltage of 900mV and tester power supply accuracy of 20mV, then low-voltage test should be applied at 880mV to guarantee that no more than 900 mV is applied. This in turn implies that sometimes the test will be applied at 860 mV, so the design must operate at this low voltage. Yield differences between 860 mV and 900 mV operation are an example of test-related yield. Additional discussion is beyond the scope of this chapter but has been discussed elsewhere [Aitken 2006a].
It is desirable to trade off various design approaches in terms of their ability to improve yield. This in turn requires an ability to predict yield—to model expected yield based on some criteria. The simplest such model is the Poisson model. This model assumes that defects are rare events that occur randomly and independently and that as such they can be modeled as following a Poisson distribution. The resulting Poisson yield equation [Nishi 2000] takes two parameters, die area A and a global defect density D0:
Y = e–AD0
For many applications the Poisson model is adequate, especially those involving changes in yield, but it has been shown to be pessimistic for absolute chip yield prediction. One primary reason is that defect density is not uniform and fixed but rather is itself a distribution. Ideally a Gaussian distribution would be used, but the mathematics becomes complex. Instead, approximating a Gaussian defect density distribution by a triangular shape leads to the Murphy model [Nishi 2000]:
Another approach, common among foundries, is to assume a uniform distribution by layer, and to assign a complexity factor to each layer. The cumulative result of these complexity factors becomes “n” in the Bose-Einstein model [Nishi 2000]:
In many foundries, D is given in defects per square inch per layer. For a complexity factor of 12, a value of D = 0.5 in the Bose-Einstein model is equivalent to D0 of 1.12 defects per square centimeter in the Poisson model (the unit change is also typical). Published values for D range from 0.16 to 0.28 per square inch for a commercial 90-nm process as of March 2006 [Sydow 2006].
Another useful model is the negative binomial model, which takes into account the tendency of defects to cluster. This model was advocated extensively by Stapper at IBM [Stapper 1989]:
The clustering parameter, α, has been found to lie between 2 and 3 in many processes. As α approaches infinity, the model reduces to the Poisson model. Additional discussion of yield models is available in Chapter 26 of [Nishi 2000].
The chances of more than a single defect affecting a given instance of a small memory are sufficiently small that they can be ignored. As a result, the Poisson yield model can be used to estimate ΔY, the change in yield expected across area at global defect density when single defects are repaired with probability P(repair):
ΔY = P(repair) · (1 – base_yield)
= P(repair) · (1 – e–AD)
D can be calculated “bottom up,” based on layer defect densities for each layer used in the memory (e.g., product of all individual step yields up to metal 3), or “top down” by fitting observed yield to a Poisson equation. In either case, it is usually recommended to use different values for logic and static random-access memory (SRAM) and to account for the added complexity of SRAM by increasing the value D for logic circuits by a process-dependent factor of 1.5 to 3.
For a single instance, the yield improvement is small, but the yield improvement for each instance is independent, giving an overall value, for n instances, of the following:
ΔYn = repair_yieldn – base_ yieldn
= (e–(A+Ar)D + P(repair) · (1 – e–AD))n – e–nAD
Note that repair improvement applies only to the base area, not the additional area of the test overhead (Ar). Figure 9.3 shows yield improvement plotted against test overhead and defect density for a set of 250 small memories of 16k bits each (128 × 128) in a 90-nm process. A conservative value of 0.5 was assumed for P(repair). Higher or lower values change the scale of yield improvement, but not the shape of the curve.
For large memories, test overhead, including redundant memory cells, remapping logic, fuses, and test controllers is often less than 5% of total area, but for smaller memories this percentage is higher. Figure 9.3 shows that both test overhead and defect density strongly influence yield improvement. Thus, it is vital when designing repair circuitry for small memories to keep overhead low. It is also clear that the need for redundancy is higher when the process is immature and defect densities are higher than it is later in the process life cycle when defect densities are low.
To give some idea of the magnitude of costs involved, if wafer cost is $2500 and there are 100 good dies per wafer (often referred to as net die per wafer), a 5% increase in the number of good dies per wafer decreases the die cost from $25 to $23.80. Over a high volume of chips, the savings can be substantial. If redundancy is already in place for larger memories on a chip, the added external cost (e.g., laser fusing) is virtually zero. For a production volume of 10 million chips, the savings can amount to $12 million. A key part of achieving good yield is photolithography, which is discussed in the next section.
Photolithography is a key challenge in the production of ICs and has a significant influence on both manufacturability and yield. This section outlines the basics of lithography and shows how its complexities directly influence both design for manufacturability (DFM) and design for yield (DFY). Figure 9.4 represents a basic lithography system. (The discussion below follows [Liebmann 2003].) A plane of light of wavelength λ passes through gaps in a photomask set at pitch P apart to create two coherent individual light sources, and they interfere with each other, causing diffraction nodes at any angle where an integral multiple m of the wavelength exists across the difference in path length between the paths, as shown in the figure:
A lens can use these diffraction nodes for image formation provided that its numerical aperture (NA) contains at least the first diffracted order, giving a minimum value for P:
The minimum feature size, R, is half of Pmin. The wavelength used for printing has not kept pace with feature size, shrinking from 365nm for technology defined by line widths of 1 μm through 0.35 μm, then 248 nm for 0.25 μm through 0.13 μm, and over recent times to 193nm for 90nm and smaller technologies. Only certain wavelengths are available for use in lithography, because each requires a specialized light source (ArF laser for 193nm, KrF for 248 nm, moving to F2 for 157 nm). The high cost of switching light sources (which requires a complete replacement of all lithography equipment) has led to work in resolution enhancement with existing technology. One approach is off-axis imaging, which allows features to be printed at half the size of conventional lithography as shown in Figure 9.5.
Printing of fine-geometry features can be enhanced by adding subresolution assist features (SRAF), which are features in the mask that do not print themselves but are added to improve the printing of the desired features by creating interference patterns. A common example is scatter bars, as shown in Figure 9.6.
The SRAF scatter bars improve printing of the desired line but are insufficient to prevent the line-end shortening, as shown by the first part of the diagram. To help correct line-end shortening, optical proximity correction (OPC) is used to add serif-like features that force the line end to be printed where it is intended. Current generation processes sometimes use multiple sets of scatter bars. It is clear that the addition of SRAF scatter bars and OPC places restrictions on the allowed layout. For example, scatter bars cannot be placed on top of other features, or one another, and this gives rise to layout restrictions such as forbidden pitches. In some cases certain layout features will be problematic without substantial relaxation of pitch, such as that shown in Figure 9.7.
The situation shown in Figure 9.7 can be described in conventional DRC terms, but it is cumbersome. It is representative of a class of geometries that are easily described in terms of shape but are harder to describe with distances, diagonals, and other DRC staples. The DRC of the future is likely to be shape-based as a result.
SRAF scatter bars and OPC are two techniques that can be grouped under the heading of resolution enhancement technology (RET). Figure 9.8 from [Brunet 2006, personal communication] dramatically illustrates just how important RET is to modern-day chip making: without it, nothing would ever work!
These and other optical complexities have led some processes to force unidirectional criticality (i.e., all transistor gates will have the same orientation). That way, dimensions in the critical direction can be ensured with RET, whereas those in the noncritical direction will suffer if shape-based problems occur in SRAF generation. Many innovative approaches are being proposed to address this major change in layout design methodology. For a good overview, see [Liebmann 2003].
Design for manufacturability (DFM) and design for yield (DFY) mean many things, depending on the context. For the purposes of this chapter, DFM will refer to layout design changes made to improve any aspect of manufacturability, from mask making through lithography and chemical-mechanical processing (CMP). DFY will refer to techniques specifically targeted to improving manufacturing yield.
The DFM challenge can be phrased simplistically as follows: uniformity is good for manufacturability, but nonuniformity is the source of value in a design. Field programmable gate arrays (FPGAs) solve this problem through programmability of regular structures. Memories repeat bit cells and other common layouts over and over. Standard cells push the bounds of regularity but must retain enough uniformity to be manufacturable. Design rules enforce significant uniformity, but their binary nature (pass/fail) prevents them from accurately conveying the tradeoffs that exist in manufacturability.
In general, the changes involved in making a layout DFM-compliant are subtle. The standard tradeoff applied is to make changes that do not increase the area of the cell. Consider, for example, the two layouts shown in Figures 9.9 and 9.10. The single contact at A is made more manufacturable by doubling it and adding additional metal overlap. The contact at B cannot be doubled without increasing cell area. Instead, additional metal overlap is added. Contact C is already doubled, but additional overlap will help its manufacturability as well. D is an example of a small metal jog whose removal will simplify mask making and improve lithography. In each case, the effects on yield and manufacturability are minor but will add up across a die.
As explained previously, current IC manufacturing processes at current technology nodes make use of light with a wavelength of 248 nm or 193 nm for photolithography; both wavelengths are in the ultraviolet (UV) region of the spectrum, specifically the UVC region, which applies to wavelengths below about 400 nm. This means that subwavelength features are now the rule rather than the exception and require resolution enhancement technology (RET) for successful printing. The basic optical issues in photolithography were discussed in Section 9.4.
The complex optics needed for printing result in some interesting challenges. For example, the resolution enhancement for dense lines and isolated lines is different, and this can lead to gaps where neither approach works, leading to unprintable lines as shown in Figure 9.11. At 0.13 μm, an intermediate density could not be printed. At finer geometries, there can be multiple regions of such forbidden pitches.
(Courtesy of D. Pan; Graph from [Socha 2000].)
Figure 9.11. Forbidden pitches at 0.13-μm technology because of lithography effects.
Another issue that arises in photolithography is the concept of shape-based rules. We touched on this subject earlier in the discussion of Figure 9.7. We present another example here. Figure 9.12 shows an example piece of layout (polysilicon gate crossing a diffusion region). At 0.18 μm, the shape prints well enough, so no adjustment on gate width or length dimension is needed, provided that gate width is maintained (compliance with rule A). At 45 nm, the object will print correctly (where correctly in this case refers to a change in effective W of 5% or less) provided that a set of ratios of properties of A, B, and C are maintained (as shown in the upper right part of the diagram; constant k = 2 in this example). This property is difficult to code in rule-based DRC, so a set of rules has been developed limiting A, B, and C that will suffice in most cases. Now consider two assignments of values for A, B, and C, both of which are legal according to the rule-based DRC. In the first case, A = 200, B = 85, C = 90. Delta W = 5%, so the underlying “real” rule is met. Now change C from 90 to 95. Delta W goes to 10%, which could well cause a problem in the implemented circuit. This is somewhat counterintuitive, because the spacing is larger than before. An additional rule could be developed to outlaw this particular case, or extraction could be modified to take the change in W into consideration, but the situation could have been avoided in the first place if the DRC were targeted at shapes and not linear dimensions. Future generations of DRC tools will follow this approach in order to reduce complexity while simultaneously improving the ability to identify actual problem regions.
As noted previously, the more uniform an area is, the simpler it is to print. Consider, for example, Figure 9.13, which shows the polysilicon layer for a group of bit cells in an SRAM array. Notice that all gates are aligned in the same direction. The uniform density and repeated shapes allow shape-dependent variation to be effectively controlled, and this enables consistent lithography. Compare this with the polysilicon layer of an older (pre-DFM) standard cell, as shown in Figure 9.14. Some gates are horizontal and some are vertical. The density varies substantially within the cell, and there are various jogs and complex routes. Over the past few process generations, standard cell polysilicon has become increasingly uniform, primarily to improve printability. This has led to some loss of flexibility in layout (the design in Figure 9.14 is no longer allowed) but with the benefit of improved lithography.
To assist layout engineers, tools have been developed to identify lithography problem areas. These tools present a challenge for information exchange in a disaggregated supply chain. Detailed process information is required and must be applied to detailed transistor-level layout, but this needs to be done in a timely fashion (see [Aitken 2003] for additional discussion on information sharing issues). Between the 90-nm and 65-nm technology nodes, several approaches have been tried, but the industry is now converging on a method whereby foundries can encrypt some details of their processes, and tools are able to generalize some others based on their knowledge of semiconductor processes. This allows layout designers to quickly identify problem areas (hot spots) at a level the foundry deems important without either long turnaround times or risk of intellectual property (IP) loss that could happen when layouts leave an organization. Figure 9.15 presents an example of a hot spot (in this case, a potential bridging location) identified by a tool. This particular hot spot is formed because of the difficulty of applying OPC to the metal region because of the proximity of corners of the two shapes involved, as well as the empty area under the right-hand shape.
The optical region of influence for photolithography is about 1 μm. This means that patterns up to 1 μm away may affect the printability of a given shape. This figure is not reducing quickly as geometries shrink, and in some cases may actually be increasing. At 0.25-μm technology, for example, 1 μm encompasses two transistor gates and their intervening space. At 65 nm, it can cover five or more gates. In fact, the relative size of the region of influence has increased to the point where it exceeds the size of individual standard cells. This has required significant uniformity in layout rules and has led some to propose that designs be composed of larger entities (so-called bricks) where uniformity rules could be relaxed inside in favor of tradeoffs for performance or density [Pileggi 2003]. In the extreme case, this might result in FPGA-like layouts, which are notoriously inefficient in power and area but which are very regular for printability. The brick approach has been designed to mitigate these costs, but it may require different synthesis approaches than those needed for present-day standard cells.
Not all lithography issues relate directly to printing. The production of masks is itself a complex process, and some rules are present to reduce the cost of making masks. Also, once lithography itself is complete (the patterns have been printed on a silicon wafer), etch issues come into play. These tend to be at the wafer level and largely result from the chemical challenges associated with thin films. For example, the outer edges of a wafer spin much faster than the center. This is just one of many such phenomena that must be taken into consideration by process engineers. Other examples include mechanical issues (stress), structural issues (contact overlap of gate, leading to salicide formation challenges), and electrical issues (variations in R or C that are strongly influenced by manufactured line width or thickness). Additional physical effects that must be considered include chemical mechanical polishing (CMP) and physical/chemical interactions such as ion implant.
Not surprisingly, photolithography remains the biggest challenge in current processes and is thus the target of most DFM/DFY. One technique being explored at the present time to improve DFM/DFY is immersion lithography, and this is expected to be used in most 45-nm processes. Immersion lithography takes advantage of the fact that a liquid can have a refractive index greater than 1, and thus improve resolution over air or a vacuum. The maximum expected numerical aperture for water-based immersion is 1.35, versus 1.0 for dry lithography. More esoteric materials can give the numerical aperture (NA) values of up to 1.65 [Hand 2005]. In addition, lithography using extreme ultraviolet (EUV) light, probably at 13.5-nm wavelength, has been proposed for patterning instead of the current 193-nm or 157-nm wavelength.
Other techniques being considered include multiple exposure methods, where different features are patterned separately. One interesting variant has been proposed in [Fritze 2005], where a completely regular pattern is generated initially by using maskless interference patterns and is then selectively “erased” where necessary to generate particular features using lower resolution mask-based lithography.
Lithography challenges become design challenges in two primary areas: (1) physical IP design (library design) and (2) during routing. DFM can be considered as part of library design. Certain structures are inherently vulnerable to optical effects and therefore allowance should be made in their design to ensure that subsequent OPC will be able to treat them correctly. An example is line-end shortening of polysilicon as shown in Figure 9.6. The presence of a nearby structure can prevent OPC correction, resulting in an incorrectly printed object. Optical issues undoubtedly pose a significant challenge in IP development for current process generations.
Critical area is a common metric used to evaluate the susceptibility of a given layout to defects [Shen 1985]. The critical area for bridging between wires is the area where the center of a particle of given radius could land and cause a short circuit between two wires (such short circuits are often termed simply “shorts”). In Figure 9.16, the critical area for a 0.5-micron particle is 0.2 square microns, as shown.
Critical area by itself is not a particularly significant metric. It needs to be combined with a defect distribution in order to quantify the relative importance of specific defects.
Critical area is a monotonically increasing function of particle size, because bigger particles cause more defects. Particle size itself is usually modeled as an inverse cube distribution, where a particle of size 2X is 1/8 as likely as a particle of size X. Critical area is affected by layout features such as layer density and complexity.
Figure 9.17 shows a defect size distribution for defect sizes ranging from 0.12μm to 0.5μm. The “minimum spacing” DRC rule is set at a value where the foundry believes that good yield can be achieved across a wide variety of designs. At a “recommended spacing” that is significantly higher than the minimum spacing, defect probability is reduced by a factor of about 4. Under some circumstances where a significant area or performance benefit can be achieved, process control or design requirements justify a much tighter “waiver spacing” where defect probability is higher by a factor of nearly 3.
Combining the critical area distribution (which progresses monotonically from 0 to 100% as defect size is increased) with a defect size distribution as shown in Figure 9.17 leads to the concept of weighted critical area, where critical area at certain defect sizes is significantly more important than at others. This is shown in Figure 9.18. Weighted critical area peaks at a value slightly above the minimum DRC separation and then tapers off quickly, such that at double the minimum separation it becomes less important.
From a design standpoint, the simplest approach to improve critical area is to increase wire spacing, but as the preceding section described, this can sometimes lead to lithography problems because of forbidden pitches. In addition, because improving critical area leads to an overall area increase, it may not always be clear that this tradeoff is a good one. Defect density in a fab will change over time, but area cannot be recovered once it has been lost.
The “critical area” concept can also be extended to cover missing material (by measuring the area susceptible to a circular open of a given fixed size), contact or via failure rates, and overlap issues.
As an alternative to weighted critical area, sometimes a single defect size value can be chosen, such as the 50th percentile layer defect size (the size where half the expected defect particles are larger and half are smaller) and critical area calculated from that.
Making changes for DFM reasons that increase area or lower performance cannot be done without accurate metrics to quantify the tradeoffs. A yield metric must be able to adapt to changing process conditions in order to be useful over time.
One major difficulty is that a manufacturing process is not static: as problems are found, they are fixed; process recipes are altered; equipment ages or is replaced. Consider the following example. Suppose two metal-1 layouts are available for a certain cell, shown in Figure 9.19. If the target process is highly susceptible to metal-1 shorts, the ideal layout will be the one on the left (L). On the other hand, if contacts are more of a problem in this particular process at this time, then the better layout will be the one on the right (R).
Consider the case where initial process analysis shows that shorts are the bigger problem, and layout L is selected as part of a cell library because its yield, YL, will be better than that of layout R, YR (YL >YR). If, after some time, process engineers identify the issue that causes the shorts, then although both YL and YR will improve, YR could potentially become greater than YL (YR >YL). A single yield number associated with either would be inadequate. Recharacterization of the library might help a subsequent design, but it is too late for one that has already gone into production. Some process changes are predictable in advance (e.g., a steady decline in defect density over a product lifetime), whereas others are not (e.g., unpredictable changes caused by moving to a different equipment set).
One way of looking at yield variation over time in more detail is to consider graphs such as the one shown in Figure 9.20, which are commonly used to discuss the relative weighting of feature-limited yield (systematic effects) versus defect-limited yield (random effects) [Guardiani 2005]. The graph conveys an important point, namely that feature-limited yield is more important in recent processes than it has been historically, but it is also somewhat misleading in that it implies that these numbers are fixed in time.
In reality, however, yield is not fixed in time. Process engineers expend significant effort identifying systematic and random problems and working to fix them [Wong 2005] [May 2006]. Feature-limited yield, for example, can be addressed either by modifying the process to make the feature print (through RET changes or recipe changes) or by making the feature illegal by forcing a DRC change. In both cases, yield loss caused by the individual feature will decline. Similarly, random yield can be improved with reduction in defect density, because of a cleaner process or equipment change for example. Again, yield will improve over time. Process engineers often use a Pareto chart (a histogram, sorted by occurrence) to identify the most immediate problem, as shown in Figure 9.21. Once this problem has been tackled, then the next most significant one may be addressed, etc.
As a result, both random and systematic yield improve over time. Early in a process life cycle, most yield loss is systematic, but eventually, systematic yield loss is reduced to the point at which random yield loss becomes more important. The difference between current processes and their ancestors is that economic pressure is driving process release earlier in the life cycle. Figure 9.22 shows this trend. Thus, the curve in Figure 9.20 is representative at process release time, but over time all processes will tend toward being limited by defects rather than systematic effects.
Just as design and manufacturing have long been considered independently, the interaction between testability and yield has been neglected. Test and design have evolved over the history of integrated circuits as separate topics, though of mutual interest. Design for testability (DFT) is concerned about structures and methods to improve detection of defective parts. Defects cause faults, which are deterministic, discrete changes in circuit behavior. Design is not concerned with faults. Rather, design worries about parametric variation, manifesting itself as design margin. This has led to the development of DFM, which is concerned with structures and methods to improve manufacturability and yield. This state of affairs is illustrated in Figure 9.23. Test is concerned with distribution 2, while design is concerned with distribution 1.
It has always been known that this separation is artificial, but it has remained because it is convenient. The first signs of a breakdown came in IDDQ test (which tests parts by measuring their leakage current). Results such as those in [Josephson 1995] and [Nigh 1997] showed that there was no readily identifiable breakpoint between good and bad parts, leading to questions about the usefulness of IDDQ test [Williams 1996].
Rather than being an anomaly, leakage variability, as highlighted by IDDQ test, has proven to be an indicator of the future. Measurement criteria such as circuit delay and minimum operating voltage are now suffering from the same inability to distinguish parts with defects from inherent variability. While it may be argued that there is no need to discriminate as both are “bad,” it is clear that choices made in these matters will directly affect yield and quality.
Historically, testing has attempted to distinguish between “defects” (random events that cause silicon failure) and “design errors” (problems with a design that prevent it from functioning correctly). Process variation (sometimes referred to as parametric variation) occupies a middle ground between these two: design margin will account for some amount of variation, but beyond that a circuit will fail to operate. Had additional margin been provided, the design would have worked, so it may be considered to be a design error, but the excess variation can equally well be thought of as a process defect.
Variability occurs throughout a process, lot-to-lot, wafer-to-wafer, die-to-die, and intradie [Campbell 2001] [Segura 2004]. Three primary sources of variation are considered here: (1) transistor length variation, (2) gate dielectric thickness variation, and (3) ion implant variation.
Length variation across a chip tends to be continuous: a map of variation versus X,Y location will show a continuous pattern. Transistors with shorter channel lengths will be faster and leakier, while those with longer channels will be slower but less leaky. In most cases, transistor models will not account for the X,Y dependency of this variation, but will instead assume that all variation occurs within the boundaries of the device models as supplied to the designers (the familiar fast and slow silicon corners). Design margin is needed to account for this variability.
Gate dielectric thickness directly affects the electric field of a transistor, so variation can significantly change its behavior. Wafer-to-wafer variation can be caused by changes in temperature and time in the furnace during the dielectric formation process. Because gate dielectric thickness is so vital, great care is taken to ensure uniformity, and localized variation is minimal; even so, dielectric variation does contribute to leakage variation, especially at low temperatures where gate leakage is more dominant.
Unlike length and gate dielectric variation, ion implant variation is localized. The distribution of implanted ions is roughly Gaussian and depends on the ion’s energy. For lighter ions such as Boron, lower implant energy results in higher variability [Campbell 2001]. Bombarding ions also scatter beyond masked areas, resulting in changes to diffused areas and deflecting off of nearby structures, thereby creating higher variability near well boundaries. Implant variation between transistors leads to threshold voltage variation, which in turn causes changes to both leakage and delay as shown in Figure 9.24. As a result, leakage variation caused by implant variation can be assumed to be independent on a per-cell basis.
Small variations in threshold voltage lead to substantial changes in leakage, but relatively minor changes in performance. For example, an 85mV decrease in VT might lead to 10% improvement in drive current, at the cost of a 10× increase in leakage in a typical 0.13-μm process.
Variability can be considered at several levels of IC production: lot-to-lot, wafer-to-wafer within a lot, die-to-die within a wafer, and within a die. The first three are often grouped together as interdie variation, whereas the last is referred to as intradie variation. Process engineers spend significant time analyzing sources of variability. They check for variation in localized test structures (e.g., ring oscillators or specially designed transistors) and compare properties visually. Examples of silicon properties that might vary include transistor line width, roughness of line edges, and the thickness of layers such as metal, dielectric, and polysilicon.
Figure 9.25 shows an example of a property varying on a reticle-by-reticle basis. In this case, the property (e.g., line thickness) is at its strongest in the upper left die of each 2 × 2 reticle and at its weakest in the lower right die. Figure 9.26, on the other hand, shows a property that varies on a wafer-by-wafer basis, so that it is strongest in the center of the wafer and then progressively weaker as it works outward. Notice that the variation is not absolutely equal in all directions. Other factors (such as measurement accuracy and random effects) can also influence these results.
Wafer-level variability is not always perfectly centered. It may originate in one region of the die, as shown in Figure 9.27, or follow stripes or bands, or any of a myriad of other possibilities depending on the physical and chemical phenomena underlying the variability. See [Campbell 2001] for additional discussion.
As discussed previously, variability at some point can be so extreme that it becomes defectivity (a term meaning “manifestation of defects”). For example, if via resistance becomes too high, current passing through wires will simply fail to function at the circuit’s rated speeds. There is no predefined point where a given property passes from variation to defect; the choice is fab dependent, design dependent, and in some cases application dependent. When deciding whether variation is caused by a defect or the result of simple variation, “neighborhood” context is sometimes used. This is shown in Figure 9.28, which modifies Figure 9.27 slightly to show how some extreme measures are more likely than others to be the result of defects. For additional information, see [Madge 2002] and [Maly 2003].
New issues in manufacturing are requiring visibility earlier in the design cycle. It is no longer sufficient to assume that adjustments for optical effects can be made after tapeout on DRC clean layouts. Neither can designers assume that the physical effects of implant variation are negligible in memory design nor that the measurement environment and equipment have no influence in design timing. As a result, designers must consider a multiplicity of factors as part of optimization.
For physical IP designers, this means developing methodologies and metrics to take into account yield, manufacturability, and test, to ensure that tradeoffs can be made correctly. For example, doubling contacts improves yield caused by contact failures but increases critical area, thereby reducing yield caused by metal shorts, and the extra capacitance added will lower performance and may even increase sensitivity to variability in the transistors. Effective design in these circumstances requires the ability to quantify and measure all these criteria.
In addition to increased cooperation between manufacturing and design, design for excellence (DFX), which includes DFM, DFY, and DFT, requires increased understanding at higher system levels too. This ranges from simple concepts (some transistors are involved in critical paths, some are not) to more complex interactions between variability, performance targets, power consumption, and more. For example, consider the microarchitectural approach used in Razor [Ernst 2004], where the processor is designed to operate with transient errors that are corrected by execution rollback. This allows the circuits to operate at a lower power level or higher frequency than they might otherwise, but it cannot be achieved without significant interaction between the physical IP and the processor architecture.
This discussion follows what was presented in [Aitken 2006b]. Each of the classic standard cell properties has associated metrics. Area is the simplest and is usually measured in square microns. Timing was initially expressed as a simple delay, typically the propagation delay of the cell in nanoseconds. As technology advanced, this simple delay measurement became inadequate. Delay was next calculated for multiple process corners (slow, typical, and fast), to account for process spread. As wire delay has become a more important component of overall delay, more complex delay models have been developed, including equation-based timing, nonlinear delay tables, current source modeling, etc. It is not uncommon for an inverter to have several hundred delay measurements associated with it. Similarly, power metrics have evolved from a single number representing dynamic current to include leakage, load-dependent power, state-dependent leakage, etc.
These metrics share two important qualities: (1) they move over time toward increasing accuracy, and (2) there is an agreed-upon procedure for calculating them (de facto standard). Both qualities are needed to assure working silicon across multiple designs and designers. The actual delay of a single standard cell is rarely measured for a chip. Instead, it is the cumulative delay effect of critical paths made up of many of these cells connected together that matters. Similarly, the power associated with a given cell can be identified only with special hardware, but cumulative power consumption of all cells is what matters for battery life, heat dissipation, etc. If the low-level metrics were unreliable, cumulative calculations would be meaningless.
The process of calculating metrics for standard cells is known as characterization. In general, SPICE is used as the “gold standard” for characterization, because it has proven over time to describe cell behaviors, especially delay, accurately enough to enable high-volume manufacturing. Table 9.1 summarizes the relationship between the important standard cell properties and their associated metrics. For each property, the metric used to calculate that property is listed, along with the level of accuracy that successful manufacturing requires. Also included are the accuracy that is available in state-of-the-art technology and an “implications” column, which comments on the issues facing efforts to match accuracy to requirements.
Table 9.1. Standard Cell Metrics
Property | Metric | Accuracy Needed | Accuracy Available | Implications |
|---|---|---|---|---|
Area | Square microns | High | High | Self-evident to calculate; chip area is a property of library routability |
Power | Dynamic and leakage current | Medium | Medium to high; highly dependent on the SPICE model; challenging for leakage because of process variation | Except in special cases, only the cumulative effect of thousands of cells is measurable, not individual values |
Performance | Delay | High | High, but requires complex analysis at the cell, block, and chip level; dependence on variation not fully understood | Performance depends on a small number of cells (typically 10–100) forming a set of critical and near-critical paths, so accuracy is vital |
Manufacturability | Yield | Depends | Depends | Failure of a single cell can cause a chip to fail, but failure rates depend on factors that are difficult to characterize; catastrophic failure can be predicted with some accuracy, but interacting failure modes are difficult to model, let alone predict |
The last row in Table 9.1 is for yield and manufacturability. The entries are vague because there is much that is not universally agreed upon for yield and standard cells, including a suitable metric (percentage or number of good dies per wafer, across lots or per lot, etc.), an objective means of calculating the metric, and even the data that would be used in the calculation.
Ideally, a yield number could be associated with each standard cell and a synthesis tool could use this yield number, along with power, performance, and area to produce a circuit optimal for the designer’s needs. Several efforts have been made in this area (e.g., [Guardiani 2004] and [Nardi 2004]), and it is certainly a worthy goal to strive for.
The major difficulty with the ideal case, as noted earlier, is that a manufacturing process is not static (see Figure 9.22). As problems are found, they are fixed. A single yield number associated with any specific problem would be inadequate. Recharacterization of the library might help a subsequent design, but it is too late for one that has already gone to silicon. Some process changes are predictable in advance (e.g., steady decline in defect density over a product lifetime), whereas others are not (e.g., changes caused by moving to a different equipment set).
A yield metric must be able to adapt to changing process conditions in order to be useful over time.
A second issue is objectivity. Before embarking on a design, it is common for designers to evaluate several libraries and to select the one(s) that provide the best results for the target design. As we have shown, standard library metrics have objective definitions: given a SPICE model and set of assumptions (e.g., delay of a transition is the time taken for a signal to move from 10% to 90% of the power rail voltage), then the simulated delay of a cell should be the same for a given output load, regardless of who calculates it. Yield, on the other hand, is inherently statistical. The yield of a cell depends on its surrounding context, including neighboring cells, position on a die, position in a reticle, and position on a wafer. Exact values for each of these are unlikely, so approximations must be used, based on some test data. Different organizations may have different access to data, may have used different methods to collect it, and may have collected it at different times. Comparisons can therefore be challenging. For example, critical area is a relatively objective metric, but to be converted to yield it must include a failure rate, and this is subject to all the difficulties just mentioned as well as commercial sensitivity.
Despite the challenges, there are a number of potential yield metrics that can be useful in design for yield (DFY).
Critical area (see Section 9.5.2) is one such metric used to evaluate the susceptibility of a given layout to defects. Figures 9.29 and 9.30 show two partial metal-1 layouts for a three-input NOR gate. The critical area for shorts is much smaller for layout 1 (Figure 9.29) than that of layout 2 (Figure 9.30), showing that even for simple functions critical area can be an important criterion.
Combining critical area with a particle distribution leads to weighted critical area, as shown in Figure 9.18. An example is given in Figure 9.31. Similar to other outlier-based analyses [Daasch 2001], the extreme cells at either end of the curve should be subjected to additional analysis—those in a high critical area to improve yield and those in a low critical area to assess layout effectiveness.
Defining a metric for resolution enhancement technology (RET) is complicated by several factors. First, recipes are foundry proprietary. Changes in yield and manufacturability give foundries an edge over their competitors, so RET recipes are jealously guarded. Current generation tools use data encryption to help with this issue. Second, optical proximity correction (OPC) and phase shift mask (PSM) rules change frequently. Even if it were possible to update library artwork for every revision, this would disrupt user design flows and thus be unacceptable. Finally, there is a data volume issue: post-OPC layouts contain significantly more shapes and are thus significantly larger than pre-OPC data. For users already burdened by huge tape-out file sizes, including OPC information with a library is unacceptable. Still, there is some hope for such metrics, and several commercial vendors have proposed them.
Because DFM is complicated, foundries have developed special rules and recommendations for DRC. They fall into several major categories, including the following:
Improved printability. These include line end rules, regularity requirements, diffusion shape near gate rules, and contact overlap rules, among others.
Reduced mask complexity. These include rules about “jogs,” or small changes in dimensions, structures, which could confuse line end algorithms, and space needed for phase-shift mask features.
Reduced critical area. These include relaxed spacing, increased line thickness, etc.
Chemical-mechanical processing (CMP) rules. These include density fill rules, as well as layer relationship rules.
Performance related rules. These include extra source width to reduce current crowding, symmetrical contacts around the gate, etc. The collective result of these rules is to ensure that transistors perform as intended.
Sometimes a rule serves multiple purposes, and sometimes the purposes conflict. For example, increasing contact overlap improves yield but also increases critical area for shorts. To allow numerical treatment of rules, a weighted approach is desirable. Each rule can be given a certain weight, and relative compliance can be scored. An example is given in Table 9.2 for four simplified polysilicon rules and a simple scoring system: 0% for meeting minimum value, 50% credit for an intermediate value, 100% for a recommended value; and the inverse of these values for “negative” rules, of which “avoid jogs” is an example—any noncomplying structures are subtracted from the score. Note that the rule values are artificial and are not meant to represent any actual process.
Table 9.2. Rules Example
Rule | Weight | Scoring | |||
|---|---|---|---|---|---|
0% | 50% | 100% | |||
1. | Increase line end | 0.4 | 0.05 | 0.1 | 0.15 |
2. | Avoid jogs in polysilicon | –0.3 | Jog > 0.1 | Jog > 0.05 | Jog < 0.05 |
3. | Reduce critical area for polysilicon gates | 0.2 | 0.15 spacing | 0.2 spacing | 0.25 spacing |
4. | Maximize contact overlap | 0.1 | 0.05 on two sides | 0.05 on three sides | 0.05 on four sides |
Figure 9.32 shows a sample layout, together with areas that comply with the minimum rule (e.g., 1B is a minimum line end, 4B is a minimal contact) and the recommended rule (1A meets the recommended value, 4A is an optimal contact). In scoring this cell, there are 6 line ends, 2 minimum (0%), 1 intermediate (50%), and 3 recommended (100%), for a total of 3.5 out of 6. There are 4 small jogs, for a score of –4. Gate spacing is scored at 2.5 out of 4 (two recommended, one intermediate), with contacts at 1 out of 3. Weighting these values gives a total of 0.8 out of a possible total of 3.5. Minor changes to the cell layout, as shown in Figure 9.33, increase the weighted total to 2.65, much closer to the ideal. None of these changes increased cell area. Improving some values further would require an area increase to avoid violating other rules. These are indicated by “C.” The results are summarized in Table 9.3.
Table 9.3. Metrics for Example Layouts
Layout 1 | Layout 2 | Ideal Layout | |||||
|---|---|---|---|---|---|---|---|
Weight | Raw | Weighted | Raw | Weighted | Raw | Weighted | |
Rule 1 | 0.4 | 3.5 | 1.4 | 4.5 | 1.8 | 6 | 2.4 |
Rule 2 | 0.3 | –4 | –1.2 | 0 | 0 | 0 | 0 |
Rule 3 | 0.2 | 2.5 | 0.5 | 3 | 0.6 | 4 | 0.8 |
Rule 4 | 0.1 | 1 | 0.1 | 2.5 | 0.25 | 3 | 0.3 |
Total | 1 | 0.8 | 2.65 | 3.5 | |||
Building a fractional compliance metric such as the one described here is a straightforward process using the scripting capability of modern DRC tools. Similar scripting methods have been shown in [Pleskacz 1999] to calculate critical area. The challenge is to determine an effective set of weights for the various rules. Additionally, there are some DFM requirements that cannot readily be expressed in either rule or metric format, and these still require hand analysis. For example, a DRC-clean structure might be tolerable in a rarely used cell but be flagged as a potential yield limiter in a frequently used cell.
As complementary metal oxide semiconductor (CMOS) processes evolve, design for manufacturability (DFM) and design for yield (DFY) will become increasingly important, and their interaction with design for testability (DFT) will also become critical. The combination of these and other effects is classified as design for excellence (DFX) in this chapter. A key aspect of DFX will be the ability to cope with ever increasing amounts of variability that will be encountered with reduced feature sizes. For example, the number of dopant atoms in a minimum-sized channel at 65-nm process node is on the order of 200, gate oxides are four to five molecules thick, and resolution enhancement continues to push physical limits. Innovative approaches continue to be developed to counter this complexity. Some of the more recent promising approaches include the use of regular fabrics to simplify processing [Pileggi 2003], radically restricted layout practices [Liebmann 2003], and statistical approaches to timing [Visweswariah 2004].
This chapter has attempted to bring forth several important issues regarding design for manufacturability and yield enhancement. Among these are the following:
The economics of CMOS scaling and Moore’s law have driven the IC industry to a disaggregated supply chain model, with increasing consolidation in the various specialty areas.
“Yield” has no single objective definition but is measured and modeled in different ways depending on the situation.
Overall yield is composed of five subcategories: systematic yield, parametric yield, defect-related yield, design-related yield, and test-related yield.
The possibility of repair introduces additional complexity to yield calculations, but with the benefit of recovering parts that would otherwise be unusable.
Photolithography has moved well into the realm of subwavelength features and now requires significant resolution enhancement technology and subresolution enhancement features.
Uniformity and regularity are key to successful DFM.
A variety of useful metrics can be developed for DFM, including DRC-derived metrics, shape-based metrics, CMP-based metrics, and weighted critical area.
Manufacturing processes are dynamic, so yield enhancement must evolve with the process and is subject to change over time.
As relative variation increases, DFM, DFY, and DFT are becoming increasingly intertwined.
Variability contains deterministic and random components. Control and measurement can quantify and limit the deterministic portion but can never eliminate the random portion.
The demise of Moore’s law and CMOS scaling has been predicted for more than 20 years, but innovation has so far trumped the detractors. The effective use of design in order to improve manufacturability and yield has always been a competitive advantage for those who have tried it and will continue to be a vital component of IC design and manufacturing. As DFX evolves, it will absorb new areas, including variability, reliability, and power management.
9.1 | (Introduction) Redraw Figure 9.1 to include semiconductor equipment vendors and their relationship to foundries. What other industries could form part of this ecosystem? |
9.2 | (Yield) Defect density in a Poisson process drops from 1 percm2 to 0.5 percm2.
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9.3 | (Photolithography) A lens has a numerical aperture of 0.5 for light with a wavelength of 193 nm.
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9.4 | (Photolithography) Uniformity in layout is desirable for lithography purposes because it enables better printing of a reduced number of shapes. It is also helpful for chemical-mechanical polishing (CMP) because it allows for consistent etch rates. Which of the following layouts is better for CMP and why? |
9.5 | (Critical Area) Which of the preceding layouts has lower critical area for shorts because of particles of a size equal to twice the wire width? |
9.6 | (Critical Area) Two well-known methods for calculating critical area are “dot throwing,” where random dots are inserted in a layout to determine if they join two lines, and “polygon expansion,” where rectangle boundaries are enlarged and then subsequently analyzed to see if shorts are created. Which approach is likely to arrive at an answer faster for a large (e.g., chip size) layout? |
9.7 | (Variability) Why are the outlying red dies in Figure 9.28 more likely to be caused by defects than those in the main group? Are the ones in the main group known to be defect free? |
9.8 | (DFX) How would the “ideal” layout described in Table 9.3 differ from that shown in Figure 9.33? |
The author wishes to thank Dr. Lars Liebmann of IBM, Dr. Jean-Marie Brunet of Mentor Graphics, and Professor David Pan of the University of Texas at Austin for their contributions to this chapter, as well as Dr. Anne Gattiker of IBM, Dr. Anurag Mittal of ARM, and Dr. Harry Oldham of ARM for their valuable review comments.